10-Bit, 200 MSPS/250 MSPS

1.8 V Analog-to-Digital Converter

AD9601
FEATURES APPLICATIONS
SNR = 59.4 dBFS @ fIN up to 70 MHz @ 250 MSPS Wireless and wired broadband communications
ENOB of 9.7 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) Cable reverse path
SFDR = 81 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) Communications test equipment
Excellent linearity Radar and satellite subsystems
DNL = 0.2 LSB typical Power amplifier linearization
INL = 0.2 LSB typical
FUNCTIONAL BLOCK DIAGRAM
CMOS outputs RBIAS PWDN AGND AVDD (1.8V)
Single data port at up to 250 MHz
Demultiplexed dual port at up to 2 × 125 MHz
REFERENCE AD9601
700 MHz full power analog bandwidth
CML DRVDD
On-chip reference, no external decoupling required
DRGND
VIN+
Integrated input buffer and track-and-hold TRACK-AND-HOLD
VIN–
Low power dissipation ADC 10 OUTPUT 10
10-BIT STAGING Dx9 TO Dx0
274 mW @ 200 MSPS CORE LVDS

322 mW @ 250 MSPS CLK+ CLOCK OVRA

CLK– MANAGEMENT
Programmable input voltage range OVRB

1.0 V to 1.5 V, 1.25 V nominal SERIAL PORT

1.8 V analog and digital supply operation DCO+
DCO–
Selectable output data format (offset binary, twos

07100-001
complement, Gray code) RESET SCLK SDIO CSB

Clock duty cycle stabilizer Figure 1.

Integrated data capture clock

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

The AD9601 is a 10-bit monolithic sampling analog-to-digital 1. High Performance—Maintains 59.4 dBFS SNR @ 250 MSPS
converter optimized for high performance, low power, and ease with a 70 MHz input.
of use. The product operates at up to a 250 MSPS conversion 2. Low Power—Consumes only 322 mW @ 250 MSPS.
rate and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary func- 3. Ease of Use—CMOS output data and output clock signal
tions, including a track-and-hold (T/H) and voltage reference, allow interface to current FPGA technology. The on-chip
are included on the chip to provide a complete signal reference and sample-and-hold provide flexibility in
conversion solution. system design. Use of a single 1.8 V supply simplifies
system power supply design.
The ADC requires a 1.8 V analog voltage supply and a differen-
tial clock for full performance operation. The digital outputs are 4. Serial Port Control—Standard serial port interface supports
CMOS compatible and support either twos complement, offset various product functions, such as data formatting, power-
binary format, or Gray code. A data clock output is available for down, gain adjust, and output test pattern generation.
proper output data timing. 5. Pin-Compatible Family—12-bit pin-compatible family
Fabricated on an advanced CMOS process, the AD9601 is offered as the AD9626.
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
AD9601

TABLE OF CONTENTS
Features .............................................................................................. 1 Clock Input Considerations...................................................... 17
Applications....................................................................................... 1 Power Dissipation and Power-Down Mode ........................... 18
Functional Block Diagram .............................................................. 1 Digital Outputs ........................................................................... 18
General Description ......................................................................... 1 Timing—Single Port Mode ....................................................... 19
Product Highlights ........................................................................... 1 Timing—Interleaved Mode....................................................... 19
Revision History ............................................................................... 2 Layout Considerations................................................................... 20
Specifications..................................................................................... 3 Power and Ground Recommendations ................................... 20
DC Specifications ......................................................................... 3 CML ............................................................................................. 20
AC Specifications.......................................................................... 4 RBIAS........................................................................................... 20
Digital Specifications ................................................................... 5 AD9601 Configuration Using the SPI ..................................... 20
Switching Specifications .............................................................. 6 Hardware Interface..................................................................... 21
Timing Diagrams.......................................................................... 7 Configuration Without the SPI ................................................ 21
Absolute Maximum Ratings............................................................ 8 Memory Map .................................................................................. 23
Thermal Resistance ...................................................................... 8 Reading the Memory Map Table.............................................. 23
ESD Caution.................................................................................. 8 Reserved Locations .................................................................... 23
Pin Configurations and Function Descriptions ........................... 9 Default Values ............................................................................. 23
Equivalent Circuits ......................................................................... 11 Logic Levels................................................................................. 23
Typical Performance Characteristics ........................................... 12 Evaluation Board ............................................................................ 25
Theory of Operation ...................................................................... 16 Outline Dimensions ....................................................................... 31
Analog Input and Voltage Reference ....................................... 16 Ordering Guide .......................................................................... 31

REVISION HISTORY
11/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 32
 AD9601

SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, single port output mode, DCS enabled,
unless otherwise noted.

Table 1.
AD9601-200 AD9601-250
Parameter 1 Temp Min Typ Max Min Typ Max Unit
RESOLUTION 10 10 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed
Offset Error 25°C 4.0 4.0 mV
Full −12 +12 −12 +12 mV
Gain Error 25°C 1.4 1.4 % FS
Full −2.1 +4.5 −2.1 +4.5 % FS
Differential Nonlinearity (DNL) 25°C 0.2 0.2 LSB
Full −0.5 +0.5 −0.5 +0.5 LSB
Integral Nonlinearity (INL) 25°C 0.2 0.2 LSB
Full −0.5 +0.5 −0.5 +0.5 LSB
TEMPERATURE DRIFT
Offset Error Full 8 8 μV/°C
Gain Error Full 0.021 0.021 %/°C
ANALOG INPUTS (VIN+, VIN−)
Differential Input Voltage Range 2 Full 0.98 1.25 1.5 0.98 1.25 1.5 V p-p
Input Common-Mode Voltage Full 1.4 1.4 V
Input Resistance (Differential) Full 4.3 4.3 kΩ
Input Capacitance 25°C 2 2 pF
POWER SUPPLY
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
Supply Currents
IAVDD 3 Full 133 142 157 167 mA
IDRVDD3/Single Port Mode 4 Full 19 20 22 24 mA
IDRVDD3/Interleaved Mode 5 Full 16 18 mA
Power Dissipation3 Full mW
Single Port Mode4 Full 274 291 322 344 mW
5
Interleaved Mode Full 268 315 mW
Power-Down Mode Supply Currents
IAVDD Full 40 40 μA
IDRVDD Full 170 170 22 μA
Standby Mode Supply Currents
IAVDD Full 19 19 mA
IDRVDD Full 170 170 22 μA
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.
3
IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate.
4
Single data rate mode; this is the default mode of the AD9601.
5
Interleaved mode; user-programmable feature. See the Memory Map section.

Rev. 0 | Page 3 of 32
AD9601
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. 1

Table 2.
AD9601-200 AD9601-250
Parameter 2 Temp Min Typ Max Min Typ Max Unit
SNR
fIN = 10 MHz 25°C 59.5 59.4 dB
Full 58.5 57.8 dB
fIN = 70 MHz 25°C 59.3 59.4 dB
SINAD
fIN = 10 MHz 25°C 59.5 59.4 dB
Full 58.5 57.7 dB
fIN = 70 MHz 25°C 59.3 59.4 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz 25°C 9.6 9.7 Bits
fIN = 70 MHz 25°C 9.6 9.7 Bits
WORST HARMONIC (SECOND OR THIRD)
fIN = 10 MHz 25°C 84 84 dBc
Full 77 72 dBc
fIN = 70 MHz 25°C 78 81 dBc
WORST OTHER (SFDR EXCLUDING SECOND AND THIRD)
fIN = 10 MHz 25°C 88 86 dBc
Full 80 75 dBc
fIN = 70 MHz 25°C 87 85 dBc
TWO-TONE IMD
170.2 MHz/171.3 MHz @ −7 dBFS 25°C 81 81 dBFS
ANALOG INPUT BANDWIDTH 25°C 700 700 MHz
1
All ac specifications tested by driving CLK+ and CLK− differentially.
2
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

Rev. 0 | Page 4 of 32
 AD9601
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

Table 3.
AD9601-200 AD9601-250
Parameter 1 Temp Min Typ Max Min Typ Max Unit
CLOCK INPUTS
Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 1.2 1.2 V
Differential Input Voltage Full 0.2 6 0.2 6 V p-p
Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 AVDD − 0.3 AVDD + 1.6 V
Input Common-Mode Range Full 1.1 AVDD 1.1 AVDD V
High Level Input Voltage (VIH) Full 1.2 3.6 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 0 0.8 V
Input Resistance (Differential) Full 16 20 24 16 20 24 kΩ
Input Capacitance Full 4 4 pF
LOGIC INPUTS
Logic 1 Voltage Full 0.8 × VDD 0.8 × VDD V
Logic 0 Voltage Full 0.2 × AVDD 0.2 × AVDD V
Logic 1 Input Current (SDIO) Full 0 0 μA
Logic 0 Input Current (SDIO) Full −60 −60 μA
Logic 1 Input Current Full 55 50 μA
(SCLK, PDWN, CSB, RESET)
Logic 0 Input Current Full 0 0 μA
(SCLK, PDWN, CSB, RESET)
Input Capacitance 25°C 4 4 pF
LOGIC OUTPUTS
High Level Output Voltage Full DRVDD − 0.05 DRVDD − 0.05 V
Low Level Output Voltage Full GND + 0.05 GND + 0.05 V
Output Coding Twos complement, Gray code, or offset binary (default)
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

Rev. 0 | Page 5 of 32
AD9601
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

Table 4.
AD9601-200 AD9601-250
Parameter (Conditions) Temp Min Typ Max Min Typ Max Unit
Maximum Conversion Rate Full 200 250 MSPS
Minimum Conversion Rate Full 40 40 MSPS
CLK+ Pulse Width High (tCH) Full 2.15 2.4 1.8 2.0 ns
CLK+ Pulse Width Low (tCL) Full 2.15 2.4 1.8 2.0 ns
Output, Single Data Port Mode 1
Data Propagation Delay (tPD) 25°C 3.7 3.7 ns
DCO Propagation Delay (tCPD) 25°C 3.4 3.4 ns
Data to DCO Skew (tSKEW) Full 0 0.3 0.55 0 0.3 0.55 ns
Latency Full 6 6 Cycles
Output, Interleaved Mode 2
Data Propagation Delay (tPDA, tPDB) 25°C 3.5 3.5 ns
DCO Propagation Delay (tCPDA, tCPDB) 25°C 3.0 3.0 ns
Data to DCO Skew (tSKEWA, tSKEWB ) Full 0 0.5 1.1 0 0.5 1.1 ns
Latency Full 6 6 Cycles
Standby Recovery 25°C 250 250 ns
Power-Down Recovery 50 50 μs
Aperture Delay (tA) 25°C 0.1 0.1 ns
Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 ps rms
1
See Figure 2.
2
See Figure 3.

Rev. 0 | Page 6 of 32
 AD9601
TIMING DIAGRAMS
N+2
N+1
N+3
N
N+4
N+8
tA
N+5
N+6 N+7
tCLK = 1/fCLK
CLK+

CLK–
tCPD
DCO–

DCO+
tSKEW
tPD

07100-042
DAX N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2

Figure 2. Single Port Mode

N+2
N+1
N+3
N
N+4
N+8
tA
N+5
N+6 N+7
tCLK = 1/fCLK
CLK+

CLK–
tCPDA tCPDB
DCO+

DCO–
tSKEWA
tPDA

DAX N–6 N–4 N–2 N N+2

tSKEWB

tPDB

07100-043
DBX N–7 N–5 N–3 N–1 N+1

Figure 3. Interleaved Mode

Rev. 0 | Page 7 of 32
AD9601

ABSOLUTE MAXIMUM RATINGS

Table 5. Stresses above those listed under Absolute Maximum Ratings
Parameter Rating may cause permanent damage to the device. This is a stress
ELECTRICAL rating only; functional operation of the device at these or any
AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational
DRVDD to DRGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute
AGND to DRGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect
AVDD to DRVDD −2.0 V to +2.0 V device reliability.
Dx0 Through Dx9 to DRGND −0.3 V to DRVDD + 0.3 V THERMAL RESISTANCE
DCO+/DCO− to DRGND −0.3 V to DRVDD + 0.3 V
The exposed paddle must be soldered to the ground plane for
OVRA/OVRB to DGND −0.3 V to DRVDD + 0.3 V
the LFCSP package. Soldering the exposed paddle to the
CLK+ to AGND −0.3 V to +3.6 V
customer board increases the reliability of the solder joints,
CLK− to AGND −0.3 V to +3.6 V
maximizing the thermal capability of the package.
VIN+ to AGND −0.3 V to AVDD + 0.2 V
VIN− to AGND −0.3 V to AVDD + 0.2 V Table 6.
SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V Package Type θJA θJC Unit
PDWN to AGND −0.3 V to +3.6 V 56-Lead LFCSP (CP-56-2) 30.4 2.9 °C/W
CSB to AGND −0.3 V to +3.6 V
SCLK/DFS to AGND −0.3 V to +3.6 V Typical θJA and θJC are specified for a 4-layer board in still air.
ENVIRONMENTAL Airflow increases heat dissipation, effectively reducing θJA. In
Storage Temperature Range −65°C to +125°C addition, metal in direct contact with the package leads from
Operating Temperature Range −40°C to +85°C metal traces, and through holes, ground, and power planes
Lead Temperature 300°C reduces the θJA.
(Soldering, 10 sec)
Junction Temperature 150°C
ESD CAUTION

Rev. 0 | Page 8 of 32
 AD9601

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DA0 (LSB)

DRGND
DRVDD

AVDD
AVDD
DCO+
DCO–

CLK+
CLK–
DA1
DA3
DA2

NIC
NIC
54
53
52
56
55

44
43
51
50
49
48
47
46
45
DA4 1 PIN 1 42 AVDD
INDICATOR
DA5 2 41 AVDD
DA6 3 40 CML
DA7 4 39 AVDD
DA8 5 38 AVDD
(MSB) DA9 6 37 AVDD
DRVDD 7
AD9601 36 VIN–
DRGND 8 TOP VIEW 35 VIN+
OVRA 9 (Not to Scale) 34 AVDD
NIC 10 33 AVDD
NIC 11 32 AVDD
(LSB) DB0 12 31 RBIAS
DB1 13 PIN 0 (EXPOSED PADDLE) = AGND 30 AVDD
DB2 14 29 PWDN

21
16
17
18
19
20

22
23
24
25
26
27
28
15

SDIO/DCS
SCLK/DFS
OVRB

CSB
RESET
DRGND
DB6
DB3
DB4
DB5

DB7
DB8
(MSB) DB9

DRVDD

07100-002
Figure 4. Pin Configuration

Table 7. Single Data Rate Mode Pin Function Descriptions

Pin No. Mnemonic Description
30, 32, 33, 34, 37, 38, 39, AVDD 1.8 V Analog Supply.
41, 42, 43, 46
7, 24, 47 DRVDD 1.8 V Digital Output Supply.
0 AGND 1 Analog Ground.
8, 23, 48 DRGND1 Digital Output Ground.
35 VIN+ Analog Input—True.
36 VIN− Analog Input—Complement.
40 CML Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44 CLK+ Clock Input—True.
45 CLK− Clock Input—Complement.
31 RBIAS Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.)
Nominally 0.5 V.
28 RESET CMOS-Compatible Chip Reset (Active Low).
25 SDIO/DCS Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer
Select (External Pin Mode).
26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
27 CSB Serial Port Chip Select (Active Low).
29 PWDN Chip Power-Down.
49 DCO− Data Clock Output—Complement.
50 DCO+ Data Clock Output—True.
53 DA0 (LSB) Output Port A Output Bit 0 (LSB).
54 DA1 Output Port A Output Bit 1.
55 DA2 Output Port A Output Bit 2.
56 DA3 Output Port A Output Bit 3.
1 DA4 Output Port A Output Bit 4.
2 DA5 Output Port A Output Bit 5.
3 DA6 Output Port A Output Bit 6.

Rev. 0 | Page 9 of 32
AD9601
Pin No. Mnemonic Description
4 DA7 Output Port A Output Bit 7.
5 DA8 Output Port A Output Bit 8.
6 DA9 (MSB) Output Port A Output Bit 9 (MSB).
10, 11, 51, 52 NIC Not internally connected.
9 OVRA Output Port A Overrange Output Bit.
12 DB0 (LSB) Output Port B Output Bit 0 (LSB).
13 DB1 Output Port B Output Bit 1.
14 DB2 Output Port B Output Bit 2.
15 DB3 Output Port B Output Bit 3.
16 DB4 Output Port B Output Bit 4.
17 DB5 Output Port B Output Bit 5.
18 DB6 Output Port B Output Bit 6.
19 DB7 Output Port B Output Bit 7.
20 DB8 Output Port B Output Bit 8.
21 DB9 (MSB) Output Port B Output Bit 9 (MSB).
22 OVRB Output Port B Overrange Output Bit.
1
AGND and DRGND should be tied to a common quiet ground plane.

Rev. 0 | Page 10 of 32
 AD9601

EQUIVALENT CIRCUITS
AVDD AVDD

26kΩ
1kΩ
CSB
1.2V
10kΩ 10kΩ
CLK+ CLK–

07100-006
07100-003
Figure 5. Clock Inputs Figure 8. Equivalent CSB Input Circuit

AVDD

DRVDD
VIN+ BUF AVDD

2kΩ
VCML
BUF ~1.4V
AVDD
2kΩ

VIN– BUF

07100-044
DRGND
07100-004

Figure 6. Analog Inputs (VCML = ~1.4 V) Figure 9. CMOS Outputs (Dx, OVRA, OVRB, DCO+, DCO−)

1kΩ DRVDD
SCLK/DFS
RESET
PDWN 30kΩ

1kΩ
SDIO/DCS
07100-005

07100-007
Figure 7. Equivalent SCLK/DFS, RESET, PDWN Input Circuit Figure 10. Equivalent SDIO/DCS Input Circuit

Rev. 0 | Page 11 of 32
AD9601

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, TA = 25°C, 1.25 V p-p differential input, AIN = −1 dBFS, unless
otherwise noted.
0 70k
200MSPS
10.3MHz @ –1.0dBFS
–20 SNR: 59.48dB 60k
ENOB: 9.58 BITS
SFDR: 83.79dBc
–40 50k
AMPLITUDE (dBFS)

NUMBER OF HITS
–60 40k

–80 30k

–100 20k

–120 10k

–140 0
07100-020

07100-023
0 10 20 30 40 50 60 70 80 90 100 N–2 N–1 N N+1
FREQUENCY (MHz) BIN
Figure 11. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 10.3 MHz Figure 14. AD9601-200 Grounded Input Histogram; 200 MSPS

0 90
200MSPS SFDR (+85°C)
70.3MHz @ –1.0dBFS
–20 SNR: 59.3dB 85 SFDR (–40°C)
ENOB: 9.7 BITS
SFDR: 78dBc 80
–40 SFDR (+25°C)
AMPLITUDE (dBFS)

SNR/SFDR (dB)

75
–60
70
–80
65

–100 SNR (+25°C)

60 SNR (–40°C)

–120 SNR (+85°C)

55

–140 50
07100-021

07100-024
0 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz)
Figure 12. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 70.3 MHz Figure 15. AD9601-200 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1.25 V p-p Full Scale; 200 MSPS

0 90
200MSPS
170.3MHz @ –1.0dBFS 80 SFDR (dBFS)
–20 SNR: 59.35dB
ENOB: 9.7 BITS
SFDR: 83dBc 70
–40
AMPLITUDE (dBFS)

60
SNR/SFDR (dB)

SNR (dBFS)
–60
50

–80 40
SFDR (dBc)
30
–100
20 SNR (dB)
–120
10

–140 0
07100-022

07100-025

0 10 20 30 40 50 60 70 80 90 100 90 80 70 60 50 40 30 20 10 0
FREQUENCY (MHz) AMPLITUDE (–dBFS)
Figure 13. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 170.3 MHz Figure 16. AD9601-200 SNR/SFDR vs. Input Amplitude; 170.3 MHz

Rev. 0 | Page 12 of 32
 AD9601
1.0 90

0.8
85
0.6 SFDR (+25°C)
80
0.4

SNR/SFDR (dB)
75
0.2
INL (LSB)

0 70 SFDR (+85°C) SFDR (–40°C)

–0.2
65
–0.4
60
–0.6
55 SNR (+85°C) SNR (+25°C) SNR (–40°C)
–0.8

–1.0 50

07100-026

07100-029
0 128 256 384 512 640 768 896 1024 0 50 100 150 200 250 300 350 400 450 500
OUTPUT CODE ANALOG INPUT FREQUENCY (MHz)
Figure 17. AD9601-200 INL; 200 MSPS Figure 20. SNR/SFDR vs. Analog Input Frequency, Interleaved Mode vs.
Temperature

400 0
250MSPS
10.3MHz @ –1.0dBFS
350
–20 SNR: 59.4dB
ENOB: 9.7 BITS
300 SFDR: 84dBc
–40

AMPLITUDE (dBFS)
TOTAL POWER (mW)
CURRENT (mA)

250
–60
200
–80
150 IAVDD (mA)

–100
100

50 IDVDD (mA) –120

0 –140
07100-027

07100-030
5 25 45 65 85 105 125 145 165 185 205 225 245 0 20 40 60 80 100 120
SAMPLE RATE (MSPS) FREQUENCY (MHz)
Figure 18. AD9601-200 Power Supply Current vs. Sample Rate Figure 21. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 10.3 MHz

1.0 0
250MSPS
0.8 70.3MHz @ –1.0dBFS
–20 SNR: 59.4dB
0.6 ENOB: 9.7 BITS
SFDR: 81dBc
0.4 –40
AMPLITUDE (dBFS)

0.2
DNL (LSB)

–60
0
–80
–0.2

–0.4 –100
–0.6
–120
–0.8

–1.0 –140
07100-028

07100-031

0 128 256 384 512 640 768 896 1024 0 20 40 60 80 100 120
OUTPUT CODE FREQUENCY (MHz)
Figure 19. AD9601-200 DNL; 200 MSPS Figure 22. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 70.3 MHz

Rev. 0 | Page 13 of 32
AD9601
0 100
250MSPS
170.3MHz @ –1.0dBFS 90 SFDR (dBFS)
–20 SNR: 59.1dB
ENOB: 9.60 BITS 80
SFDR: 73dBc
–40 70
AMPLITUDE (dBFS)

SNR/SFDR (dB)
60
–60 SNR (dBFS)
50
–80
40

–100 30
SFDR (dBc) SNR (dB)
20
–120
10

–140 0

07100-032

07100-035
0 20 40 60 80 100 120 90 80 70 60 50 40 30 20 10 0
FREQUENCY (MHz) AMPLITUDE (–dBFS)
Figure 23. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 170.3 MHz Figure 26. AD9601-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz

70k 1.0

0.8
60k
0.6
50k 0.4
NUMBER OF HITS

0.2
40k
INL (LSB)

0
30k
–0.2

20k –0.4

–0.6
10k
–0.8

0 –1.0
07100-033

07100-036
N–2 N–1 N N+1 N+2 0 128 256 384 512 640 768 896 1024
BIN OUTPUT CODE

Figure 24. AD9601-250 Grounded Input Histogram; 250 MSPS Figure 27. AD9601-250 DNL; 250 MSPS

90 400

85 SFDR (+85°C) 350

80 SFDR (+25°C) 300

TOTAL POWER (mW)
CURRENT (mA)
SNR/SFDR (dB)

75 250

70 SFDR (–40°C) 200

IAVDD (mA)
65 150
SNR (+25°C)
60 100

55 SNR (+85°C) 50 IDVDD (mA)

SNR (–40°C)

50 0
07100-037
07100-034

0 50 100 150 200 250 300 350 400 450 500 5 25 45 65 85 105 125 145 165 185 205 225 245
ANALOG INPUT FREQUENCY (MHz) SAMPLE RATE (MSPS)

Figure 25. AD9601-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Figure 28. AD9601 Power Supply Current vs. Sample Rate
Temperature with 1.25 V p-p Full Scale; 250 MSPS

Rev. 0 | Page 14 of 32
 AD9601
1.0 2.5

0.8
2.0
0.6 AD9601-250

0.4
1.5
0.2

GAIN (%FS)
DNL (LSB)

AD9601-210
0 1.0
AD9601-170
–0.2
0.5
–0.4

–0.6
0
–0.8

–1.0 –0.5

07100-040
07100-038
0 128 256 384 512 640 768 896 –60 –40 –20 0 20 40 60 80 100 120
OUTPUT CODE TEMPERATURE (°C)

Figure 29. AD9601-250 DNL; 250 MSPS Figure 31. Gain vs. Temperature

90 6.0
SFDR
80 5.5
AD9601-250
70
5.0

60
SNR/SFDR (dB)

4.5
OFFSET (mV)
SNR
AD9601-210
50
4.0
40 AD9601-170
3.5
30
3.0
20

10 2.5

0 2.0

07100-041
07100-039

75 125 175 225 275 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

SAMPLE RATE (MSPS) TEMPERATURE (°C)

Figure 30. SNR/SFDR vs. Sample Rate; Figure 32. Offset vs. Temperature
AD9626-250 , 170.3 MHz @ −1 dBFS

Rev. 0 | Page 15 of 32
AD9601

THEORY OF OPERATION
The AD9601 architecture consists of a front-end sample-and-
1V p-p 49.9Ω
hold amplifier (SHA) followed by a pipelined switched capacitor 499Ω
ADC. The quantized outputs from each stage are combined into AVDD
33Ω
499Ω VIN+
a final 10-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input AD8138 20pF AD9601
523Ω
sample, while the remaining stages operate on preceding 0.1µF VIN–
33Ω CML

07100-008
samples. Sampling occurs on the rising edge of the clock. 499Ω

Each stage of the pipeline, excluding the last, consists of a low

Figure 33. Differential Input Configuration Using the AD8138
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier At input frequencies in the second Nyquist zone and above, the
magnifies the difference between the reconstructed DAC output performance of most amplifiers may not be adequate to achieve
and the flash input for the next stage in the pipeline. One bit of the true performance of the AD9601. This is especially true in
redundancy is used in each stage to facilitate digital correction IF undersampling applications where frequencies in the 70 MHz
of flash errors. The last stage simply consists of a flash ADC. to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
The input stage contains a differential SHA that can be ac- or
configuration. The signal characteristics must be considered
dc-coupled. The output-staging block aligns the data, carries
when selecting a transformer. Most RF transformers saturate at
out the error correction, and passes the data to the output
frequencies below a few millihertz, and excessive signal power
buffers. The output buffers are powered from a separate supply,
can also cause core saturation, which leads to distortion.
allowing adjustment of the output voltage swing. During power-
down, the output buffers go into a high impedance state. In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
ANALOG INPUT AND VOLTAGE REFERENCE or removed.
The analog input to the AD9601 is a differential buffer. For best
dynamic performance, the source impedances driving VIN+ 15Ω
VIN+
and VIN− should be matched such that common-mode settling
1.25V p-p 50Ω 2pF AD9601
errors are symmetrical. The analog input is optimized to provide
superior wideband performance and requires that the analog VIN–
15Ω

07100-009
inputs be driven differentially. 0.1µF

A wideband transformer, such as Mini-Circuits® ADT1-1WT, Figure 34. Differential Transformer-Coupled Configuration
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog As an alternative to using a transformer-coupled input at
inputs are self-biased by an on-chip resistor divider to a frequencies in the second Nyquist zone, the AD8352 differential
nominal 1.4 V. driver can be used (see Figure 35).
VCC
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.25 V p-p fixed span 0.1µF
of the ADC core. This internal voltage reference can be adjusted 0.1µF
0Ω 16
8, 13
by means of SPI control. See the AD9601 Configuration Using ANALOG INPUT 1 11 0.1µF R
2 VIN+
the SPI section for more details. 200Ω
CD RD RG AD8352 C AD9601
Differential Input Configurations 3
10 0.1µF 200Ω
R
4 VIN– CML
Optimum performance is achieved while driving the AD9601 ANALOG INPUT
5
14
in a differential input configuration. For baseband applications, 0.1µF 0Ω 0.1µF
07100-010

0.1µF
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode Figure 35. Differential Input Configuration Using the AD8352
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.

Rev. 0 | Page 16 of 32
 AD9601
CLOCK INPUT CONSIDERATIONS In some applications, it is acceptable to drive the sample clock
For optimum performance, the AD9601 sample clock inputs inputs with a single-ended CMOS signal. In such applications,
(CLK+ and CLK−) should be clocked with a differential signal. CLK+ should be directly driven from a CMOS gate, and the
This signal is typically ac-coupled into the CLK+ pin and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor
CLK− pin via a transformer or capacitors. These pins are biased in parallel with a 39 kΩ resistor (see Figure 39). Although the
internally and require no additional bias. CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
Figure 36 shows one preferred method for clocking the AD9601. selection of the drive logic voltage very flexible.
The low jitter clock source is converted from single-ended to
AD9510/AD9511/
differential using an RF transformer. The back-to-back Schottky AD9512/AD9513/
0.1µF
AD9514/AD9515
diodes across the secondary transformer limit clock excursions CLOCK
INPUT CLK
into the AD9601 to approximately 0.8 V p-p differential. This OPTIONAL
0.1µF
50Ω* 100Ω
helps prevent the large voltage swings of the clock from feeding CMOS DRIVER CLK+

through to other portions of the AD9601 and preserves the fast ADC
CLK AD9601
rise and fall times of the signal, which are critical to low jitter 0.1µF
CLK–
performance. 0.1µF 39kΩ

07100-014
MINI-CIRCUITS *50Ω RESISTOR IS OPTIONAL.
ADT1–1WT, 1:1Z
0.1µF 0.1µF Figure 39. Single-Ended 1.8 V CMOS Sample Clock
CLOCK XFMR
CLK+
INPUT 100Ω ADC
50Ω
0.1µF AD9601
AD9510/AD9511/
CLK– AD9512/AD9513/
0.1µF SCHOTTKY AD9514/AD9515
07100-011

0.1µF
DIODES: CLOCK
HSM2812 INPUT CLK OPTIONAL
50Ω* 100Ω 0.1µF
Figure 36. Transformer-Coupled Differential Clock CMOS DRIVER CLK+

ADC
If a low jitter clock is available, another option is to ac couple a CLK AD9601
0.1µF 0.1µF
differential PECL signal to the sample clock input pins, as CLK–
shown in Figure 37. The AD9510/AD9511/AD9512/AD9513/

07100-015
AD9514/AD9515 family of clock drivers offers excellent jitter
*50Ω RESISTOR IS OPTIONAL.
performance.
Figure 40. Single-Ended 3.3 V CMOS Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
Clock Duty Cycle Considerations
0.1µF 0.1µF
CLOCK
CLK CLK+
Typical high speed ADCs use both clock edges to generate a
INPUT
ADC variety of internal timing signals. As a result, these ADCs may
100Ω
PECL DRIVER AD9601 be sensitive to the clock duty cycle. Commonly, a 5% tolerance
0.1µF 0.1µF
CLOCK CLK–
INPUT CLK is required on the clock duty cycle to maintain dynamic per-
50Ω* 50Ω* 240Ω 240Ω
formance characteristics. The AD9601 contains a duty cycle
07100-012

*50Ω RESISTORS ARE OPTIONAL. stabilizer (DCS) that retimes the nonsampling edge, providing
Figure 37. Differential PECL Sample Clock an internal clock signal with a nominal 50% duty cycle. This
allows a wide range of clock input duty cycles without affecting
the performance of the AD9601. When the DCS is on, noise
AD9510/AD9511/ and distortion performance are nearly flat for a wide range of
AD9512/AD9513/
0.1µF AD9514/AD9515 0.1µF duty cycles. However, some applications may require the DCS
CLOCK CLK+
INPUT CLK function to be off. If so, keep in mind that the dynamic range
100Ω ADC performance can be affected when operated in this mode. See the
LVDS DRIVER AD9601
0.1µF 0.1µF
CLOCK CLK–
AD9601 Configuration Using the SPI section for more details
INPUT CLK
50Ω* 50Ω* on using this feature.
07100-013

The duty cycle stabilizer uses a delay-locked loop (DLL) to

*50Ω RESISTORS ARE OPTIONAL.
create the nonsampling edge. As a result, any changes to the
Figure 38. Differential LVDS Sample Clock
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.

Rev. 0 | Page 17 of 32
AD9601
Clock Jitter Considerations and internal reference remain on, but digital circuitry is powered
High speed, high resolution ADCs are sensitive to the quality of the down. Upon reactivating the clock, the AD9601 resumes normal
clock input. The degradation in SNR for a full-scale input signal operation after allowing for the pipeline latency.
at a given input frequency (fA) due only to aperture jitter (tJ) can DIGITAL OUTPUTS
be calculated by Digital Outputs and Timing
SNR Degradation = 20 × log10[1/2 × π × fA × tJ] The off-chip drivers on the AD9601 are CMOS-compatible
In this equation, the rms aperture jitter represents the root mean output levels. The outputs are biased from a separate supply
square of all jitter sources, including the clock input, analog input (DRVDD), allowing isolation from the analog supply and easy
signal, and ADC aperture jitter specifications. IF undersampling interface to external logic. The outputs are CMOS devices that
applications are particularly sensitive to jitter (see Figure 41). swing from ground to DRVDD (with no dc load). It is recom-
The clock input should be treated as an analog signal in cases mended to minimize the capacitive load the ADC drives by
where aperture jitter may affect the dynamic range of the AD9601. keeping the output traces short (<1 inch, for a total CLOAD < 5 pF).
Power supplies for clock drivers should be separated from the When operating in CMOS mode, it is also recommended to
ADC output driver supplies to avoid modulating the clock signal place low value (20 Ω) series damping resistors on the data lines
with digital noise. Low jitter, crystal controlled oscillators make to reduce switching transient effects on performance.
the best clock sources. If the clock is generated from another The format of the output data is offset binary by default. An
type of source (by gating, dividing, or other methods), it should example of the output coding format can be found in Table 11.
be retimed by the original clock at the last step. If it is desired to change the output data format to twos comple-
Refer to the AN-501 Application Note and the AN-756 ment, see the AD9601 Configuration Using the SPI section.
Application Note for more in-depth information about jitter An output clock signal is provided to assist in capturing data
performance as it relates to ADCs (visit www.analog.com). from the AD9601. The DCO+/DCO− signal is used to clock the
130 output data and is equal to the sampling clock (CLK) rate in
RMS CLOCK JITTER REQUIREMENT
120
single port mode, and one-half the clock rate in interleaved
output mode. See the timing diagrams shown in Figure 2 and
110
Figure 3 for more information.
100 16 BITS
Out-of-Range
90 14 BITS
SNR (dB)

An out-of-range condition exists when the analog input voltage

80
12 BITS is beyond the input range of the ADC. OVRA/OVRB is a digital
70
10 BITS
output that is updated along with the data output corresponding
60 to the particular sampled input voltage. Thus, OVRA/OVRB
0.125ps
8 BITS
50 0.25ps has the same pipeline latency as the digital data. OVRA/OVRB
0.5ps
40 1.0ps is low when the analog input voltage is within the analog input
2.0ps
30
range and high when the analog input voltage exceeds the input
07100-016

1 10 100 1000 range, as shown in Figure 42. OVRA/OVRB remains high until
ANALOG INPUT FREQUENCY (MHz)
the analog input returns to within the input range and another
Figure 41. Ideal SNR vs. Input Frequency and Jitter for 0 dBFS Input Signal
conversion is completed. By logically AND-ing OVRA/OVRB
POWER DISSIPATION AND POWER-DOWN MODE with the MSB and its complement, overrange high or under-
As shown in Figure 28, the power dissipated by the AD9601 is range low conditions can be detected.
proportional to its sample rate. The digital power dissipation OVRA/OVRB
DATA OUTPUTS +FS – 1 LSB

does not vary much because it is determined primarily by the 1 1111 1111 1111 OVRA/
0 1111 1111 1111 OVRB
DRVDD supply and bias current of the LVDS output drivers. 0 1111 1111 1110
–FS + 1/2 LSB
By asserting PDWN (Pin 29) high, the AD9601 is placed in
standby mode or full power-down mode, as determined by the 0 0000 0000 0001
0 0000 0000 0000
contents of Serial Port Register 08. Reasserting the PDWN pin 1 0000 0000 0000
low returns the AD9601 into its normal operational mode.
07100-017

–FS +FS
An additional standby mode is supported by means of varying –FS – 1/2 LSB +FS – 1/2 LSB

the clock input. When the clock rate falls below 20 MHz, the Figure 42. OVRA/OVRB Relation to Input Voltage and Output Data
AD9601 assumes a standby state. In this case, the biasing network

Rev. 0 | Page 18 of 32
 AD9601
TIMING—SINGLE PORT MODE mended to use the rising edge of DCO+ to capture the data
In single port mode, the CMOS output data is available from from Port A, and the rising edge of DCO− to capture the data
Data Port A (DA0 to DA9). The outputs for Port B (DB0 to from Port B. In both cases, the setup and hold time depends on
DB9) are unused, and are high impedance in this mode. the input sample clock period, and both are approximately
The Port A outputs and the differential output data clock 2/fS ± tSKEW.
(DCO+/DCO−) switch nearly simultaneously during the rising fS/2 Spurious
edge of DCO+. In this mode, it is recommended to use the Because the AD9601 output data rate is at one-half the sampling
rising edge of DCO− to capture the data from Port A. The setup frequency in interleaved output mode, there is significant fS/2
and hold time depends on the input sample clock period, and is energy in the outputs of the part, and there is significant energy
approximately 1/fCLK ± tSKEW. in the ADC output spectrum at fS/2. Care must be taken to be
TIMING—INTERLEAVED MODE certain that this fS/2 energy does not couple into either the clock
circuit or the analog inputs of the AD9601. When fS/2 energy is
In interleaved mode, the output data of the AD9601 is de-
coupled in this fashion, it appears as a spurious tone reflected
multiplexed onto two data port buses, Port A (DA0 to DA9) and
around fS/4, 3fS/4, 5fS/4, and so on. For example, in a 125 MSPS
Port B (DB0 to DB9). The output data and differential data
sampling application with a 90 MHz single-tone analog input,
capture clock switch at one-half the rate of the sample clock
this energy generates a tone at 97.5 MHz.
input (CLK+/CLK−), increasing the setup and hold time for the
external data capture circuit relative to single port mode (see [(3 × 125 MSPS/4 − 90 MHz) + 3 × 125 MSPS/4]
Figure 3, interleaved mode timing diagram). The two ports Depending on the relationship of the IF frequency to the center
switch on alternating sample clock cycles, with the data for of the Nyquist zone, this spurious tone may or may not be in the
Port A being valid during the rising edge of DCO+, and the user’s band of interest. Some residual fS/2 energy is present in
data for Port B being valid during the rising edge of DCO−. The the AD9601, and the level of this spur is typically below the
pipeline latency for both ports is six sample clock cycles. Due to level of the harmonics at clock rates. Figure 20 shows a plot of
the random nature of the ÷2 circuit that generates the timing the fS/2 spur level vs. the analog input frequency for the
for the output stage in interleaved mode, the first data sample AD9601-250. For the specifications provided in Table 2, the fS/2
during power-up can be assigned to either Data Port A or Port spur effect is not a factor, as the device is specified in single port
B. The user cannot control the polarity of the output data clock output mode.
relative to the input sample clock. In this mode, it is recom-

Rev. 0 | Page 19 of 32
AD9601

LAYOUT CONSIDERATIONS
POWER AND GROUND RECOMMENDATIONS RBIAS
When connecting power to the AD9601, it is recommended The AD9601 requires the user to place a 10 kΩ resistor between
that two separate supplies be used: one for analog (AVDD, 1.8 V the RBIAS pin and ground. This resistor sets the master current
nominal) and one for digital (DRVDD, 1.8 V nominal). If only a reference of the ADC core and should have at least a 1% tolerance.
single 1.8 V supply is available, it is routed to AVDD first, then
AD9601 CONFIGURATION USING THE SPI
tapped off and isolated with a ferrite bead or filter choke with
decoupling capacitors proceeding connection to DRVDD. The The AD9601 SPI allows the user to configure the converter for
user can employ several different decoupling capacitors to cover specific functions or operations through a structured register
both high and low frequencies. These should be located close to space inside the ADC. This gives the user added flexibility to
the point of entry at the PC board level and close to the parts customize device operation depending on the application.
with minimal trace length. Addresses are accessed (programmed or read back) serially in
one-byte words. Each byte can be further divided down into
A single PC board ground plane is sufficient when using the fields, which are documented in the Memory Map section.
AD9601. With proper decoupling and smart partitioning of
analog, digital, and clock sections of the PC board, optimum There are three pins that define the serial port interface or SPI
performance is easily achieved. to this particular ADC. They are the SPI SCLK/DFS, SPI
SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used
Exposed Paddle Thermal Heat Slug Recommendations to synchronize the read and write data presented the ADC. The
It is required that the exposed paddle on the underside of the SDIO/DCS (serial data input/output) is a dual-purpose pin that
ADC be connected to analog ground (AGND) to achieve the allows data to be sent and read from the internal ADC memory
best electrical and thermal performance of the AD9601. An map registers. The CSB is an active low control that enables or
exposed, continuous copper plane on the PCB should mate to disables the read and write cycles (see Table 8).
the AD9601 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal Table 8. Serial Port Pins
path for heat dissipation to flow through the bottom of the PCB. Mnemonic Function
These vias should be solder-filled or plugged. SCLK SCLK (Serial Clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
To maximize the coverage and adhesion between the ADC and reads and writes.
PCB, partition the continuous plane by overlaying a silkscreen SDIO SDIO (Serial Data Input/Output) is a dual-purpose
on the PCB into several uniform sections. This provides several pin. The typical role for this pin is an input and
tie points between the two during the reflow process. Using one output depending on the instruction being sent
continuous plane with no partitions guarantees only one tie and the relative position in the timing frame.
point between the ADC and PCB. See Figure 43 for a PCB layout CSB CSB (Chip Select Bar) is an active low control that
gates the read and write cycles.
example. For detailed information on packaging and the PCB
RESET Master Device Reset. When asserted, device
layout of chip scale packages, see Application Note AN-772,
assumes default settings. Active low.
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package. The falling edge of the CSB, in conjunction with the rising edge
SILKSCREEN PARTITION of the SCLK, determines the start of the framing. An example of
PIN 1 INDICATOR
the serial timing and its definitions can be found in Figure 44
and Table 10.
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
07100-018

the W0 and W1 bits, which is 1 or more bytes of data. All data is

composed of 8-bit words. The first bit of each individual byte of
Figure 43. Typical PCB Layout
serial data indicates whether this is a read or write command.
CML This allows the serial data input/output (SDIO) pin to change
The CML pin should be decoupled to ground with a 0.1 μF direction from an input to an output.
capacitor, as shown in Figure 45. Data can be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see Interfacing to High Speed ADCs via SPI at
www.analog.com.

Rev. 0 | Page 20 of 32
 AD9601
HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI
The pins described in Table 8 comprise the physical interface In applications that do not interface to the SPI control registers,
between the user’s programming device and the serial port of the SPI SDIO/DCS and SPI SCLK/DFS pins can alternately
the AD9601. All serial pins are inputs, which is an open-drain serve as standalone CMOS-compatible control pins. When the
output and should be tied to an external pull-up or pull-down device is powered up, it is assumed that the user intends to use
resistor (suggested value of 10 kΩ). the pins as static control lines for the duty cycle stabilizer. In
This interface is flexible enough to be controlled by either this mode, the SPI CSB chip select should be connected to
PROMS or PIC microcontrollers as well. This provides the user ground, which disables the serial port interface.
with an alternate method to program the ADC other than a SPI Table 9. Mode Selection
controller.
External
If the user chooses not to use the SPI interface, some pins serve Mnemonic Voltage Configuration
a dual function and are associated with a specific function when SPI SDIO/DCS AVDD Duty cycle stabilizer enabled
strapped externally to AVDD or ground during device power- AGND Duty cycle stabilizer disabled
on. The Configuration Without the SPI section describes the SPI SCLK/DFS AVDD Twos complement enabled
strappable functions supported on the AD9601. AGND Offset binary enabled

tDS tHI tCLK tH

tS tDH tLO
CSB

SCLK DON’T CARE DON’T CARE

07100-019
SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE

Figure 44. Serial Port Interface Timing Diagram

Rev. 0 | Page 21 of 32
AD9601
Table 10. Serial Timing Definitions
Parameter Timing (minimum, ns) Description
tDS 5 Setup time between the data and the rising edge of SCLK
tDH 2 Hold time between the data and the rising edge of SCLK
tCLK 40 Period of the clock
tS 5 Setup time between CSB and SCLK
tH 2 Hold time between CSB and SCLK
tHI 16 Minimum period that SCLK should be in a logic high state
tLO 16 Minimum period that SCLK should be in a logic low state
tEN_SDIO 1 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 44)
tDIS_SDIO 5 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 44)

Table 11. Output Data Format

Gray Code Mode
Offset Binary Output Mode Twos Complement Mode (SPI Accessible)
Input (V) Condition (V) D11 to D0 D11 to D0 D11 to D0 OR
VIN+ − VIN− < 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 1
VIN+ − VIN− = 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 0
VIN+ − VIN− =0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0
VIN+ − VIN− = 0.62 1111 1111 1111 1111 1111 1111 0000 0000 0000 0
VIN+ − VIN− > 0.62 + 0.5 LSB 1111 1111 1111 1111 1111 1111 0000 0000 0000 1

Rev. 0 | Page 22 of 32
 AD9601

MEMORY MAP
READING THE MEMORY MAP TABLE RESERVED LOCATIONS
Each row in the memory map table has eight address locations. Undefined memory locations should not be written to other
The memory map is roughly divided into three sections: chip than their default values suggested in this data sheet. Addresses
configuration register map (Address 0x00 to Address 0x02), that have values marked as 0 should be considered reserved and
transfer register map (Address 0xFF), and program register map have a 0 written into their registers during power-up.
(Address 0x08 to Address 0x2A).
DEFAULT VALUES
The Addr (Hex) column of the memory map indicates the Coming out of reset, critical registers are preloaded with default
register address in hexadecimal, and the Default Value (Hex) values. These values are indicated in Table 12. Other registers
column shows the default hexadecimal value that is already do not have default values and retain the previous value when
written into the register. The Bit 7 (MSB) column is the start of exiting reset.
the default hexadecimal value given. For example, Hexadecimal
Address 0x09, clock, has a hexadecimal default value of 0x01. LOGIC LEVELS
This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, An explanation of various registers follows: “Bit is set” is
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The synonymous with “bit is set to Logic 1” or “writing Logic 1 for
default value enables the duty cycle stabilizer. Overwriting this the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
default so that Bit 0 = 0 disables the duty cycle stabilizer. For more Logic 0” or “writing Logic 0 for the bit.”
information on this and other functions, consult the Interfacing
to High Speed ADCs via SPI user manual at www.analog.com.

Table 12. Memory Map Register

Default
Addr Bit 7 Bit 0 Value Default Notes/
(Hex) Parameter Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments
Chip Configuration Registers
00 chip_port_config 0 LSB Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles
first should be
mirrored by the
user so that LSB
or MSB first mode
registers correctly,
regardless of shift
mode.
01 chip_id 8-bit chip ID, Bits[7:0] Read- Default is unique
AD9601 = 0x36 only chip ID, different
for each device.
This is a read-
only register.
02 chip_grade 0 0 0 Speed grade: X X X Read- Child ID used to
01 = 200 MSPS only differentiate
10 = 250 MSPS graded devices.
Transfer Register
FF device_update 0 0 0 0 0 0 0 SW 0x00 Synchronously
transfer transfers data
from the master
shift register to
the slave.
ADC Functions
08 modes 0 0 PDWN: 0 0 Internal power-down mode: 0x00 Determines
0 = full 000 = normal (power-up, default) various generic
(default) 001 = full power-down modes of chip
1= 010 = standby operation.
standby 011 = normal (power-up)
Note: external PDWN pin overrides
this setting

Rev. 0 | Page 23 of 32
AD9601
Default
Addr Bit 7 Bit 0 Value Default Notes/
(Hex) Parameter Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments
09 clock 0 0 0 0 0 0 0 Duty cycle 0x01
stabilizer:
0=
disabled
1=
enabled
(default)
OD test_io Reset Reset Output test mode: 0x00 When set, the
PN23 gen: PN9 gen: 0000 = off (default) test data is
1 = on 1 = on 0001 = midscale short placed on the
0 = off 0 = off 0010 = +FS short output pins in
(default) (default) 0011 = −FS short place of normal
0100 = checker board output data.
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = unused
1001 = unused
1010 = unused
1011 = unused
1100 = unused
(Format determined by output_mode)
OF ain_config 0 0 0 0 0 Analog CML 0 0x00
input enable:
disable: 1 = on
1 = on 0 = off
0 = off (default)
(default)
14 output_mode 0 0 Interleave Output 0 Output Data format select: 0x00
output enable: invert: 00 = offset binary
mode: 0= 1 = on (default)
1= enable 0 = off 01 = twos
enabled (default) (default) complement
0= 1= 10 = Gray code
disabled disable
(default)
16 output_phase Output 0 0 0 0x03
clock
polarity
1=
inverted
0=
normal
(default)
17 flex_output_delay Output Output clock delay: 0x00
delay 00000 = 0.1 ns
enable: 00001 = 0.2 ns
0= 00010 = 0.3 ns
enable …
1= 11101 = 3.0 ns
disable 11110 = 3.1 ns
11111 = 3.2 ns
18 flex_vref Input voltage range setting: 0x00
10000 = 0.98 V
10001 =1.00 V
10010 = 1.02 V
10011 =1.04 V
…
11111 = 1.23 V
00000 = 1.25 V
00001 = 1.27 V
…
01110 = 1.48 V
01111 = 1.50 V

Rev. 0 | Page 24 of 32
 GND P7
CONNECTS TO J2
GND P5 VSPI E33 GNDCD10
E32 CSB 60
GND P4 GND P17 E31 DOR 40
C10 GNDCD9 D10 DORB
CSB_DUT 50
GND P3 GND P16 RN1 59
D10 C9 D9 D10B
39 GNDCD8 49
GND P2 GND P10 50_OHMS 58
D8 C8 D8 D8B
GND 38 GNDCD7 48
P1 GND P9
57
D6 C7 D7 D6B
37 GNDCD6 47
1 16 56
DOR D4 C6 D6 D4B

SCLK_DTP
SDIO_ODM
36 GNDCD5 46
2 15 55
EVALUATION BOARD

DORB D2 C5
GNDCD4
D5 D2B
35 45
3 14 54
D11 D0 C4 D4 D0B
R13 R10 34 GNDCD3 44
1K 1K 4 13 53
D11B C3 D3
33 GNDCD2 43
E10 E1 VSPI 5 12 52
VSPI D10 C2 D2
32 GNDCD1 42
E5 E3 6 11 51
GND D10B C1 D1
E4 31 GNDAB10 41
AVDD E2 GND 7 10 30
D9 A10 B10
10 GNDAB9 20
R11 8 9 29
D9B D11 A9 B9 D11B
9 GNDAB8 19
SW3 1K 28
IN OUT D9 A8 B8 D9B
1 2 8 GNDAB7 18
50_OHMS

CSB
DRVDD
GND
ANALOG GND 27
D7 A7 B7 D7B
Alternate Options RN2 7 GNDAB6 17
26
EVQ-Q2 D5 A6 B6 D5B
6 GNDAB5 16

28
27
26
25
24
23
22
21
20
19
18
17
16
15
T3 1 16

R12
10K
25
ADT1-1WT D3 A5 B5 D3B
GND RESETB 5 GNDAB4 15
Input VSPI E7 2 15

D9
GND 1 6 TOUT 24

D11
D10
PDN D8

D9B
E9 A4 B4

DOR
5 2 D1 4 GNDAB3 D1B

D11B
D10B
29 14 14

DORB
CML nc CML GND E8 3 14 23

SPCSB
DVDD1
DGND1
3 4 AVDD AVDD_REF D8B D8 A3 B3
TINB TOUTB 30 13 3 GNDAB2 13
GND PRI SEC 4 13
RBIAS D7 D8B 22
R4 A2 B2

SPSDIO/DCS
SPSCLK/DFS
T5 31 12 12 2 GNDAB1 12
DNP 5

L8
0
C16 C19 AMPOUT+ AVDD AVDD_PIPE5 D7B D7 21
GND 1 5 TOUT DCO A1 B1 DCOB
32 11 6 11 1 11
0.1UF 2 CML
GND 0.1UF AVDD AVDD_PIPE4 D6 D7B
HEADERM1469169_1

33
3

R7
4 33 10
J2 7 10
L1 PRI SEC C22 R5 R9 AVDD AVDD_PIPE3 D6B D6
GND 34 9

C21
TINB 0.1UF 36 DNP 8 9
10NH U4

0.1UF
ETC1-1-13 AIN DGND GND D6B

3
1
35 8

DNP
CML AD9601_CSP
AINB DVDD DRVDD

T6
E6 36 7 50_OHMS GND P11
GND

PRI SEC
4
2
5
TOUTB R6

ETC1-1-13
AVDD AVDD_PIPE2 D5 CONNECTS TO J1

C17

optional
36 37 6
RN3 GNDCD10
AVDD AVDD_PIPE1 D5B 60
GND GND 38 5 1 16 40
C10 GNDCD9 D10
AVDD_PIPE D5 50

R16
33
AVDD 59
39 D4 4
2 15 C9 GNDCD8 D9
CML D5B 39 49
D4B

0
AMPOUT- 58

L9
0.1UF 40 3 3 C8 D8
14 38 GNDCD7
AVDD AVDD_FL1 D3 D4 48
C18 41 2 57
4 13 C7 D7

Rev. 0 | Page 25 of 32
D3B D4B 37 GNDCD6 47
AVDD AVDD_FL
42 1 56

CLK
DCOB
D0B
D0
D1B
D1
D2B
D2

CLKB
DGND2
DCO

DVDD2
AVDD_CLK1
PAD 5 12 C6 GNDCD5 D6

CMLX
D3 36 46
R17 55
AVDD_CLK C5 D5

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57

6 11 35 GNDCD4 45
0 DNP D3B
54
CML 7 10 C4 D4
34 GNDCD3 44
53
8 9 C3 D3
33 GNDCD2
GND

43

GND

AVDD
AVDD
CR2 TO MAKE LAYOUT AND PARASITIC LOADING SYMMETRICAL 52
C2 D2

DRVDD
32 GNDCD1 42

C75
0.1UF
GND 51
GND GND 31
C1 GNDAB10 D1
41
30
R14 R1 RN4 A10
10 GNDAB9 B10 20

Figure 45. AD9601 Evaluation Board Schematic Page 1

DNP R8 50_OHMS 29
R89 CLK CLK A9
C20 00 9 GNDAB8 B9 19
J3 00 50 28
DNP A8 GNDAB7 B8
T2 8 18

1
2
1 16 27

3
ADT1-1WT D2 A7 B7
7 GNDAB6 17
1 6 CLKCT 2 15 26
CLKCT 5 2 DNP D2B CSB1_CHA A6 GNDAB5 B6 SCLK_CHA
nc 6 16

CR2

CR3

C15
0.1UF
ENCODE GND 3 14 25
3 4 A5 SDI_CHA
0.1UF GND D1 5 GNDAB4 B5 15

3
PRI SEC

2
1
C23 4 13 24
R3 R15 D1B A4 SDO_CHA
R87 4 GNDAB3 B4 14
J4 50 DNP 5 12 23
R90 VCLK D0 A3 GNDAB2 B3
0 3 13
00 OPTIONAL ENCODE CIRCUITS 6 11 22
GND D0B A2
2 GNDAB1 B2 12
GND CVHD_956 Crystek Crystal R85 7 10 21
XTALINPUT 10K DCO A1 B1
GND U6 1 11
VOLT_CONTROL 8 9
XTALINPUT 4 1 DCOB HEADERM1469169_1
OUTPUT VOLT_CONTROL C61
R86
E18 10K
GND 0.1UF
5 2 E19
NC TRI_STATE
VCLK
6 3 E20
VCLK VCLK GND
GND
GND

C74
0.1UF
07100-045
AD9601
 AD9601

AVDD

+
C8

C33
C32
C31
C30
C29
C28
C27
C62
C63
C64
C65
C70
C71

10UF

0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF

POWER OPTIONS
GND

P8
GND DRVDD VCLK
PJ-102A

C26
0.1UF
C24
0.1UF
EGND +

C60
0.1UF
C13
0.1UF
C67
0.1UF
C69
0.1UF
C73
100PF

2
C9 C54 +
4 3

EGND
10UF 10UF

3
C25
U8

C59
C66
C68
C72

0.1UF
1 2

0.1UF
0.1UF
0.1UF
0.1UF

1
VIN GND
GND
T1
+ C11
U7
VSPI VSPIEXT VAMP

R2
10UF

499
C39
C58
0.1UF
C56
0.1UF

C36 C35 0.1UF C12 + C34 +

EGND 10UF C14
0.1UF
0.1UF 0.1UF
EGND 10UF
C57
0.1UF

GND GND
GND

GND
H4
MTHOLE6
H3
MTHOLE6
VAMPX AVDDX
DRVDDX1 VSPIEXTX H2
MTHOLE6
GND GND H1
GND MTHOLE6
GND
GND

C7

C5
C3

1UF
C1

1UF
1UF

1UF

4
4
4

Rev. 0 | Page 26 of 32
OUT
OUT
OUT

OUT
+5V 1.8V
1.8V 3.3V
P6

IN
OUT1
GND
IN
OUT1
GND
8

GND

IN
OUT1
GND

VSPIEXTX

3
2
1
3
2
1
IN
OUT1
GND
VSPIEXT1 FERRITE
7

3
2
1
VSPIEXT 3.3V

3
2
1
ADP3338 ADP3338 L15
U10 U9 ADP3338
6

ADP3338 GND
U12 U11
DRVDD1 FERRITE

Figure 46. AD9601 Evaluation Board Schematic Page 2

GND
5

GND DRVDD 1.8V

GND GND L14

C6
C4

1UF
AVDDX

C10

VAMPX
1UF

GND
C2
1UF
4

GND

GND
GND

1UF
GND

DRVDDX1
AVDD1 FERRITE
VIN
3

AVDD 1.8V

VIN
VSPIEXTX

L13

VIN
VIN
2

GND
VAMP1 FERRITE

0
1

R88
VAMP +5.0V
L12
DRVDDX

L7
L4

FERRITE
FERRITE
L2
L6

FERRITE
FERRITE

L5
L3

FERRITE
FERRITE

AVDD1

VAMP1
VCLK

VSPIEXT1

VSPI

DRVDD1
07100-046
 10K 10K
GND
VAMP R43 R42

GND
R91

E14
00
CML

E13

E12
Operational Amplifier .1UF C37 .1UF C46
C47
R45 GND GND
.1UF 5
GND
VAMP
GND
R35 16 15 14 13
25
P13 DNP
SMBMST R94 R37
VIP ENB VCM VCC GND

00
R36
C40
DNP
00 1 12
TINB1 TOUT2 GND
RDP

C44
R41

DNP
L11
DNP
T4 00
2 11
ADT1-1WT C43 AMPOUT+
GND R40 RGP VOP
1 6 GND 49.9
DNP DNP R44
5 2 R33 Z1 R46

C76
nc 00
DNP

R34 3 4 3 RGN 10 00
VON AMPOUT-
P12 DNP PRI SEC
SMBMST AD8352

C41
DNP

00
R47
L10
4 RDN 9

C45
DNP

DNP
25 GND
TINB2 TOUTB2 R38 VCC
VIN GND
C42 5 6 7 8
R39 GND
.1UF AD9515 Logic Setup
5
TINB1 T7 TOUT2
1 5 VAMP
VCLK GND
2
GND GND
3 4 S0
PRI SEC
R64
00
R63
00

TINB2 ETC1-1-13
TOUTB2
VCLK GND

S1
R66
00
R65
00

VCLK GND

S2
R68
00
R67
00

VCLK GND

S3

Rev. 0 | Page 27 of 32
AD9515(Opt_Clk Circuit)
C53
R70
00
R69
00

CLK
VCLK GND
VCLK
R62 0.1UF
S4
4.12K 100
GND GND R59
R72
00
R71
00

C50 CLK VCLK GND

00 00 10K
R53 R52 R54 GND

Figure 47. AD9601 Evaluation Board Schematic Page 3

00

R49
DNP
0.1UF S5

32
31
33
SMBMST R51 U1
23

C49
DNP
2 CLK OUT0 240 240
22
R74
00
R73
00

P15 3 CLKB R61 R60

GND
OUT0B

RSET
VCLK GND
5 19
R57 SYNCB

GND_PAD
OUT1
00 18 S6
SMBMST AD9515 OUT1B

C48
0.1UF
R76
00
R75
00

S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10

VREF
P14 GND

6
7
8
9
VCLK GND
10
11
12
13
14
15
16
25

50 R50 C51
R48 DNP 00 00 E17
E15 S7
R56 R55 S9
0.1UF
S8
S7
S6
S5
S4
S3
S2
S1
S0

S10
100
R78
00
R77
00

R58
GND GND VCLK GND
C52
DNC; 27, 28 E16 S8
VCLK; 1, 4, 17, 20, 21, 24, 26, 29, 30
GND 0.1UF
R80
00
R79
00

VCLK GND

S9
R82
00
R81
00

VCLK GND

S10
00
R83
00

R84
07100-047
AD9601
AD9601

CSB_DUT
07100-048

R24

SCLK_DTP
1K
VSPIEXT

R25
1K

VSPI
VSPI

VSPI

4
6

VCC
Y1

Y2
VCC
Y1

Y2

NC7WZ16
NC7WZ07

U3
U5
1K
R27

GND
GND

A1

A2
A1

A2

3
1

GND
GND
R26

R18
10K

10K
GND
SPI CIRCUITRY

SDO_CHA

GND
SDIO_ODM

R19
10K

VSPIEXT
CSB1_CHA

SDI_CHA

SCLK_CHA

Figure 48. AD9601 Evaluation Board Schematic Page 4

Table 13. Bill of Materials

Reference
Qty Designator Package Description Vendor Part Number
1 PCB PCB, AD9230 customer evaluation board, Rev. G Moog AD9230revG
7 C1, C3, C4, C5, 603 Capacitor, 1 μF, 0603, X5R, ceramic, 6.3 V, 10% Panasonic ECJ-1VB0J105K
C6, C7, C10
6 C8, C9, C11, 6032-28 Capacitor, 10 μF, tantalum, 16 V, 10% Kemet T491C106K016AS
C12, C14, C55
1 C17 402 Capacitor, 2.0 pF, 50 V, ceramic, 0402, SMD Murata GRM1555C1H2R0GZ01D
7 C27, C32, C33, 402 Capacitor, 0.33 μF, ceramic, X5R, 10 V, 10% Murata GRM155R61A334KE15D
C62, C63, C64,
C71
6 C28, C29, C30, 402 Capacitor, 120 pF, ceramic, C0G, 25 V, 5% Murata GRM1555C1H121JA01J
C31, C65, C70
10 C21, C22, C23, 402 Capacitor, 0.1 μF, ceramic, X5R, 10 V, 10% Murata GRM155R71C104KA88D
C24, C25, C26,
C34, C35, C36,
C39
1 CR4 603 LED green, SMT, 0603, SS-TYPE Panasonic LNJ314G8TRA
1 CR2 Mini 3P Diode, 30 V, 20 mA Agilent HSMS2812
1 F1 1210 Fuse, 6.0 V, 2.2 A trip current resettable fuse Tyco/Raychem NANOSMDC110F-2
15 E1, E2, E3, E4, Connector, header, 0.1" Samtec TSW-150-08-G-S
E5, E7, E8, E9,
E10, E12, E13,
E14, E31, E32,
E33
2 J2, J3 SMA end Connector, SMA PCB coax end launch, Johnson Johnson 142-0701-851
launch 142
10 L2, L3, L4, L5, 1206 Ferrite bead, BLM, 3 A, 50 Ω @ 100 MHz Murata BLM31PG500SN1L
L7, L12, L13,
L14, L15, R88
1 P8 Power jack, male, 2.1 mm power jack dc CUI Inc CP-102A-ND
1 R1 201 Resistor, 100 Ω, 0201, 1/20 W, 1% NIC Components NRC02F1000TRF
1 R2 603 Resistor, 499 Ω, 0603, 1/10 W, 1% NIC Components NRC06F4990TRF

Rev. 0 | Page 28 of 32
 AD9601
Reference
Qty Designator Package Description Vendor Part Number
2 R5, R6 402 Resistor, 36 Ω, 0402, 1/16 W, 1% Panasonic ERJ-2GEJ360X
2 R7, R16 402 Resistor, 15 Ω, 0402, 1/16 W, 5% Panasonic ERJ-2RKF15R0X
6 R10, R11, R13, 402 Resistor, 1 kΩ, 0402, 1/16 W, 1% NIC Components NRC04F1001TRF
R24, R25, R27
4 R12, R18, R19, 402 Resistor, 10 kΩ, 0402, 1/16 W, 5% NIC Components NRC04J103TRF
R26,
7 R15, C16, C18, 402 Resistor, 0 Ω, 0402, 1/16 W, 5% NIC Components NRC04ZOTRF
C19, C20, R89,
R90
4 RN1, RN2, RN3, 0402x8 Resistor array, SMT 0402; 0 Ω, ¼ W, 5%, Panasonic EXB2HV050JV
RN4 RESNEXB-2HV
3 L1, L8, L9 603 Resistor, 0 Ω, 0603, 1/10 W, 5% NIC Components NRC06ZOTRF
1 P9, P10 805 Resistor, 0 Ω, 0805, 1/8 W, 1% NIC Components NRC10ZOTRF
1 SW3 EVQ- Switch, light touch SMD Panasonic P12937SCT-ND
Q2F03W
1 T1 2020 Ferrite bead, 5 A, 50 V, 190 Ω @ 100 MHz Murata DLW5BSN191SQ2L
2 T2,T3 CD542 Transformer, 0.5 W, 30 mA Mini-Circuits ADT1-1WT+
1 U3 6-SC70 IC, buffer, inverter, UHS dual SC70-6 Fairchild NC7WZ16P6X
1 U5 6-SC70 IC, buffer, inverter, UHS dual OD out SC70-6 Fairchild NC7WZ07P6X
1 U7 DO-214AA Diode, 50 V, 2 A Micro Commercial S2A-TPMSTR-ND
1 U8 DO-214AB Diode, 30 V, 3 A (SMC) Micro Commercial SK33-TPMSCT-ND
1 U11 SOT-223 Voltage regulator, 3.3 V, 1.5 A Analog Devices ADP3339AKCZ-3.3
2 U9, U12 SOT-223 Voltage regulator, 1.8 V, 1.5 A Analog Devices ADP3339AKCZ-1.8
1 U4 LFCSP56 AD9230 12-bit, 170 MSPS/210 MSPS/250 MSPS, Analog Devices AD9230BCPZ-xxx
1.8 V ADC, LFCSP-56
2 P7, P11 HM-Zd PCB Connector, 2-Pr, 10-column, high speed, HM-Zd, Tyco 6469169-1
PCB-mounted
Do not install the following:
0 C2, C54 TAJD Capacitor, tantalum, SMT 6032, 10 μF, 16 V, 10% Kemet T491C106K016AS
0 C15, C37, C38, 402 Capacitor, 0.1 μF, ceramic, 10% Murata GRM155R71C104KA88D
C40, C41, C61,
C42, C43, C44,
C45, C46, C47,
C48, C49, C50,
C51, C52, C53,
C39, C56, C57,
C58, C59, C74,
C75, C60, C66,
C67, C68, C69,
C72
0 CR1 Led_ss LED green, USS type 0603 Panasonic LNJ314G8TRA
0 CR3 Diode Schottky diode Agilent HSMS2812
0 805 Tyco/Raychem NANOSMDC110F-2
0 E6, E15, E16, Connector, header, 0.1" Samtec TSW-150-08-G-S
E17, E18, E19,
E20
0 J1 10-pin TSW-110-08-G-D Samtec TSW-110-08-G-D
header
0 J4 SMA Connector, PCB coax SMA end launch, Johnson 142-0701-851
Johnson 142
0 L6 1206 Inductor, 10 nH Murata BLM31P500S
0 P12, P13, P14, SMA Amphenol RF ARFX1231-ND
P15

Rev. 0 | Page 29 of 32
AD9601
Reference
Qty Designator Package Description Vendor Part Number
0 R3, R14, R33, 402 Resistor, 49.9 Ω Susumu RR0510R-49R9-D
R34, R35, R48,
R49
0 R42, R43, R54, 402 Resistor, 10 kΩ NIC Components NRC04J103TRF
R85, R86
0 R28, R29, R30, 402 Resistor, 5 kΩ NIC Components NRC04F4991TRF
R31, R32
0 R37, R38 402 Resistor, 25 Ω NIC Components NRC04F24R9TRF
0 R39, R45 402 Resistor, 5 Ω NIC Components NRC04J5R1TRF
0 R58, R59 402 Resistor, 100 Ω NIC Components NRC04F1000TRF
0 R60, R61 402 Resistor, 240 Ω NIC Components NRC04J241TRF
0 R8, R9, R17, 402 Resistor, 0 Ω NIC Components NRC04ZOTRF
R36, R40, R41,
R44, R46, R47,
R87, R50, R51,
R52, R53, R55,
R56, R57, R62,
R63, R64, R65,
R66, R67, R68,
R69, R70, R71,
R72, R73, R74,
R75, R76, R77,
R78, R79, R80,
R81, R82, R83,
R84
0 P1, P2, P16, P17 805 Resistor, 0 Ω NIC Components NRC10ZOTRF
0 SW1 EVQ- Switch, light touch SMD Panasonic P12937SCT-ND
Q2F03W
0 T4 Transformer, RF, 0.4 MHz to 800 MHz, SMD case Mini-Circuits ADT1-1WT+
style CD542
0 T5, T6 sm-22 Balun M/A-Com MABA007159-0000
0 U2 SOIC-8 PIC12F629 Microchip Tech PIC12F629-I/SN
0 U6 Crystal Cvhd_956 crystal CVHD_956
0 U10 SOT-223 Regulator ADP3339AKCZ-5.0
0 Z1 16CSP4X4 AD8352
0 U1 16CSP8X8 AD9515
0 P6 8-pin power connector post Wieland Z5.530.0825.0
0 P6 8-pin power connector top Wieland 25.602.2853.0

Rev. 0 | Page 30 of 32
 AD9601

OUTLINE DIMENSIONS
0.30
8.00 0.60 MAX 0.23
BSC SQ
0.60 MAX 0.18
PIN 1
43 56 INDICATOR
1
PIN 1 42
INDICATOR

TOP 7.75 EXPOSED 4.45

VIEW BSC SQ PAD 4.30 SQ
(BOTTOM VIEW) 4.15

0.50
0.40 29 14
28 15
0.30
0.30 MIN
6.50
0.80 MAX REF
1.00 12° MAX
0.85 0.65 TYP
0.80 0.05 MAX
0.02 NOM
SEATING 0.50 BSC COPLANARITY
PLANE 0.20 REF 0.08

112805-0
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2

Figure 49. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

8 mm × 8 mm Body, Very Thin Quad
(CP-56-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9601BCPZ-200 1 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-2
AD9601BCPZ-2501 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-2
AD9601-250EBZ1 CMOS Evaluation Board with AD9601BCPZ-250
1
Z = RoHS Compliant Part.

Rev. 0 | Page 31 of 32
AD9601

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D07100-0-11/07(0)

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