Chapter 2

Power Electronic
Devices
 Control of Energy
Consumption
E  Pt
Power
On-time
(ton)
P

Off-time
Time
(toff) Duty Ratio (K)
t)
Period ( ton
E= Pt
t
 Load Switching
Power
On-time
(ton)
P

Off-time
(toff) Time (t)

t)
Period (

ton toff
 Ideal Switch
vsw
+
vs
i R R
vs vt i

vs
-

Vsw
 Bi-polar Transistor (BJT)
(C)
(C)
(C) IC
Collector
VCB
N IB
Base (B)
(B) VCE
P (B)
N
VBE
Emitter
IE
(E)
(E)

IC   I B
(E)

I E = I B + IC
VCE = VCB + VBE
 (C)
IC
Characteristics of Bi-polar
VCB Transistor
IB
(B) VCE

VBE
Saturation Region IB1
IE

IB (E) IC
IB2< IB1

Linear Region

IB= 0

V 0.6 VCE
BE Cut Off Region

Base Characteristics Collector Characteristics

 IC IC IB max

RL VCC
(1)
IB RL

V CE
V CC
(2)

IB = 0

VCC VCE
VCC = VCE + RL I C
Closed At point (2)
At point (1)
switch IC is very small
VCE is very small
IC 
VCC Open VCE  VCC
RL switch
 Example
• A transistor has a current gain of 200
in the linear region and 10 in the
saturation region. Calculate the base
current when the collector current is
equal to 10 A assuming that the
transistor operates in the linear
region. Repeat the calculation for
the saturation region
 Solution
In the linear region

I 10
IB = C = = 50 mA
 1 200

In the saturation region

IC 10
IB = = =1 A
 2 10
 Main Features of BJT
• Current controlled device
– Base current must be present during the
closing period
– High base losses
• Low current gain in the saturation
region
• Can operate at high frequencies
 Field Effect Transistor (FET)
(D) ID V GS1
ID
VGS2 < V GS1
(G)
VDS
VGS3 < V GS2

VGS
0 < VGS4 < V GS3
(S)
VDS
 Main Features of FET
• Voltage controlled device
• Low gate losses
Thyristors (Four Layer Diode)
Anode (A) Anode (A)
Anode (A) IA
IA IA

Ic2
P Q2
P Q1
N N N
P PIh Ic1
P VRB
N N Q2
Q1 VBO VAK
IA

Cathode (K) Cathode (K)

Cathode (K)
Thyristors [Silicon Controlled Rectifier
(SCR)]
Anode (A) IA

Ig = max
Ig = 0
Ig > 0
Ih
Gate (G) VRB

V
AK

V VBO
Cathode (K) TO
 Closing Conditions of SCR
Anode (A)
1. Positive anode to
cathode voltage
(VAK)
Gate (G)
2. Maximum
triggering pulse is
Cathode (K)
applied (Ig)
Closing angle is a
 Opening Conditions of SCR
IA
1. Anode current is
below the holding Ig = 0
value (Ih)
Ih
VRB

V
AK

Opening angle is 
 Other Power Devices (Darlington
Transistor)
IC
  is low in saturation region
IB (C)

I e2 = (1 +  2 ) I b2 = (1 +  2 ) (1 + 1 ) I b1
Ib1
(B)
Ib2
I e2
1 + total = = (1 +  2 ) (1 + 1 )
I b1
 total = 1  2 + 1 +  2 Ie2

If 1 =  2 = 10; total =120 (E)

Darlington Transistor
 IGBT: Insulated Gate Bipolar Transistor
BJT (Bipolar Junction Transistor)

• Low Vce forward drop

• Low losses at collector (power) circuit during conduction

• High switching freq (better than SCRs)

• Low current gain at saturation reg (conduction)

• High base current

• High base losses (low efficiency)

• Complex & expensive switching circuit

M OSFET (M OS Field Effect Transistor)

• Voltage controlled device: small input current

• M uch simpler & less expensive trigger circuit

• Low Vds forward drop at low voltage (<200V)

• At low voltage: fast switching

 IGBT: Insulated Gate Bipolar Transistor

IGBT
• MOSFET at input (switching)
circuit & BJT at output (power)
circuit
• Is of the MOSFET triggers
(closes) the BJT (Is=Ib)
• Low losses in input (switching)
circuit
• Relatively low power (output)
circuit losses
• May use for high switching
operation
• MOSFET & BJT may be included
in the same wafer: IGBT
Characteristics of an IGBT (N-channel
type)
 Ratings of Power Electronic Devices

• Steady State Circuit ratings:

• The current and voltage of the circuit
should always be less than the
device ratings.
 Ratings of Power Electronic Devices

• Junction temperature: Losses inside

solid-state devices are due to
impurities of their material as well as
the operating conditions of their
circuits.
 Ratings of Power Electronic Devices
• During the conduction period, the voltage drop
across the solid-state device is about one volt.
This voltage drop multiplied by the current inside
the device produces losses.
• When the device is in the blocking mode (open), a
small amount of leakage current flows inside the
device which also produces losses.
• The gate circuits of the SCRs and FETs, and the
base circuits of the transistors, produce losses
due to their triggering signals.
• Every time the solid state device is turned on or
off, switching losses are produced. These losses
are usually higher for faster devices, and for
devices operating in high frequency modes.
 Ratings of Power Electronic Devices

• Surge current: It is the absolute maximum

of the non-repetitive impulse current
 Ratings of Power Electronic Devices

• Switching time:
• Turn-on time is the interval between
applying the triggering signal and the turn-
on of the device.
• The turn-off time is the interval from the on-
state to the off-state.
• The larger the switching time the smaller is
the operating frequency of the circuit.
 Ratings of Power Electronic Devices

• Critical rate of rise of current (or

maximum di/dt): A solid-state device can
be damaged if the di/dt of the circuit
exceeds the maximum allowable value of
the device. di/dt damage can occur even if
the current is below the surge limit of the
device. To protect the device from this
damage, a snubbing circuit for di/dt must be
used.
 Ratings of Power Electronic Devices

• Critical rate of rise of voltage (or

maximum dv/dt): When dv/dt across a
device exceeds its allowable limit, the
device is forced to close. This is a form of
false triggering. It may lead to excessive
current or excessive di/dt. To protect the
device against excessive dv/dt, a snubbing
circuit for dv/dt must be used.
 di/dt and dv/dt Protection
Rs Cs
+ -

Ls

V Load
 Snubbing Circuit
Rs Cs
+ -

Ls

Load
V I
1

Load impedance
1
Z L = RL + j LL +
j CL
 Snubbing Circuit
Rs Cs
+ -

Ls

V Load
I
1

R = Rs + RL
V( S )
I 1( S ) =
 1  L = Ls + LL
 R + SL + 
 CS  Cs C L
C=
Cs + C L
 Snubbing Circuit
Rs Cs
+ -

Ls

V Load
I
1

C Vn
i1 ( t ) = e −  n t sin  n ( 1 −  2 ) t 
(1− 2 )  

1 R C
n = ; =
LC 2 L
 Snubbing Circuit: Ls
di1 − CV  n2  −  n t
= e sin [  n ( 1 −  2 ) t ] + CV  n2 e −  n t cos[  n ( 1 −  2 ) t ]
dt (1− 2 )
Worst Scenario for Maximum di/dt:
When the caps are not charged at t=0
di1  di1  V
= CV  2
 dt  =
dt
max n   max L

VBO
Ls =
V
− LL Ls = − Ll
di1  di 
( )max 0.5  
dt  dt  rating
Snubbing Circuit: Cs & Rs
Assume the cap is initially discharged

Vscr = Rs i1

dVscr di1
= Rs
dt dt
dVscr V
= Rs
dt L
 Snubbing Circuit: Cs & Rs
Assume the cap is discharging
t
After the SCR is closed −
Rs Cs Vo Rs C s
+ - i2 = e
I
2
Rs
Ls
t
−
di2 − Vo Rs C s
= e
V Load
dt Rs2 C s

 di2  − Vo
 dt  =
  max Rs2 C s