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55 views41 pagesDatasheet LCD
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/ 41
MicrocHip MCP23008/MCP23S08
8-Bit I/O Expander with Serial Interface
Features
+ B-bit remote bidirectional YO port
= VO pins default to input
High-speed 7C™ interface (MCP23008)
= 100 kHz
= 400 kHz
= 1.7 MH
High-speed SPI™ interface (MCP23808)
= 10 MHz.
Hardware address pins
+ Three for the MCP23008 to allow up to eight
GPS
ao—eds & sb——cps
RESET 6B rgb ++ os
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1DS219198.pago 1 MCP23008/MCP23S08
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Von POR ‘Configuration!
Coal
Vss ———_{] Registers
DS219196-page 2 © 2005 Microchip Technology inc. MCP23008/MCP23S08
1.0 DEVICE OVERVIEW
‘The MCP23X08 device provides 8-bit, general
purpose, parallel /O expansion for IC bus or SPI
applications. The two devices differ in the number of
hardware address pins and the serial interface:
+ MCP23008 — [2G interface; three address pins
+ MCP23808 — SPI interface; two address pins
‘Tho MCP23X08 consists of multiple 8-bit configuration
rogistors for input, output and polarity selection. Tho
system master ean enable the /Os as either inputs or
‘outputs by writing the VO configuration bits. The data
for each input or output is kept in the corresponding
Input or Output register. The polarity of the Input Port
register can be inverted with the Polarity Inversion
register. Allragisters can be read by the system master.
‘Tho interrupt output can be configured to activate
Under two conditions (mutually exclusive):
1. When any input state differs from its
corresponding input port register state. This is
sed to indicate to the system master that an
input state has changed,
2. When an input stata differs from a preconfigured
rogistor value (DEFVAL register).
‘The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition,
that caused the interrupt.
Tho Power-on Resot (POR) sets the registers to their
default values and initializes the device state machine,
‘The haréware address pins are used to determine the
davice address.
1.1 Pin Descriptions
TABLE 1-1: PINOUTDESCRIPTION
Pin | PDIPIS Pin
Name |" ole, |8°° |zype Function
SCUSCK| 1 | 1 | I | Serial dock input
SDAIS| [2 | 2 | VO |Sorial data VO (MCP23008 Serial data input (MGP23808)
A280 | 3 VO |Hardware address input (MCP23008)Serial data output (MCP23808).
/A2 must be biased externally.
Al 4 | 4 _| 1 [Hardware address input, Must be biased externally
AO 5 | |_| [Hardware address input. Must be biased externally.
RESET | 6 | 6 | 1 |Exteratreset input
NCIGS_|_T_|_7_| 1 _[Noconnect (MCP23008)External chip select input (MCP23808).
INT | 8 [0 [interrupt output. Can be configured for activerhigh,active-low or open-drain.
vss 9 | 8 | P [Ground
GPO 10 | 42 | VO | Bidirectional VO pin. Can be enabled for interrupton-change andlor internal weak
pul-up resistor.
CPt 11 | 13 | VO [Bidirectional /O pin. Can’be enabled forinterrupt-on-change andlor intemal weak
pull-up resistor.
GPa 12 | 14 | VO | Bidirectional VO pin. Gan be enabled for interupt-on-change andlor intemal woak
pulkup resistor.
GPs 13 | 15 | VO | Bidirectional VO pin. Can be enabled for interrupton-change andlor intemal weak
pull-up resistor.
GPa 14 | 46 | VO | Bidirectional /}O pin. Can be enabled for interrupt-on-change andlor intemal weak
pulkup resistor.
oP 45 | 17 | VO [Bidirectional VO pin. Can be enabled forinterrupton-change andlor intemal weak
pull-up resistor.
GPé 46 | 18 | VO | Bidirectional VO pin. Can be enabled for interrupton-change andlor internal weak
pull-up resistor.
or 17 | 18 | VO [Bidirectional /}O pin. Can be enabled for interupton-change andlor intemal woak
pull-up resistor.
Voo 18 | 20 | P [Power
NC 70,1
© 2005 Mierochip Technology Ine.
DS219196-page 3 MCP23008/MCP23S08
1.2 Power-on Reset (POR)
‘The on-chip POR circuit holds the device in reset until,
\Voo has reached a high enough voltage to deactivate
the POR circuit (i., release the device from reset)
Tho maximum VoO rise time is specified in Section 2.0
“Electrical Characteristics”
When the device exits the POR condition (releases,
reset), device operating parameters (i0., voltage,
‘tomperatur, serial bus frequency, etc.) must be met to
‘ensure proper operation,
1.3 Serial Interface
This block handles the functionality of the PC
(MCP23008) or SPI (MCP23808) interface protocol
‘The MCP23X08 contains eleven registers that can be
addressed through the serial interface block (Table 1-2)
TABLE 1 REGISTER ADDRESSES
‘Address ‘Access to:
oon TODIR
oan IPOL,
oan. GPINTEN
03h DEFVAL
oan INTGON
05h TOCON
oeh GPPU
O78 INTF
oan INTCAP (Read-only)
08h PIO
oan LAT
1.3.4 SEQUENTIAL OPERATION BIT
‘The Sequential Operation (SEQOP) bit (IOCON
register) controls the operation of the address pointer.
Tho address pointer can either bo enabled (dofault) to
allow the address pointer to increment automatically
after each data transfer, oritcan be disabled.
When operating in‘ Sequential mode
(IOCON.SEQOP = 0), the address pointer automati-
cally increments to the next address ater each byte
is clocked.
‘When operating in Byte mode (IOCON.SEQOP = 2),
the MCP23x08 does not increment its address
‘counter after each byte during the data transfer. This
‘ives the ability to continually read the same address.
by providing extra clocks (without additional control
bytes). This is useful for polling the GPIO register for
data changes.
132 PCM INTERFACE
1.3.2.1 [2C Write Operation
The 12C Write operation includes the control byte and
register address sequence, as shown in the bottom of
Figure 1-1. This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23008. The operation is ended with a STOP
‘or RESTART condition being generated by the master.
Data is written to the MCP23008 after every byte
transfer. If a STOP or RESTART condition is
generated during a data transfer, the data will not be
\writton to the MCP23008.
Byte writes and sequential writes are both supported
by the MCPZ3008. The MCP23008 increments its
address counter after each ACK during the data
transfer.
1322 PC Read Operation
The °C Read operation includes the control byte
sequence, as shown in the bottom of Figure 1-1. This
sequence is followed by another contro byte (includ-
ing the START condition and ACK) with the RW bit
‘equal to a logic 1 (RIW = 1). The MCP23008 then
transmits the data contained in the addressed register.
‘The sequence is ended with the master generating
STOP or RESTART condition
1.3.23 PC Sequential Write/Read
For soquential operations (Write or Read), instoad of
transmiting a STOP or RESTART condition after the
data transfer, the master clocks the next byte pointad to
by the address pointer (see Section 1.3.1 “Sequential
Operation Bit” for details regarding sequertial
poration conto)
‘The sequence ends withthe master sending a STOP or
RESTART condition
The MCP23008 address pointer will rll over to
address zero after reaching the last register address.
Rofor to Figure 1-1
1.3.3 SPI™ INTERFACE
133.1 SPIWrite Operation
‘The SPI Write operation is startod by lowering CS. The
Wirte command (slave address with RW bit lared) is
then clocked into the device. The opcode i followes by
an address and atleast one data byto.
1.332 SPI Read Operation
‘The SPI Read operation is started by lowering CS. The
‘SPI read command (slave address with RIW bit set) is
then clocked into the device. The opcode is followed by
aan address, with at least one data byte being clocked
ut of the device.
DS219196-page 4
{© 2008 Merochip Technology ine MCP23008/MCP23S08
FIGURE 1-4 McP23008 2c™ DEVICE PROTOCOL
[s]-start
~ RESTART
al S| oP [Ww] ADR} —» Bw]... B] mf
(P]-stop
Ww] - Write ;—misr[_oP [R| Dour]... [ Dour P
R]-Read
OP] - Device opcode m(sr[_op [w| On ]..[ Ow ||P
'ADDR | - Device addross L_ py]
DouT_|- Data out from MCP23008
Din] - Data into MCP23008,
[or [Rr [Dour]... [ Boor | »[P]
-———6sr|_oP [Rr] Dour Dour P
|wSrl_ oP [W] ADDR | OW Dx ]->[P]
___»fP
Byte and Sequential Write
eye [8] oP |W) ADDR |—m[ DN }—»[P]
Soquential [8] OP |W] ADDR |—e{ Dw]... DN }—»>[P
Byte and Sequential Read
Bye[S[|_op [R|-»sr| op [Rr] dour | —m{P
sequential S| oP [R]-m SR] oP [R] Dour]...[ Dour} m[P]
1333 SPI Sequential Write/Read 1.4 Hardware Address Decoder
For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the address pointer.
‘Tho sequence ends by the raising of CS.
‘The MCP23S08 address pointer will roll over to
‘address zero after reaching the last register adress.
‘Tho hardware address pins aro used to determine the
device address. To address a device, the correspond
ing address bits in the control byte must match the pin
state.
+ MCP23008 has address pins A2, A1 and AQ.
+ MCP23808 has address pins A1 and AO,
‘Tho pins must be biased externally.
{© 2005 Microchip Tecnology Inc.
DS219196-page 5 MCP23008/MCP23S08
1.41 ADDRESSING I’C DEVICES FIGURE 1-2: e™ CONTROL BYTE
(McP23008) FORMAT
The MCP23008is a stave [°C davice that supports 7-bit :
slave addressing, with the readiwrite bit filing out the Control Byte
‘control byte, The slave address contains four fixed bits S [0 [7 [0] 0 [A2|Ai [Ao TRW]ACK]
and thes usecdefined hardware address bi (pins A2, : *
Wahi ierscecttns” | | een 8 F
142 ADDRESSING SPI DEVICES Siar ROW bit
(mcr23s08) it ACK bit
‘The MCP23808 is a siave SPI device. The siave
address contains five fixed bits and two user-defined
hardware address bits (pins A1 and AO), with the
readiwtte bit filing out the control byte. Figure 1-3 SPI™ CONTROL BYTE.
‘shows the control byte format. FORMAT
as
Control Byte ————»
O[ 710] 0] 0 [AT[AOT RW
i Slave Adcross —i
Ruweit
FIGURE 1-4: Fc™ ADDRESSING REGISTERS
SPO LALO [RSL AT [AO] 0 PACK AT [AS [AB LAT AS | RET AT | AD [ACR
RIW=0 5
+— Device Opcode —», «Register Address ——_——+!
‘The ACKs are provided by the MCP23008.
FIGURE 1-5: ‘SPI™ ADDRESSING REGISTERS
ws
TLT[OLOL OTA AOlRW) = LAT AST AST AES ETAT A
“+ avice opcode —___y) @—__—Registar Ascrass —
DS219196-page 6 © 2005 Microchip Technology inc. MCP23008/MCP23S08
1.5. GPIO Port 1.6 Configuration and Control
The GPIO module contains the data port (GPIO), Registers
intemal pull up resistors and the Output Latches The Configuration and Control blocks contain the
(OLAT), registers 26 shown in Table 13.
Reading the GPIO register reads the value on the port.
Reading the OLAT register only reads the OLAT, not
the actual value on the port.
Writing to the GPIO register actually causes a write to
the OLAT. Writing to the OLAT register forces the:
associated output drivers to drive to the level in OLAT.
Pins configured as inputs tum off the associated output
diver and put itn high-impedance.
TABLE 1-3: CONFIGURATION AND CONTROL REGISTERS
Racist |Adsers | yey | one | nes | ona | ona | ot2 | ont | oxo | PORRST
[A
wet [oh | er | ps | es | ease Yooo 000
wwreon | 04 | Toor | toce | 1005 | toot | toca [toca | oct | 1060 | 000-000
ToCON | 0 [ESSENSE Sea0 | Oss. RAEN] oor —[wrPOU [EEE 00" 000-
coef we | pur | pu | eu | pur | us [pw eu | pw [avon oo0o
RTCA |e [oer [1066 [ops [ope [ros [ropa [rot [oho |oooo oo0o
oa [aa [our [ove [015 [ove [013 [012 out 010 0000-0000
* Not used on the MCP23008.
© 2005 Mierochip Technology Ine. 5219196: page 7 MCP23008/MCP23S08
1.6.1 0 DIRECTION (IODIR) REGISTER
Controls the direction ofthe data /O.
‘When a bit is set, the corresponding pin becomes an
input When a bit is clear, the corresponding pin
bacomes an output.
REGISTER 1-1: IODIR - 1/0 DIRECTION REGISTER (ADDR 0x00)
RW RW RW OR ORM RAV RR
107 108 | _ 105 104 103 to2_ | 101 100
bit7 ito
bit7-0 1072100: These bits control the direction of data /O <7:0>,
11= Pins configured as an input.
(0 = Pinis configured as an output
Legend:
R= Readable bit W=Writable bit Inimplomented bit, road aso"
n= Value at POR 2° = Bitis sat Bitis deared x= itis unknown
DS219196-page 8
© 2005 Microchip Technology inc. MCP23008/MCP23S08
1.62 INPUT POLARITY (IPOL) REGISTER
‘Tho IPOL register allows the user to configure the
polarity on the corresponding GPIO port bits.
Ifa bit is set, the corresponding GPIO register bit will
rofloct the inverted value on the pin,
REGISTER 1-2; IPOL — INPUT POLARITY PORT REGISTER (ADDR 0x01)
RW RW RW RWO RO RO
RW RM-0
7, PS PS Pa PS 1P2 PT PO
bit7 bio
bit 7-0 IP7:1PO: These bits control the polarity inversion of the input pins <7:0>,
‘GPIO register bt wil reflect the opposite logic state of tho input pin.
‘GPIO register bit wil reflect the same logic state of the input pin.
Legend:
R= Readable bit W= Writable bit
Value at POR
Inimplomonted bit, read as ‘0°
'o'=Bitis cleared x= Bitis unknown
© 2005 Microchip Technology Ine. DS219196-page 9 MCP23008/MCP23S08
1.63 INTERRUPT-ON-CHANGE
CONTROL (GPINTEN) REGISTER
Tho GPINTEN register controls the interrupt-on-
‘change feature for each pin,
If a bit is set, the corresponding pin is enabled for
interrupton-change. Tho DEFVAL and INTCON
registers must also be configured if any pins are
‘enabled for interupt-on-change.
GPINTEN - INTERRUPT-ON-CHANGE PINS (ADDR 0x02)
Ro RW.O RWO0 RWO RMO RWO RWO RWO
GPINT7 | GPINTS | GPINTS | GPINT4 | GPINT3 | GPINT2| GPINT | GPINTO
bit? ito
REGISTER 1.
bit7-0 GPINTT:GPINTO: General purpose I/O interrupt-on-change bits <7:0>,
11 = Enable GPIO input pin for interupt-on-change event.
(0 = Disable GPIO input pin for interrupt-on-change event,
Refer to INTCON and GPINTEN.
Legend:
R= Readable bit W=Writable bit
falue at POR 2'= Bitis set
Inimplemented bit, read aso
Bitis cleared _x=Bitis unknown
1DS219196-page 10 © 2005 Microchip Technology inc. MCP23008/MCP23S08
1.6.4 DEFAULT COMPARE (DEFVAL)
REGISTE!
CHANGE
The defauit comparis
DEFVAL register. If
FOR INTERRUPT-ON-
son value is configured in the
‘enabled (via GPINTEN and
INTCON) to compare against the DEFVAL register, an
‘opposite value on the associated pin will cause an
intorupt to occur
REGISTER 1-4:
bit 7-0
DEFVAL - DEFAULT VALUE REGISTER (ADDR 0x03)
RW0 RMO RW RWO RWO0 RMD RWO RWO
DEF? | DEF6 | DEFS | DEF4 | DEFS | DEF2 | DEF! | DEFO
bi bit
DEF7:DEFO: These bits set the compare value for pins configured forinterrupt-on-change from
dofaults <7:0>. Refer to INTCON.
Ifthe associated pin lavel is the opposite from the register bit, an interrupt occurs.
Refer to INTCON and GPINTEN,
Legend:
R= Readable bit W= Writable bit U-= Unimplemented bit, read as ‘0
luo at POR “Y= Bitis sot 'o'= Bitis cleared
its unknown
© 2005 Microchip Technology Ine. (0219196: page 11 MCP23008/MCP23S08
165 INTERRUPT CONTROL (INTCON)
REGISTER
Tho INTCON register controls how the associated pin
value is compared for the interrupt-on-change feature,
Ifa bit is set, the corresponding I/O pin is compared
‘against the associated bitin the DEFVAL ragister. if a
bit value is clear, the corresponding VO pin is
‘compared against the previous value,
REGISTER 1-5: INTCON - INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04)
Rwo RWO RWO RWO RMO RO RWO RWO
toc? [| ics | 10cs [ ice | 1ocs | 1ocz | loci | 10co
bit7 ito
bit7-0 _10€7:I0C0: These bits control how the associated pin value is compared for intarrupt-on-
change <7:0>.
41 = Controls how the associated pin value is compared for interrupt-on-chango.
0= Pin valuo is compared against the previous pin value.
Refer to INTCON and GPINTEN.
Legent
R= Readable bit W=Writable bit U= Unimplementad bit, read as ‘0°
falue at POR Bitisset___‘0'=Bitiscleared x= Bits unknown
DS219196-page 12 © 2005 Microchip Technology inc. MCP23008/MCP23S08
1.6.6 CONFIGURATION (IOCON)
REGISTER
‘The IOCON register contains several bits for
‘configuring the device:
+ The Sequential Operation (SEQOP) controls the
incrementing function of the address pointer. If
the address pointer is disabled, the address
pointer does not automatically increment after
‘each byte is clocked during a Serial transfer. This
‘feature is useful whan its desired to continuously
The Hardware Addross Enable (HAEN) control it
‘enables/disables the hardware address pins (A2,
‘A1)on the MCP23808. This bits not used on the
MCP23008. The address pins are always enabled
‘on the MCP23008,
The Open-Drain (ODR) contro bit
‘enablesidisables the INT pin for open-drain
configuration.
‘The Interrupt Polarity (INTPOL) contol bit sets
the polarity ofthe INT pin. This bt is functional
‘only when the ODR bits cleared, configuring the
poll (road) or modify (write) a register.
+ The Slew Rate (DISSLW) bit controls the slew
rate function on the SDA pin. If enabled, the SDA
slew rate willbe controlled when driving from a
INT pin as active push-pull
high to a low.
REGISTER 1-6: _ IOCON —/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)
uo uo RM —RWO RWO ORWO RW UO
= By se00r | vissiw] HAEN | ODR | INTPOL [lee
bit7 bit 0
bit7-6 _Unimplemented: Read as ‘o'.
bitS __ SEQOP: Sequential Operation mode bit.
‘Sequential operation disabled, address pointer does not increment
‘0 Sequential operation enabled, address pointer increments.
bit4 —_DISSLW: Slew Rate control bit for SDA output
= Slew rate disabled
Slew rate enabled,
bits HAEN: Hardware Addrss Enable bit (MCP23S08 only),
‘Address pins are always enabled on MCP23008,
Enables the MCP23808 address pins.
‘0= Disables the MCP23808 address pins
bit 2 DR: This bit configures the INT pin as an open-.
1 = Pullup enabled,
= Pullup disabled
Legend:
R= Readable bit W=Writable bit
falue at POR 11'= Bitis set
Inimplomonted bit, road aso"
Bitis cleared Bitis unknown
DS219196-page 14 © 2005 Microchip Technology inc. MCP23008/MCP23S08
1.68 INTERRUPT FLAG (INTF)
REGISTER
‘The INTF register reflects the interrupt condition on the.
por pins of any pin that is enabled for interrupts via the.
GPINTEN register. A ‘set’ bit indicates that the
associated pin caused the interrupt
‘This rogistor is ‘read-only’. Writes to this register will bo
Ignored.
REGISTER 1-8:
bit 7-0
INTF wil always reflect the pin(s) that
havo an intarrupt condition. For example,
‘one pin causes an interrupt to occur and is
captured in INTCAP and INF. If, before
clearing the interrupt, another pin changes.
Which would normally cause an interrupt, it
willbe rflactad in INTF, but not INTCAP.
INTF ~ INTERRUPT FLAG REGISTER (ADDR 0x07)
RO RO RO RO RO RO RO Ro
int? [_INT6 | INTS | INTS ira INT2 [| INTT | INTO
bit7 itd
INTZ:INTO: These bits reflect the interrupt condition on the port. Wil reflect the change only if
interrupts are enabled (GPINTEN) <7:0>.
Pin caused interrupt
Interrupt not pending,
Legend:
R= Readable bit W= Writable bit
faluo at POR Biisset 0
Inimplemented bit, read as ‘0
Bitis cleared its unknown
© 2005 Mierochip Technology Ine. 0S219196-page 15, MCP23008/MCP23S08
169 INTERRUPT CAPTURE (INTCAP)
REGISTER
Tho INTCAP rogistor captures the GPIO port value at
the time the interrupt occurred, The register is ‘read-
‘only’ and is updated only when an interrupt occurs. The
register wil remain unchanged until the interrupt is
‘loared via a read of INTCAP or GPIO.
REGISTER 1-9: INTCAP - INTERRUPT CAPTURED VALUE FOR PORT REGISTER
(ADDR 0x08)
Rx Rx Rx Rx Rx Rx Re Rx
icp7_| icPs | icPS | icP4 | icPs | 1cP2 | cpt | IcPO
bit7 ito
bit 7-0 ICP7:ICPO: Thase bits reflec the logic level on the port pins atthe time of interrupt due to pin
change <7:0>
1 = Logic-high
0 Logic-ow.
Legend:
R= Readable bit W=Writable bit U = Unimplomented bit, read as ‘0°
falue at POR Bitisset___‘0" = Bitis cleared itis unknown,
DS219196-page 16 © 2005 Microchip Technology inc. MCP23008/MCP23S08
1.610 PORT (GPIO) REGISTER
‘The GPIO register reflects the value on the port
Reading from this register reads the port. Writing to this
register modifies the Output Latch (OLAT) register
REGISTER 1-10: GPIO - GENERAL PURPOSE I/O PORT REGISTER (ADDR 0x09)
RW0 RMAO RW RWO RM ORM RW RIO.
ce7_| GPs | GPS | GPa cpa | GP2 | GP1 | GPO
bit7 ito
bit 7-0 PO: Thase bits reflect the logic level on the pins <7:0>.
Logicthigh,
Logic-low,
Legend:
R = Readable bit W= Writable bit U = Unimplemented bit, read as ‘0
faluo at POR 'V=Bitissot ‘0 = Bitis cleared its unknown
© 2005 Microchip Technology Ine. 219196 page 17 MCP23008/MCP23S08
1.6.11 OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output
latches. A read from this register results in aread of the
OLAT and not the pot itself. A write to this register
modifies the output latches that modify the pins
‘configured as outputs.
REGISTER 1-11:
bit 7-0
OLAT — OUTPUT LATCH REGISTER 0 (ADDR 0x0A)
RW0 RWO RWO RWO RM ORO RW RW.
a7 | os | os | o4 os oz | on | O10
bit7 ito
1 = Logie-high
0= Logiclow.
Legend:
R= Readable bit
falue at POR
W=Writable bit
Bitis set
(OL7:OLO: These bits reflect the logic level on the output latch <7:0>.
Unimplomentod bt, road as ‘0°
Bitis eared _x= itis unknown
DS219196-page 18
© 2005 Microchip Technology inc. MCP23008/MCP23S08
1.7 Interrupt Logic
The interrupt output pin wil activate if an internal
Interrupt occurs. The interrupt block is configures by
the following rogisters:
+ GPINTEN - enables the individual inputs
+ DEFVAL — holds the values that are compared
against the associated input port values
+ INTCON - controls ifthe input values are
‘compared against DEFVAL or the previous values
‘on the port
+ IOCON (ODR and INPOL) ~ configures the INT
pin 2s push-pull, open-drain and activelevel
(Only pins configured as inputs can cause interrupts.
Pins configured as outputs have no affact on INT.
Interrupt activity onthe port will use the port value to
'bo captured and copiad into INTCAP. The interrupt will
remain active until the INTCAP or GPIO register is
road. Writing to these registers will not affect the
interrupt
‘Tho fist interrupt event will cause the port contents to
‘be copied into the INTCAP register. Subsequent
interrupt conditions on the port will not caus an
intertupt to occur as long as the interrupt is not cleared
by a read of INTCAP or GPIO.
4.7.4 INTERRUPT CONDITIONS
There are two possible configurations to cause
interrupts (configured via INTCON):
1. Pins configured for interrupt-on-pin-change
will cause an interupt to occur fa pin changes
to tho opposite stato. The dofault sats is reset
fier an interupt occurs. For example, an
interrupt occurs by an input changing from 1 to
0. The new intial stata forthe pin is logic 0
2. Pins configured for interrupt-on-change from
Fegister value will cause an interrupt to occur i
the corresponding input pin diffrs from the
register bit, The intrrupt condition will remain as
long as the condition exists, regardless ifthe
INTAP oF GPIOis read
‘Soe Figure 1-6 and Figure 1-7 for more information on
intorupt operations.
FIGURE 1-6: INTERRUPT-ON-PIN-
CHANGE
Road GPIU Port value
Port value.
iscaptured or INTCAP is captured
int INTCAP, into INTCAP
INTERRUPT-ON-CHANGE
FROM REGISTER
DEFAULT
DEFVAL
cP 7 6 5 4 3 2 10
nr Lefaenvel— Yachwvel
Port value.
is captured Read GPIU
into INTCAP or INTCAP
(INT clears only ifintorupt
Condition does not exist.)
{© 2005 Microchip Tecnology Inc.
08219196-page 19 MCP23008/MCP23S08
NoTEs:
108219198-page 20 2005 Microchip Technology nc. MCP23008/MCP23S08
2.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings t
‘Ambient temperature under bias. o . vs se sens AOC 10 +125°C
‘Storage temperature “85°C to +180°C
Voltage on Voo with respect to Vss -03V 10 +55V
Voltage on all other pins with respact to Vs (excapt V0). -0.8V to (Voo + 0.6V)
‘Total power dissipation (Note) 700 mW
‘Maximum current out of VSS pin 160 mA
‘Maximum current into VoO pin. . 125 mA
Input clamp current, is (Vi < 0 0r V1 > VDD) a son sen #20 AMA,
(Output clamp current, lox (Vo < 0 or Vo > Von) +20 mA
‘Maximum output current sunk by any output pin 25 mA
‘Maximum output current sourced by any output pin. 25 mA
Note: Power dissipation is calculated as follows:
ois = Voo x {100 - E lov} + 5 {(VD0-VoH) x lor} + E(VOL x lou)
T NOTICE: Stresses above those listed under “Absolute Maximum Ratings’ may cause permanent damage to the
device. This s a stress rating only and functional operation ofthe device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affact device reliability.
© 2005 Microchip Technology Ine. (08219196: page 2+ MCP23008/MCP23S08
24 DC Characteristics
‘Operating Conditions (unless otherwise indicated):
DC Characteristics 1.BV < Von < 5.5V at -40°C < Ta < +85°C (|-Temp)
[gyevin se ev ata > 7
<0 es
DS219196:-page 26 © 2005 Microchip Technology inc. MCP23008/MCP23S08
FIGURE 26: SPI™ OUTPUT TIMING
TABLE 2-3: SPI™ INTERFACE AC CHARACTERISTICS
Operating Conditions (unless otherwise indicated):
‘SPI™ Interface AC Characteristics | 1.8V < VoD < 5.5V at -40°C < Ta < +85°C (I-Temp)
4.5V