MCP23016

16-Bit I2C™ I/O Expander

Features Package Types
• 16-bit remote bidirectional I/O port PDIP, SOIC, SSOP
- 16 I/O pins default to 16 inputs Vss •1 28 GP0.7
• Fast I2C™ bus clock frequency (0 - 400 kbits/s) GP1.0 2 27 GP0.6
GP1.1 3 26 GP0.5
• Three hardware address pins allow use of up to GP1.2 4 25 GP0.4

MCP23016
GP1.3 5 24 GP0.3
eight devices
INT 6 23 GP0.2
• High-current drive capability per I/O: ±25 mA GP1.4 7 22 GP0.1
VSS 8 21 GP0.0
• Open-drain interrupt output on input change CLK 9 20 VDD
• Interrupt port capture register TP 10 19 VSS
GP1.5 11 18 A2
• Internal Power-On Reset (POR) GP1.6 12 17 A1
GP1.7 13 16 A0
• Polarity inversion register to configure the polarity SCL 14 15 SDA
of the input port data

GP1.1
GP1.0

GP0.7
GP0.6
GP0.5
GP0.4
• Compatible with most microcontrollers QFN

Vss
• Available temperature range:
- Industrial (I): -40°C to +85°C
28 27 26 2524 23 22
GP1.2 1 21 GP0.3
CMOS Technology GP1.3 2 20 GP0.2
INT 3 19 GP0.1
• Operating Supply Voltage: 2.0V to 5.5V GP1.4 4 MCP23016 18 GP0.0
VSS 5 17 VDD
• Low standby current CLK 6 16 VSS
TP 7 15 A2
8 9 10 11 121314
Packages GP1.5
GP1.6
GP1.7
SCL

A0
A1
SDA
• 28-pin PDIP, 300 mil; 28-pin SOIC, 300 mil
• 28-pin SSOP, 209 mil; 28-pin QFN, 6x6 mm

Block Diagram

INT Interrupt Low Pass

Logic Filter
A0
A1
A2
IARES
Deserializer
Serializer/

I2C™ Bus Address

SCL Interface/ Decoder 16 Bits
SDA Protocol GP0.0 to GP0.7
Handler I/O
I2C™ Bus Port
Control
Control

CLKIN GP1.0 to GP1.7

Clock
TP Gen

Power-on Write pulse

VDD Reset
Read pulse
8-Bit Configuration
VSS Control
Registers

© 2007 Microchip Technology Inc. DS20090C-page 1

MCP23016
NOTES:

DS20090C-page 2 © 2007 Microchip Technology Inc.

 MCP23016
1.0 DEVICE OVERVIEW input or output register. The polarity of the read register
can be inverted with the polarity inversion register (see
The MCP23016 device provides 16-bit, general Section 1.7.3, “Input Polarity Registers”). All
purpose, parallel I/O expansion for I2C bus registers can be read by the system master.
applications.
The open-drain interrupt output is activated when any
This device includes high-current drive capability, low input state differs from its corresponding input port
supply current and individual I/O configuration. I/O register state. This is used to indicate to the system
expanders provide a simple solution when additional master that an input state has changed. The interrupt
I/Os are needed for ACPI, power switches, sensors, capture register captures port value at this time. The
push buttons, LEDs and so on. Power-on Reset sets the registers to their default val-
The MCP23016 consists of multiple 8-bit configuration ues and initializes the device state machine.
registers for input, output and polarity selection. The Three device inputs (A0 - A2) determine the I2C
system master can enable the I/Os as either inputs or address and allow up to eight I/O expander devices to
outputs by writing the I/O configuration bits. The data share the same I2C bus.
for each input or output is kept in the corresponding

1.1 Pin Descriptions

TABLE 1-1: PINOUT DESCRIPTION
PDIP,
SOIC, QFN I/O/P Buffer
Pin Name Description
SSOP Pin No. Type Type
Pin No.
CLK 9 6 I ST Clock source input
TP 10 7 O — Test Pin (This pin must be left floating)
GP1.0 2 27 I/O TTL D0 digital input/output for GP1
GP1.1 3 28 I/O TTL D1 digital input/output for GP1
GP1.2 4 1 I/O TTL D2 digital input/output for GP1
GP1.3 5 2 I/O TTL D3 digital input/output for GP1
GP1.4 7 4 I/O TTL D4 digital input/output for GP1
GP1.5 11 8 I/O ST D5 digital input/output for GP1
GP1.6 12 9 I/O ST D6 digital input/output for GP1
GP1.7 13 10 I/O ST D7 digital input/output for GP1
GP0.0 21 18 I/O TTL D0 digital input/output for GP0
GP0.1 22 19 I/O TTL D1 digital input/output for GP0
GP0.2 23 20 I/O TTL D2 digital input/output for GP0
GP0.3 24 21 I/O TTL D3 digital input/output for GP0
GP0.4 25 22 I/O TTL D4 digital input/output for GP0
GP0.5 26 23 I/O TTL D5 digital input/output for GP0
GP0.6 27 24 I/O TTL D6 digital input/output for GP0
GP0.7 28 25 I/O TTL D7 digital input/output for GP0
SCL 14 11 I ST Serial clock input
SDA 15 12 I/O ST Serial data I/O
INT 6 3 O OD Interrupt output
A0 16 13 I ST Address input 1
A1 17 14 I ST Address input 2
A2 18 15 I ST Address input 3
VSS 1, 8, 19 5, 16, 26 P — Ground reference for logic and I/O pins
VDD 20 17 P — Positive supply for logic and I/O pins

© 2007 Microchip Technology Inc. DS20090C-page 3

MCP23016
1.2 Power-on Reset (POR) A 1 MHz (typ.) internal clock is needed for the device to
function properly. The internal clock can be measured
The on-chip POR circuit holds the chip in RESET until on the TP pin. Recommended REXT and CEXT values
VDD has reached a high enough level to deactivate the are shown in Table 1-2.
POR circuit (i.e., release RESET). A maximum rise
time for VDD is specified in the electrical specifications. Note: Set IARES = 1 to measure the clock
output on TP.
When the device starts normal operation (exits the
RESET condition), device operating parameters TABLE 1-2: RECOMMENDED VALUES
(voltage, frequency, temperature) must be met to
ensure proper operation. REXT CEXT
3.9 kΩ 33 pF
1.3 Power-up Timer (PWRT)
1.5 I2C Bus Interface/ Protocol
The Power-up Timer provides a 72 ms nominal time-
out on power-up, keeping the device in RESET and Handler
allowing VDD to rise to an acceptable level. This block manages the functionality of the I2C bus
The power-up time delay will vary from chip-to-chip due interface and protocol handling. The MCP23016
to VDD, temperature and process variation. See supports the following commands:
Table 2-4 for details (TPWRT, parameter 3).
TABLE 1-3: COMMAND BYTE TO
1.4 Clock Generator REGISTER RELATIONSHIP
The MCP23016 uses an external RC circuit to Command Byte Result
determine the internal clock speed. The user must 0h Access to GP0
connect R and C to the MCP23016, as shown in
1h Access to GP1
Figure 1-1.
2h Access to OLAT0
FIGURE 1-1: CLOCK CONFIGURATION 3h Access to OLAT1
4h Access to IPOL0
VDD 5h Access to IPOL1
6h Access to IODIR0
REXT Internal Clock 7h Access to IODIR1
CLK
8h Access to INTCAP0 (Read-Only)
9h Access to INTCAP1 (Read-Only)
CEXT Ah Access to IOCON0
VSS MCP23016 Bh Access to IOCON1

1.6 Address Decoder

The last three LSb of the 7-bit address are user-defined
(see Table 1-4). Three hardware pins (<A2:A0>) define
these bits.

TABLE 1-4: DEVICE ADDRESS

0 1 0 0 A2 A1 A0

DS20090C-page 4 © 2007 Microchip Technology Inc.

 MCP23016
1.7 Register Block
The register block contains the Configuration and Port registers, as shown in Table 1-5.
TABLE 1-5: REGISTER SUMMARY
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR

Port Registers
GP0 GP0.7 GP0.6 GP0.5 GP0.4 GP0.3 GP0.2 GP0.1 GP0.0 0000 0000
GP1 GP1.7 GP1.6 GP1.5 GP1.4 GP1.3 GP1.2 GP1.1 GP0.0 0000 0000
OLAT0 OL0.7 OL0.6 OL0.5 OL0.4 OL0.3 OL0.2 OL0.1 OL0.0 0000 0000
OLAT1 OL1.7 OL1.6 OL1.5 OL1.4 OL1.3 OL1.2 OL1.1 OL1.0 0000 0000
Configuration Registers
IPOL0 IGP0.7 IGP0.6 IGP0.5 IGP0.4 IGP0.3 IGP0.2 IGP0.1 IGP0.0 0000 0000
IPOL1 IGP1.7 IGP1.6 IGP1.5 IGP1.4 IGP1.3 IGP1.2 IGP1.1 IGP1.0 0000 0000
IODIR0 IOD0.7 IOD0.6 IOD0.5 IOD0.4 IOD0.3 IOD0.2 IOD0.1 IOD0.0 1111 1111
IODIR1 IOD1.7 IOD1.6 IOD1.5 IOD1.4 IOD1.3 IOD1.2 IOD1.1 IOD1.0 1111 1111
INTCAP0 ICP0.7 ICP0.6 ICP0.5 ICP0.4 ICP0.3 ICP0.2 ICP0.1 ICP0.0 xxxx xxxx
INTCAP1 ICP1.7 ICP1.6 ICP1.5 ICP1.4 ICP1.3 ICP1.2 ICP1.1 ICP1.0 xxxx xxxx
IOCON0 — — — — — — — IARES ---- ---0
IOCON1 — — — — — — — IARES ---- ---0
Legend: ‘1’ bit is set, ‘0’ bit is cleared, x = unknown, — = unimplemented.

© 2007 Microchip Technology Inc. DS20090C-page 5

MCP23016
1.7.1 DATA PORT REGISTERS
Two registers provide access to the two GPIO ports:
• GP0 (provides access to data port GP0)
• GP1 (provides access to data port GP1)
A read from this register provides status on pins of
these ports. A write to these registers will modify the
output latch registers (OLAT0, OLAT1) and data output.

REGISTER 1-1: GP0 - GENERAL PURPOSE I/O PORT REGISTER 0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GP0.7 GP0.6 GP0.5 GP0.4 GP0.3 GP0.2 GP0.1 GP0.0
bit 7 bit 0

bit 7-0 GP0.0:GP0.7: Reflects the logic level on the pins.

1 = Logic ‘1’
0 = Logic ‘0’

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

REGISTER 1-2: GP1 - GENERAL PURPOSE I/O PORT REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GP1.7 GP1.6 GP1.5 GP1.4 GP1.3 GP1.2 GP1.1 GP1.0
bit 7 bit 0

bit 7-0 GP1.0:GP1.7: Reflects the logic level on the pins.

1 = Logic ‘1’
0 = Logic ‘0’

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS20090C-page 6 © 2007 Microchip Technology Inc.

 MCP23016
1.7.2 OUTPUT LATCH REGISTERS
Two registers provide access to the two port output
latches:
• OLAT0 (provides access to the output latch for
port GP0)
• OLAT1 (provides access to the output latch for
port GP1)
A read from these registers results in a read of the latch
that controls the output and not the actual port. A write
to these registers updates the output latch that controls
the output.

REGISTER 1-3: OLAT0 - OUTPUT LATCH REGISTER 0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OL0.7 OL0.6 OL0.5 OL0.4 OL0.3 OL0.2 OL0.1 OL0.0
bit 7 bit 0

bit 7-0 OL0.0:O0.7: Reflects the logic level on the output latch.
1 = Logic ‘1’
0 = Logic ‘0’

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

REGISTER 1-4: OLAT1 - OUTPUT LATCH REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OL1.7 OL1.6 OL1.5 OL1.4 OL1.3 OL1.2 OL1.1 OL1.0
bit 7 bit 0

bit 7-0 OL1.0:O1.7: Reflects the logic level on the output latch.
1 = Logic ‘1’
0 = Logic ‘0’

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

© 2007 Microchip Technology Inc. DS20090C-page 7

MCP23016
1.7.3 INPUT POLARITY REGISTERS
These registers allow the user to configure the polarity
of the input port data (GP0 and GP1). If a bit in this reg-
ister is set, the corresponding input port (GPn) data bit
polarity will be inverted.
• IPOL0 (controls the polarity of GP0)
• IPOL1 (controls the polarity of GP1)

REGISTER 1-5: IPOL0 - INPUT POLARITY PORT REGISTER 0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IGP0.7 IGP0.6 IGP0.5 IGP0.4 IGP0.3 IGP0.2 IGP0.1 IGP0.0
bit 7 bit 0

bit 7-0 IGP0.0:IGP0.7: Controls the polarity inversion for the input pins
1 = Corresponding GP0 bit is inverted
0 = Corresponding GP0 bit is not inverted

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

REGISTER 1-6: IPOL1 - INPUT POLARITY PORT REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IGP1.7 IGP1.6 IGP1.6 IGP1.4 IGP1.3 IGP1.2 IGP1.1 IGP1.0
bit 7 bit 0

bit 7-0 IGP1.0:IGP1.7: Controls the polarity inversion for the input pins
1 = Corresponding GP1 bit is inverted
0 = Corresponding GP1 bit is not inverted

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS20090C-page 8 © 2007 Microchip Technology Inc.

 MCP23016
1.7.4 I/O DIRECTION REGISTERS
Two registers control the direction of data I/O:
• IODIR0 (controls GP0)
• IODIR1 (controls GP1)
When a bit in these registers is set, the corresponding
pin becomes an input. Otherwise, it becomes an
output. At Power-on Reset, the device ports are
configured as inputs.

REGISTER 1-7: IODIR0 - I/O DIRECTION REGISTER 0

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IOD0.7 IOD0.6 IOD0.5 IOD0.4 IOD0.3 IOD0.2 IOD0.1 IOD0.0
bit 7 bit 0

bit 7-0 IOD0.0:IO0.7: Controls the direction of data I/O

1 = Input
0 = Output

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

REGISTER 1-8: IODIR1 - I/O DIRECTION REGISTER 1

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IOD1.7 IOD1.6 IOD1.5 IOD1.4 IOD1.3 IOD1.2 IOD1.1 IOD1.0
bit 7 bit 0

bit 7-0 IOD1.0:IO1.7: Controls the direction of data I/O

1 = Input
0 = Output

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

© 2007 Microchip Technology Inc. DS20090C-page 9

MCP23016
1.7.5 INTERRUPT CAPTURE REGISTERS
Two registers contain the value of the port that
generated the interrupt:
• INTCAP0 contains the value of GP0 at time of
GP0 change interrupt
• INTCAP1 contains the value of GP1 at time of
GP1 change interrupt
These registers are ‘read-only’ registers (A write to
these registers is ignored).

REGISTER 1-9: INTCAP0 - INTERRUPT CAPTURED VALUE FOR PORT REGISTER 0

R-x R-x R-x R-x R-x R-x R-x R-x
ICP0.7 ICP0.6 ICP0.5 ICP0.4 ICP0.3 ICP0.2 ICP0.1 ICP0.0
bit 7 bit 0

bit 7-0 ICP0.0:ICP0.7: Reflects the logic level on the GP0 pins at the time of interrupt due to pin
change
1 = Logic ‘1’
0 = Logic ‘0’

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

REGISTER 1-10: INTCAP1 - INTERRUPT CAPTURED VALUE FOR PORT REGISTER 1

R-x R-x R-x R-x R-x R-x R-x R-x
ICP1.7 ICP1.6 ICP1.5 ICP1.4 ICP1.3 ICP1.2 ICP1.1 ICP1.0
bit 7 bit 0

bit 7-0 ICP1.0:ICP1.7: Reflects the logic level on the GP1 pins at the time of interrupt due to pin
change
1 = Logic ‘1’
0 = Logic ‘0’

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS20090C-page 10 © 2007 Microchip Technology Inc.

 MCP23016
1.7.6 I/O EXPANDER CONTROL
REGISTER
• IOCON0 controls the functionality of the
MCP23016.
The IARES (Interrupt Activity Resolution) bit controls
the sampling frequency of the GP port pins. The higher
the sampling frequency, the higher the device current
requirements. If this bit is ‘0’ (default), the maximum
time to detect the activity on the port is 32 ms (max.),
which results in lower standby current. If this bit is ‘1’,
the maximum time to detect activity on the port is
200 µsec. (max.) and results in higher standby current.

REGISTER 1-11: IOCON0 - I/0 EXPANDER CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — IARES
bit 7 bit 0

bit 1-7 Unimplemented bit: Read as ‘0’

bit 0 IARES: Interrupt Activity Resolution

1 = Fast sample rate
0 = Normal sample rate

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

IOCON1 is a shadow register for IOCON0. Access to IOCON1 results in access to IOCON0.

© 2007 Microchip Technology Inc. DS20090C-page 11

MCP23016
1.8 Serializer/Deserializer 1.9.1 INTERRUPT EVENT DETECTION
The Serializer/Deserializer block converts and The IARES bit controls the resolution for detecting an
transfers data between the I2C bus and GPIO. interrupt-on-change event. If this bit is ‘0’ (default), the
maximum time for detecting a change of event is high,
which results in lower standby current. If this bit is ‘1’, it
1.9 Interrupt Logic
takes less time for scanning the activity on the port and
The MCP23016 asserts the open-drain interrupt output results in higher standby current.
(INT) low when one of the port pins changes state. Only
those pins that are configured as an input can cause an FIGURE 1-2: READING PORTX AFTER
interrupt. Pins defined as an output have no effect on INTERRUPT EVENT
INT. The interrupt will remain active until a read from
either the port (GPn) on which the interrupt occurred or
the INTCAPn register is performed. If the input returns
to its previous state before a read operation, it will reset GPx PORT X PORT X
the interrupt and the INT pin output will tri-state. Each
8-bit port is read separately, so reading GP0 or
INTCAP0 will not clear the interrupt generated by GP1
or INTCAP1, and vice versa.
INT
Input change activity on each port will generate an
interrupt and the value of the particular port will be
captured and copied into INTCAP0/INTCAP1. The
INTCAPn registers are only updated when an interrupt
occurs on INT. These values will stay unchanged until Port value Port value
is captured Read GPx is captured
the user clears the interrupt by reading the port or the
and written to or INTCAPn and written to
INTCAPn register. INTCAPn INTCAPn
If the input port value changes back to normal before a
user-read, the INT output will be reset. However, the
INTCAP0/INTCAP1 will still contain the value of the
port at the interrupt change. If the port value changes
again, it will re-activate the interrupt and the new value
will be captured.
The first interrupt on change event following an
interrupt RESET will result in a capture event. Any fur-
ther change event that occurs before the interrupt is
reset will not result in a capture event.

DS20090C-page 12 © 2007 Microchip Technology Inc.

 MCP23016
1.9.2 WRITING THE REGISTERS FIGURE 1-3: WRITE TO CONFIGURATION
2
To write to a MCP23016 register, the Master I C device REGISTERS (CASE 1)
needs to follow the requirements, as illustrated in

P
Figure 1-3. First, the device is selected by sending the
slave address and setting the R/W bit to logic ‘0’. The

D7 D6 D5 D4 D3 D2 D1 D0 ACK
command byte is sent after the address and

9
determines which register will be written. Table 1-3

8
shows the relationship of the command byte and

7
register.

6
The MCP23016 has twelve 8-bit registers. They are
configured to operate as six 16-bit register pairs,

Data 2

5
supporting the device’s 16-bit port. These pairs are

4
formed based on their functions (e.g., GP0 and GP1
are grouped together). The I2C commands apply to one

3
register pair to provide faster access. The first data byte

2
following a command byte is written into the register

1
pointed to by the command byte, while the second data

ACK
is written into another register in the same pair. For

9
example, if the first byte is sent to OLAT1 (command

D7 D6 D5 D4 D3 D2 D1 D0
byte 03h), the next data byte will be written into the sec-

8
ond register of that pair, OLAT0. If the first byte is writ-

7
ten to OLAT0 (command byte 02h), the second byte

6
will be written to OLAT1.

5
There is no limitation on the number of data bytes in

Data 1
one write transmission. Figure 1-4 shows the case of

4
multiple byte writes in one write operation. In this case,

3
the multiple writes are made to the same data pair.

SCL held low until

data is processed
Note: The bus must remain free until after the

1
ninth clock pulse for a minimum of 12 µs
(see Table 2-5 and Figure 2-4). ACK

9
D7 D6 D5 D4 D3 D2 D1 D0

8
7
6
Command Byte

5
4
3
2
1
ACK

9
R/W=0

8
A2 A1 A0

7
6
5
4
Address

0
0

3
2
1

1
0

© 2007 Microchip Technology Inc. DS20090C-page 13

 R/W=0
Address Command Byte Data 1 Data 2

0 1 0 0 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

FIGURE 1-4:

DS20090C-page 14
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SCL held low until

data is processed
MCP23016

Data 1 Data 2

D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
REGISTERS (CASE 2)

SCL held low until

data is processed
WRITE TO CONFIGURATION

Address Command Byte Data 1 Data 2

R/W=0
SDA 0 1 0 0 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
FIGURE 1-5:

SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

SCL held low until

data is processed

Data on GP0
DATA VALID

t GPV0

Data on GP1 VALID

DATA

t GPV1
WRITE TO OUTPUT PORTS

© 2007 Microchip Technology Inc.

 MCP23016
1.9.3 READING THE REGISTERS FIGURE 1-6: READ FROM
To read a MCP23016 register, the Master needs to CONFIGURATION
follow the requirements shown in Figure 1-6. First, the REGISTER
device is selected by sending the slave address and
setting the R/W bit to logic ‘0’. The command byte is

P
sent after the address and determines which register
will be read. A restart condition is generated and the
device address is sent again with the R/W bit set to

D7 D6 D5 D4 D3 D2 D1 D0 ACK

9
logic ‘1’. The data register defined by the command
byte will be sent first, followed by the other register in

8
the register pair. The logic for register selection is the
same as explained in Write mode (Section 1.9.2,

7
Data from MSB or
“Writing the Registers”).

LSB of register

6
The falling edge of the ninth clock initiates the register
read action. The SCL clock will be held low while the

5
data is read from the register and is transferred to the

4
I2C bus control block by the Serializer/Deserializer
block.

3
The MCP23016 holds the clock low after the falling

2
edge of the ninth clock pulse. The configuration
registers (or port control registers) are read and the

1
value is stored. Finally, the clock is released to enable
the next transmission.

ACK

ACK
There is no limitation on the number of data bytes in

9
9

SCL held low until

data is processed
one read transmission. Figure 1-8 shows the case of
D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

8
8
multiple byte read in one read operation. In this case,
the multiple writes are made to the same data pair.

7
Data from LSB or
SCL held low until
data is processed

MSB of register
Note: The bus must remain free until after the

6
6
Command Byte

ninth clock pulse for a minimum of 12 µs

(see Table 2-5 and Figure 2-4).

5
5

4
4
3

3
2
2

1
1

ACK
ACK

9
R/W=0
R/W=0

8
A0
A0

7
A1
A1

6
A2
A2

5
4

4
0
0

Address
Address

3
0
0

2
1
1

1
0
0

SCL S

S
SDA

© 2007 Microchip Technology Inc. DS20090C-page 15

 Data from LSB or Data from MSB or
Address MSB of register LSB of register
R/W=0
SDA 0 1 0 0 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
FIGURE 1-7:

DS20090C-page 16
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
MCP23016

SCL held low until

data is processed

Data in GP0

Read signal (Internal) for GP0

tRDd0
READ FROM INPUT PORTS (CASE 1)

Data in GP1

Read signal (Internal) for GP1

tRDd1

INT
tIsd tIcd0 tIcd1

Note: It is assumed that command byte is already set to ‘00’.

© 2007 Microchip Technology Inc.

 Address Data from GP0 Data from GP1
R/W=0
SDA 0 1 0 0 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
FIGURE 1-8:

SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

© 2007 Microchip Technology Inc.

Data from GP0 Data from GP1
(CASE 2)

D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

Note: It is assumed that command byte is already set to 00.

READ FROM INPUT PORTS

DS20090C-page 17
MCP23016
MCP23016
NOTES:

DS20090C-page 18 © 2007 Microchip Technology Inc.

 MCP23016
2.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias................................................................................................................ -55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS ......................................................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +6.5V
Total power dissipation (Note 1) ............................................................................................................................ 1.0 W
Maximum current out of VSS pin .......................................................................................................................... 300 mA
Maximum current into VDD pin ............................................................................................................................. 250 mA
Input clamp current, IIK (VI < 0, or VI > VDD) ....................................................................................................... ± 20 mA
Output clamp current, IOK (VO < 0, or VO > VDD) ................................................................................................ ± 20 mA
Maximum output current sunk by any I/O pin......................................................................................................... 25 mA
Maximum output current sourced by any I/O pin ................................................................................................... 25 mA
Maximum current sunk by combined PORTS ...................................................................................................... 200 mA
Maximum current sourced by combined PORTS ................................................................................................ 200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

© 2007 Microchip Technology Inc. DS20090C-page 19

MCP23016
2.1 DC Characteristics
TABLE 2-1: DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for industrial
Param Characteristic Sym Min Typ† Max Units Conditions
No.
D001 Supply Voltage VDD 2.0 — 5.5 V
D002 Standby Current IDD — 0.4 mA IARES = 1
D003 Standby Current IPD — 25 µA IARES = 0
Input Low Voltage
I/O ports VIL
D004 TTL buffer Vss — 0.15 VDD V For entire VDD range
D004A Vss — 0.8V 4.5V ≤ VDD ≤ 5.5V
D005 Schmitt Trigger buffer Vss — 0.2 VDD V
Input High Voltage
I/O ports VIH —
D006 TTL buffer 2.0 — VDD V 4.5V ≤ VDD ≤ 5.5V
D006A 0.25VDD — VDD V For entire VDD range
+ 0.8V
D007 Schmitt Trigger buffer 0.8 VDD — VDD V For entire VDD range
Input Leakage Current
D008 I/O ports IIL — — ±1.0 µA Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D009 CLK — — ±5.0 µA Vss ≤ VPIN ≤ VDD
Output Low Voltage
D010 I/O Ports VOL — — 0.6 V IOL = 8.5 mA, VDD = 4.5V
Output High Voltage
D010 I/O Ports VOH VDD-0.7 — — V IOH = 3.0 mA, VDD = 4.5V
D011 VDD start voltage to ensure VPOR — Vss — V
internal POR signal
D012 VDD rise rate to ensure SVDD 0.05 - — V/ms Note 1
internal POR signal
DC Trip Point VTPOR 1.5 1.7 1.9 V DC Slow Ramp
D012 VDD rise rate to ensure SVDD 0.05 — — V/ms Note 1
internal POR signal with
PWRT enabled
DC Current Draw IPOR — 5.0 — µA At 5.0V (1 µ/Volt typical)
Note 1: These parameters are characterized but not tested.
2: Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
3: Standby current is measured with all I/O in hi-impedance state and tied to VDD and VSS.
4: For RC CLK, current through REXT is not included. The current through the resistor can be estimated by
the formula
Ir = VDD/2 REXT (mA) with REXT in kohm.
5: Negative current is defined as coming out of the pin.

DS20090C-page 20 © 2007 Microchip Technology Inc.

 MCP23016
FIGURE 2-1: RESPONSE TIME

VDD

TABLE 2-2: RESPONSE TIME

Parameter
Symbol Characteristic Min Typ† Max Units Conditions
No.
1 Response Time 100 — — ns Minimum time where a VDD
transition from 5.0V to 0.0V to
5.0V will cause a RESET. All
times less than 100 ns will be
filtered.

FIGURE 2-2: TEST POINT CLOCK TIMING

TTP

TABLE 2-3: TEST POINT CLOCK TIMING

Parameter
Symbol Characteristic Min Typ† Max Units Conditions
No.
FTP TP pin Frequency — 1.0 — MHz Measured at TP pin,
IARES = ‘1’.
2 TTP TP pin CLK Period — 1.0 — µs Measured at TP pin,
IARES = ‘1’.
† Data in "Typ" column is at 5V, +25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.

TABLE 2-4: POWER-UP TIMER REQUIREMENTS

Parameter
Symbol Characteristic Min Typ† Max Units Conditions
No.
3 TPWRT Power-up Timer Period — 72 — ms
† Data in "Typ" column is at 5V, +25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.

© 2007 Microchip Technology Inc. DS20090C-page 21

MCP23016
FIGURE 2-3: I2C BUS START/STOP BITS TIMING

SCL
91 93
90 92

SDA

START STOP
Condition Condition

TABLE 2-5: I2C BUS START/STOP BITS REQUIREMENTS

Param Ty
Symbol Characteristic Min Max Units Conditions
No. p
90 TSU:STA START condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Setup time 400 kHz mode 600 — — START condition (Note 1)
91 THD:STA START condition 100 kHz mode 4000 — — ns After this period, the first
Hold time 400 kHz mode 600 — — clock pulse is generated
(Note 1)
92 TSU:STO STOP condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 THD:STO STOP condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
Note 1: These parameters are characterized but not tested.

DS20090C-page 22 © 2007 Microchip Technology Inc.

 MCP23016
FIGURE 2-4: I2C BUS DATA TIMING

103 100 102

101
SCL
90
106 107
111
91 92
SDA
In
110
109 109

SDA
Out

© 2007 Microchip Technology Inc. DS20090C-page 23

MCP23016
TABLE 2-5: I2C BUS DATA REQUIREMENTS
Param
Symbol Characteristic Min Max Units Conditions
No.
100 THIGH Clock High Time 100 kHz mode 4.0 — µs (Note 1)
400 kHz mode 0.6 — µs
101 TLOW Clock Low Time 100 kHz mode 4.7 — µs (Note 1)
400 kHz mode 1.3 — µs
102 TR SDA and SCL Rise 100 kHz mode — 1000 ns (Note 1)
Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from
10 - 400 pF
103 TF SDA and SCL Fall 100 kHz mode — 300 ns (Note 1)
Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from
10 - 400 pF
90 TSU:STA START Condition 100 kHz mode 4.7 — µs Only relevant for repeated
Setup Time 400 kHz mode 0.6 — µs START condition (Note 1)
91 THD:STA START Condition 100 kHz mode 4.0 — µs After this period, the first
Hold Time 400 kHz mode 0.6 — µs clock pulse is generated
(Note 1)
106 THD:DAT Data Input Hold 100 kHz mode 0 — ns (Note 1)
Time 400 kHz mode 0 0.9 µs
107 TSU:DAT Data Input Setup 100 kHz mode 250 — ns (Note 1) (Note 3)
Time 400 kHz mode 100 — ns
92 TSU:STO STOP Condition 100 kHz mode 4.7 — µs (Note 1)
Setup Time 400 kHz mode 0.6 — µs
109 TAA Output Valid from 100 kHz mode — 3500 ns (Note 1) (Note 2)
Clock 400 kHz mode — — ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — µs Time the bus must be free
400 kHz mode 1.3 — µs before a new transmis-
sion can start (Note 1)
CB Bus Capacitive Loading — 400 pF
111 TWAIT Clock wait time 100 kHz mode 12 µs — µs Time the bus must remain
after ninth pulse 400 kHz mode 12 µs — µs free after the ninth clock
pulse before a new
transmission can start.
Note 1: These parameters are characterized but not tested.
2: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line TR max.+TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.

DS20090C-page 24 © 2007 Microchip Technology Inc.

 MCP23016
TABLE 2-7: GP0 AND GP1 TIMING REQUIREMENTS
Param
Symbol Characteristic Min Typ. Max Units Conditions
No.
tGPV0 GP0 output data — 40 — µs TP = 1 MHz
valid time
tGPV1 GP1 output data — 50 — µs
valid time
tRDd0 GP0 data read — 40 — µs
delay time
tRDd1 GP1 data read — 50 — µs
delay time
tISD0 GP0 Interrupt set — — 200 µs IARES = 1, TP = 1 MHz
delay time — — 32 ms IARES = 0, TP = 1 MHz
tISD1 GP1 Interrupt set — — 200 µs IARES = 1, TP = 1 MHz
delay time — — 32 ms IARES = 0, TP = 1 MHz
tLCD0 GP0 Interrupt clear — 100 — µs TP = 1 MHz
delay time (for
read)
tLCD1 GP1 Interrupt clear — 100 — µs
delay time (for
read)
Note 1: These parameters are characterized but not tested.

© 2007 Microchip Technology Inc. DS20090C-page 25

 Data from LSB or Data from MSB or
Address MSB of register LSB of register
R/W=0
SDA 0 1 0 0 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
ACK
FIGURE 2-5:

DS20090C-page 26
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
MCP23016

SCL held low until

data is processed

Data in GP0

Read signal(Internal) for GP0

GP0 AND GP1 PORT TIMINGS

tRDd0

Data in GP1

Read signal(Internal) for GP1

tRDd1

INT
tIsd tIcd0 tIcd1

Note: It is assumed that command byte is already set to ‘00’.

© 2007 Microchip Technology Inc.

 MCP23016
3.0 PACKAGE INFORMATION

3.1 Package Marking Information

28-Lead PDIP (Skinny DIP) Example:

XXXXXXXXXXXXXXXXX MCP23016-I/SP e3
XXXXXXXXXXXXXXXXX
YYWWNNN 0717017

28-Lead SOIC Example:

XXXXXXXXXXXXXXXXX MCP23016-I/SO e3
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN 0710017

28-Lead SSOP Example:

XXXXXXXXXXXX MCP23016
XXXXXXXXXXXX -I/SS e3
YYWWNNN 0720017

28-Lead QFN Example:

XXXXXXXX MCP23016
XXXXXXXX -I/ML e3
YYWWNNN 0710017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )
e3 can be found on the outer packaging for this package.
e3

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

© 2007 Microchip Technology Inc. DS20090C-page 27

MCP23016
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

NOTE 1
E1

1 2 3

A A2

L c

A1 b1
b e eB

Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 28
Pitch e .100 BSC
Top to Seating Plane A – – .200
Molded Package Thickness A2 .120 .135 .150
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .335
Molded Package Width E1 .240 .285 .295
Overall Length D 1.345 1.365 1.400
Tip to Seating Plane L .110 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .050 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.

DS20090C-page 28 © 2007 Microchip Technology Inc.

 MCP23016
28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D
N

E
E1

NOTE 1

1 2 3
e
b

h
α
h

φ c
A A2

L
A1 L1 β

Units MILLMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 28
Pitch e 1.27 BSC
Overall Height A – – 2.65
Molded Package Thickness A2 2.05 – –
Standoff § A1 0.10 – 0.30
Overall Width E 10.30 BSC
Molded Package Width E1 7.50 BSC
Overall Length D 17.90 BSC
Chamfer (optional) h 0.25 – 0.75
Foot Length L 0.40 – 1.27
Footprint L1 1.40 REF
Foot Angle Top φ 0° – 8°
Lead Thickness c 0.18 – 0.33
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α 5° – 15°
Mold Draft Angle Bottom β 5° – 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B

© 2007 Microchip Technology Inc. DS20090C-page 29

MCP23016
28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D
N

E
E1

1 2
b
NOTE 1
e

c
A A2

φ
A1
L1 L

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 28
Pitch e 0.65 BSC
Overall Height A – – 2.00
Molded Package Thickness A2 1.65 1.75 1.85
Standoff A1 0.05 – –
Overall Width E 7.40 7.80 8.20
Molded Package Width E1 5.00 5.30 5.60
Overall Length D 9.90 10.20 10.50
Foot Length L 0.55 0.75 0.95
Footprint L1 1.25 REF
Lead Thickness c 0.09 – 0.25
Foot Angle φ 0° 4° 8°
Lead Width b 0.22 – 0.38
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-073B

DS20090C-page 30 © 2007 Microchip Technology Inc.

 MCP23016
28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]
with 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D D2
EXPOSED
PAD

E
b
E2

2 2
1 1 K

N N
NOTE 1 L
TOP VIEW BOTTOM VIEW

A3 A1

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 28
Pitch e 0.65 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Overall Width E 6.00 BSC
Exposed Pad Width E2 3.65 3.70 4.20
Overall Length D 6.00 BSC
Exposed Pad Length D2 3.65 3.70 4.20
Contact Width b 0.23 0.30 0.35
Contact Length L 0.50 0.55 0.70
Contact-to-Exposed Pad K 0.20 – –
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-105B

© 2007 Microchip Technology Inc. DS20090C-page 31

MCP23016
NOTES:

DS20090C-page 32 © 2007 Microchip Technology Inc.

 MCP23016
APPENDIX A: REVISION HISTORY

Revision A (December 2002)

Original data sheet for MCP23016 device.

Revision B (September 2003)

1. Addition of Output Low Voltage section to
Table 2-1 in Electrical Characteristics.
2. Addition of Output High Voltage section to
Table 2-1 in Electrical Characteristics.

Revision C (January 2007)

This revision includes updates to the packaging
diagrams.

© 2007 Microchip Technology Inc. DS20090C-page 33

MCP23016
NOTES:

DS20090C-page 34 © 2007 Microchip Technology Inc.

 MCP23016
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office.
PART NO. X /XX Examples:
a) DSTEMP-I/P: Industrial Temperature,
Device Temperature Package
PDIP package.
Range
a) DSTEMP-I/SO: Industrial Temperature,
SOIC package.
Device: DSTEMP: 16-Bit I2C I/O Expander a) DSTEMP-I/SS: Industrial Temperature,
SOIC package.
a) DSTEMP-I/ML: Industrial Temperature,
Temperature I = -40°C to +85°C QFN package.
Range:

Package: SP = Plastic DIP (300 mil Body), 28-lead

SO = Plastic SOIC, Wide (300 mil Body), 28-lead
SS = Plastic SOIC, (209 mil, 5.30mm), 28-lead
ML = Plastic Quad, Flat No Leads (QFN), 28-lead

© 2007 Microchip Technology Inc. DS20090C-page 35

MCP23016
NOTES:

DS20090C-page 36 © 2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
MICROCHIP MAKES NO REPRESENTATIONS OR
registered trademarks of Microchip Technology Incorporated
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
hold harmless Microchip from any and all damages, claims, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
suits, or expenses resulting from such use. No licenses are Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
conveyed, implicitly or otherwise, under any Microchip PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
intellectual property rights. PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

© 2007 Microchip Technology Inc. DS20090C-page 37

 WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-4182-8400 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-4182-8422 Fax: 43-7242-2244-393
Tel: 480-792-7200 Habour City, Kowloon Denmark - Copenhagen
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Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://support.microchip.com Fax: 852-2401-3431
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Web Address:
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www.microchip.com
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Westborough, MA Tel: 82-54-473-4301
Tel: 86-28-8665-5511 Fax: 39-0331-466781
Tel: 774-760-0087 Fax: 82-54-473-4302
Fax: 86-28-8665-7889 Netherlands - Drunen
Fax: 774-760-0088 Korea - Seoul
China - Fuzhou Tel: 82-2-554-7200 Tel: 31-416-690399
Chicago
Tel: 86-591-8750-3506 Fax: 82-2-558-5932 or Fax: 31-416-690340
Itasca, IL
Tel: 630-285-0071 Fax: 86-591-8750-3521 82-2-558-5934 Spain - Madrid
Fax: 630-285-0075 China - Hong Kong SAR Tel: 34-91-708-08-90
Malaysia - Penang
Tel: 852-2401-1200 Tel: 60-4-646-8870 Fax: 34-91-708-08-91
Dallas
Addison, TX Fax: 852-2401-3431 Fax: 60-4-646-5086 UK - Wokingham
Tel: 972-818-7423 China - Qingdao Tel: 44-118-921-5869
Philippines - Manila
Fax: 972-818-2924 Tel: 86-532-8502-7355 Fax: 44-118-921-5820
Tel: 63-2-634-9065
Detroit Fax: 86-532-8502-7205 Fax: 63-2-634-9069
Farmington Hills, MI China - Shanghai Singapore
Tel: 248-538-2250 Tel: 86-21-5407-5533 Tel: 65-6334-8870
Fax: 248-538-2260 Fax: 86-21-5407-5066 Fax: 65-6334-8850
Kokomo China - Shenyang Taiwan - Hsin Chu
Kokomo, IN Tel: 86-24-2334-2829 Tel: 886-3-572-9526
Tel: 765-864-8360 Fax: 86-24-2334-2393 Fax: 886-3-572-6459
Fax: 765-864-8387
China - Shenzhen Taiwan - Kaohsiung
Los Angeles Tel: 86-755-8203-2660 Tel: 886-7-536-4818
Mission Viejo, CA Fax: 86-755-8203-1760 Fax: 886-7-536-4803
Tel: 949-462-9523
China - Shunde Taiwan - Taipei
Fax: 949-462-9608
Tel: 86-757-2839-5507 Tel: 886-2-2500-6610
Santa Clara Fax: 86-757-2839-5571 Fax: 886-2-2508-0102
Santa Clara, CA
China - Wuhan Thailand - Bangkok
Tel: 408-961-6444
Tel: 86-27-5980-5300 Tel: 66-2-694-1351
Fax: 408-961-6445
Fax: 86-27-5980-5118 Fax: 66-2-694-1350
Toronto
China - Xian
Mississauga, Ontario,
Tel: 86-29-8833-7250
Canada
Fax: 86-29-8833-7256
Tel: 905-673-0699
Fax: 905-673-6509

12/08/06

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