1

EC/EE/IN Hinglish
Work Book - 05
Subject : Analog Electronics
Topic : Op-Amp
1. The LED in the following circuit will be ON if vi is 4. In the given circuit if v1 = (2 + 0.1 sin 2000πt) V and
v2 = 2.1 V, output vo is
+
v1 10 k 10 k
10 k
+10 V – 470  –
vi 100 k
10 k +
–
Op-Amp are ideals 4 k vo
+
(a) > 10 V (b) < 10 V
100 k
(c) > 5 V (d) < 5 V –
v2 + 10 k 10 k

2. In following circuit output is given as (a) (5.1 + 5.1 sin 2000πt) V

(b) (209.1 + 5.1 sin 2000πt) V
v0 = 10v1 – 4v2 + 5v3 + 2v4
(c) (5.1 – 5.1 sin 2000πt) V
R1 = 20 k RF (d) (209.1 – 2.1 sin 2000πt) V
v1
R2
v2 –
vo 5. Consider an op-amp circuit and input to the circuit as
v3 +
R3 = 80 k shown in figure. Initially voltage across capacitor is
v4 R5 = 50 k
R1 zero.
0.1 F vin

The resistance R2 R4 and RF respectively are 10 k

1
– 3 4
(a) 50 kΩ, 200 kΩ, 500 kΩ vo
+ 1 2
vin + t(ms)
(b) 50 kΩ, 100 kΩ, 80 kΩ – –1
(c) 50 kΩ, 200 kΩ, 200 kΩ
The output waveform will be
(d) 50 kΩ, 80 kΩ, 100 kΩ vo

1 2 3 4
(a) t(ms)
3. Input impedance of an instrumentation amplifier
–1
compared with a difference amplifier is
vo
(a) High
(b) 1 2 3 4
t(ms)
(b) Low
–1
(c) Same
vo
(d) Cannot not be determined 1
(c)
t(ms)
1 2 3 4

vo
1
(d) t(ms)
1 2 3 4
 2

6. In the following circuit the voltage vd is (1 + 2 sinωt) 9. In the following op-amp circuit, the load current iL is
mV and va = –10 mV. The output voltage vo is R1
20 k R1
20 k vi
2 k
vi1 – 1 k R2
–
+ vo iL R2
vi2 RL
+
1 k
vi vi
(a) –0.4(1 + sinωt) mV (a)  (b)
(b) 0.4(1 + sinωt) mV R2 R2
(c) –0.4(1 + 2sinωt) mV vi vi
(c)  (d)
(d) 0.4(1 + 2sinωt) mV RL RL

7. In following circuit output vo(t) is 10. Consider the following circuit and input voltage to it.
vs
– 10 k 5
8 mF vo
+ D2

50  vs
2 k D1
T T 3T
t
vo
5u( t) mA 250  1 k 2 2
4.7 k
–5
If op-amp and diodes are ideal, the output voltage
t t waveform is
(a) 10
e u (t ) V (b) e u (t ) V
10 vo T 3T
t t 2 T 2
  t
(c) 10
e u (t ) V (d) e u (t ) V
10
(a)

–25
8. The circuit shown below is at steady state before the
switch opens at t = 0. The vc(t) for t > 0 is vo T 3T
t=0 2 T 2
t
(b)
20 k –25
20 k vo
– 20 k
25
+ +
4 F vC (c)
5V +
– – T T 3T
t
2 2
vo
(a) 10 – 5e–12.5t V
25
(b) 5 – 5e–12.5t V
1 (d)

(c) 10  5e 12.5 V
t
1 T T 3T
 2 2
(d) 10  5e 12.5 V
 3

11. If M1 is operating in saturation, the circuit shown 15. The analog multiplier X shown below has the
below acts as a characteristics vP = v1v2. The output of this circuit is
vss
R1 M1 R
X
vo R
vs
vo
vin +
–

(a) Logarithm amplifier (a) vs vss (b) –vs vss

(b) Precision rectifier v vs
(c)  s (d)
(c) Square root amplifier vss vss
(d) Voltage follower
12. Three ideal amplifiers having voltage gain of 16. Consider the circuit shown below.
A1, A2, and A3 connected in cascade. Then over- R
all voltage gain is + 12 V
R + 12 V
(a) A1 A2 A3 (b) A1 + A2 + A3
Vi
(c) A1 = A2 – V3 (d) None of these Vo
R – 12 V
R – 12 V
13. In the given circuit both transistors Q1 and Q2 are R R
identical. The output voltage at T = 300 K is
Vo

+12 V
40 k (a) –6 V (b)
vi v2 +6 V
Vi
R1 R2
–12 V

333 k Vo
Vo
20 k +12 V
+12 V

vo (c) (d) Vi
–6 V +6 V
Vi –6 V +6 V
20 k
333 k –12 V –12 V

17. The following circuit has R = 10 kΩ, C = 10 μF. The

v R  v R 
(a) 2log10  2 1  (b) log10  2 1  input voltage is a sinusoidal at 50 Hz with an rms
 v1 R2   v1 R2  value of 10 V. Under ideal conditions, the current Is
v R  v R  from the source is
(c) 2.303log10  2 1  (d) 4.605log10  2 1 
 v1 R2   v1 R2  (a) 10π mA leading by 90°
(b) 20π mA leading by 90°
14. A low-pas filter with a cut-off frequency of 30 Hz is (c) 10π mA lagging by 90°
cascaded with a high pass filter with a cut-off (d) 10π mA lagging by 90°
frequency of 20 Hz. The resultant system of filters
will function as
(a) an all – pass filter
(b) an all – stop filter
(c) an band stop (band-reject) filter
(d) a band – pass filter
 4

18. An ideal op-amp circuit and its input wave form are Common Data For Q.19 and Q20.
shown in the figures. The output waveform of this A general filter circuit is shown in the figure:
circuit will be R2
Vin
R1
3 vA C
2
vo
1
t4 t 5 t6
R3 R4
t
0 t1 t2 t3
–1
–2 19. If R1 = R2 = RA and R3 = R4 = RB, the circuit acts as
–3 a (an)
+6 V (a) all pass filter
1 k (b) band pass filter
Vin
Vo (c) high pass filter
2 k (d) low pass filter
–3 V
1 k
20. The output of the shown filter is given to the circuit
below. The gain versus frequency characteristics of
Vs the output (v0) will be
6 RA/2

(a)
vm C vo
t3 t4
t
–3 Gain Gain

Vs (a) (b)
6  
Gain Gain
(b) (c) (d)
t3 t4  
t
–3 21. The block diagrams of two half wave rectifiers are
Vo shown in the figure. The transfer characteristics of
the rectifiers are also shown within the block.
6 P
Vo Q
Vo
Vin 0
(c) Vo
Vin Vo
0 t2 t4 t5 t 0 Vin

–3 It is desired to make full wave rectifier using above

two half-wave rectifiers. The resultants circuit will
Vo be
R
6
(a) Vin R
(d) P
R Vo
0 Q
t2 t4 t5 t
–3
 5

R
R (a)
(b) Vin P
R Vo
Q
R
(b)
R
R
(c) Vin Q
R Vo
P 12 V
(c)
R
–0.7 V

R R
0.7 V
(d) R Vo (d)
Vin P –12 V
Q R

24. The switch S in circuit of the figure is initially closed,

22. The circuit shown in the figure is it is opened at time t = 0. You may neglect the Zener
R1 diode forward voltage drops. Wha is the behavior of
vout for t > 0?
+
V– Load +10 V
R2
r
+10 V
1 k

rV vout
(a) a voltage source of
R1||R2 S 10 k 5V
0.01 –10 V
(b) a voltage source of
r||R2
V F 5V
R1 100 k
–10 V
 r||R2  V
(c) a current source of   (a) It makes a transition from –5 V to +5 V at
 R1  R2  r t = 12.98 μs
 R2  V (b) It makes a transition from –5 V to + 5 V at
(d) a current source of  
 R1  R2  r t = 2.57 μs
23. For a given sinusoidal input voltage, the voltage (c) It makes a transition from +5 V to –5 V at
waveform at point P of the clamper circuit shown in t = 12.98 μs
figure will be (d) It makes a transition from +5 V to –5 V at
t = 2.57 μs
C +12 V
25. In the given figure, if the input is a sinusoidal signal,
RL
vin P the output will appear as
–12 V vin

t
vin

t
 6

+V 28. The circuit shown is a

R
vin (a) Low pass filter
+ (b) Band pass filter
R –V R1 Vout (c) Band Reject filter
– (d) High pass filter

Vout Vout 29. If the above filter has a 3 dB frequency of 1 kHz, a

high frequency input resistance of 100 kΩ and a high
(a) (b) frequency gain of magnitude 10, then values of R1, R2
t t
and C respectively are
Vout Vout (a) 100 kΩ, 1000 kΩ, 15.9 nF
(b) 10 kΩ, 100 kΩ, 0.11 μF
(c) 100 kΩ, 1000 kΩ, 15.9 nF
(c) t (d) t (d) none of these

30. Consider a circuit shown in figure. Assume op-amp

26. The output voltage (v0) of the Schmitt trigger shown
is ideal.
in figure swings between +15 V and –15 V. Assume RF
that the operational amplifier is ideal. The output will ID = 12 mA
change from +15 V to –15 V when the instantaneous 5 k
R1
value of the input sine wave is 5V
10 k i1 = 1 mA vo
10 sin(t)
vo
10 k
The values of resistors R1 and RF respectively are
3 k (a) 5 kΩ, 5 kΩ (b) 55 kΩ, 5 kΩ
(c) 55 kΩ, 55 kΩ (d) 5 kΩ, 55 kΩ
+2 V
(a) 5 V in the positive slope only
31. For the circuit shown below, assume op-amp is ideal.
(b) 5 V in the negative slope only The input waveform to the circuit is also shown in
(c) 5 V in the positive and negative slopes the figure.
(d) 3 V in the positive and negative slopes 4.7 V 4.7 V

27. For the oscillator circuit shown in figure, the R D1 D2

vin (t) +Vsat
expression for the time period of oscillation can be vout
given by (where τ = RC) –Vsat 100 k
R
C 47 k
vo
vin( t)

R R
5V

(a) τ ln 3 (b) 2τ ln 3 t
(c) τ ln 2 (d) 2τ ln 2
Common Data For Q.28 and 29:
–5 V
Consider the circuit shown in figure.
R So, the output voltage waveform is
R1 C
vi
vo
 7

vout vo
Vsat 7V

vi
(a) (b) R
t Slope 2
R1
–7 V
–Vsat vo
vout 5.6 V

2.5 V vi
(c) R
t Slope – 2
(b) R1
–2.5 V –5.6 V
vo
vout
7V
7.94 V
R2
Slope –
R1 v
i
(c) t (d)

–7 V
–7.94 V
vout
7.94 V 33. Consider the circuit shown below. Assume op-amp is
ideal.
vz2 = 6.3 V
t
(d) vz1 = 6.3 V
R
vin
vo
–7.94 V R

VR
32. Consider the circuit shown below. Assume op-amp is
ideal. Given
R2 Zener diode voltage, vz1 = vz2 = 6.3 V
vz2= 6.3 V Forward bias voltage, vr1 = vr2 = 0.7 V
The plot vo versus vin will be
vz1 = 6.3 V vo
R1
vi 7V
vo

(a) vin
Given that Zener diode voltage vz1 = vz2 = 6.3 V and VR
diode forward bias voltage Vf = 0.7V, then the plot –7 V
between the vo versus vi will be: vo
vo
5.6 V 7V

(a) vi vin
R (b) VR
Slope 2
R1
–5.6 V
–7 V
 8

vo vo
+0.7 V
7V

(c) vin –0.1 V 0.1 V

(c) vi
–VR

–7 V –0.7 V
vo vo
7V +0.7 V

(d) vin –0.1 V 0.1 V

–VR (d) vi

–7 V
–0.7 V

Common Data for Q.34 to 36:

Consider the circuit shown below, assume op-amp is 36. What is the diode current ID2 flow in diode D2?
ideal, and diode cutin voltage Vγ = 0.7 V. (a) –1.12 mA (b) 0 mA
60 k (c) 10 μA (d) 1.12 mA
–12 V
10 k 37. Consider the circuit shown below. Assume op-amp is
10 k
vo ideal and input v2 > 0
vo1
+12 V D1 D2 v1
R = 1 k D1
vi +
– Iv2 R = 1 k

R = 1 k
R = 1 k D2 R = 1 k
v2 R = 1 k
34. What is the value of output voltage Vo?
vin
(a) ±12 V (b) ± 0.7 V D4

(c) 7 V1 (d) –6 V1 R = 1 k D3
–1V R = 1 k

35. The transfer characteristic will be

vo What is the value of output voltage
+12 V (a) v1v2 (b) –v1 v2
(c) –(v1 + v2) (d) v1 + v2
–1.71 V 1.71 V
(a) vi
38. Consider the circuit shown below. Assume diodes
and op-amps are ideal.
5 k
–12 V
vo 5 k D1
vin
+12 V v0
5 k
D2

–1.71 V 1.71 V 10 k
(b) vi
–15 V
The plot of transfer characteristic is
–12 V
 9

V0 40. Consider the circuit shown in below. Assume op-amp

is ideal.
5 10 k
(a)
0.1 F
Vin vin (t)
5 v0( t)
V0

(b) 5
Input voltage waveform is shown in following figure.
Vin vin (t)
5 10
V0
+5
3 4
t (mS)
(c) Vin 1 2
–10 –5
–5 –5

The output voltage waveform will be

V0 v0(t)

+5
(d) Vin
–5 2 3
–5 (a) t (mS)
1 4

–10
39. Consider the circuit shown in below. Assume diodes
and op-amps are ideal. v0 (t)
v01
+10
5 k 10 k
D1 +5
5 k
vin (b) 3 4
t (mS)
1 2
D2 –5
5 k 15 k v0 (t)
v02
+10
The transfer characteristic v02 versus v1 will be
v02 v02

(a) (c) 1 3 4
vin (b) vin t (mS)
2
–5
v02 v02
v0(t)
(c) vin (d) vin +5
1 2 3
(d) t (mS)
4
–5

–10
 10

41. Consider the circuit shown in below. Assume op-amp 42. Consider the given amplifier circuit. Assume op-amp
is ideal. Input waveform is also shown in this figure. is ideal.
5 k

5 k
2 F
10 k
vin (t)
vo(t)
10 k
RL vo
5 k
vin (t)
vin
+5 V

If input voltage vin = 3 sinωt, then the output voltage

t (mS)
0 2 5 7 10 12 15 17 20 22 will be
The output waveform will be (a) 0
vo(t) (b) 6 sinωt
(c) –6 sinωt
(d) 12 sinωt
(a)
43. Consider the integrator shown in figure.
t (mS)
0 2 5 7 10 12 15
R C
vo(t)
vo
vin

(b)
If op-amp having an input impedance of Rin, and
t (mS) open loop gain Aol then what is the pole location of
0 2 5 7 10 12 15 17
the integrator circuit?
vo(t)
1  R 
(a)  1  
RC  Rin 
2 5 7 10 12 15 17 1
(c) t (mS) (b) 
0 RC
1  R 
(c)  1  
 1  Rin 
vo(t) RC 1  
 Aol 
0 2 5 7 10 12 15
t (mS)
1  R 
(d)  1  
–0.5 RC (1  Aol )  Rin 
(d)
–1.0

–1.5
 11

Vo ( s) If Vin = Vm cosωt, then the output waveform Vout is

44. The transfer function T ( s)  is Vout Vout
Vin ( s)
+Vsat +Vsat
1
AOL R2 || (a) –0.7V
t (b) 0
t
sC2
(a) 
1 1
R1 ||  R2 || Vout
sC1 sC2 Vout

1
R2 || t
0.7 V
t
sC2 (c) (d)
(b) 
1 1 –Vsat –Vsat
(1  AOL ) R1 ||  R2 ||
sC1 sC2
1 47. Consider the circuit shown in figure below. Assume
AOL R2 ||
sC2 op-amp is ideal.
(c) 
1 1 0.1 F
(1  AOL ) R1 ||  R2 ||
sC1 sC2
1 200 k
R1 ||
sC1 v1 = 1.5 V vo
(d)  AOL
1 1
R1 ||  R2 ||
sC1 sC2
The output wave form is
v0
45. What is the relation between components R1C and R2
Vout
C2, if is unity at all frequencies? (a)
Vin
t
1 1 0
|| R1 || R2
sC1 A 1 sC2 A 1 v0
(a)  OL (b)  OL
|| R2 AOL  1 || R1 AOL  1
1 1
sC2 sC1 (b)
1 1 t
R2 || R2 ||
sC2 1 sC2 AOL  1 0 t0
(c)  (d)  v0
R1 ||
1 AOL  1 R1 ||
1 1
sC1 sC1 0
t
(c)
46. Consider the circuit shown in figure below. Cut in
voltage of diode is 0.7 V and op-amp is ideal.
–Vsat v0
vin= Vmsint vin
vo 0 t0
(d) t
+Vsat
t
R D
 12

Answer Key
1. (c) 24. (b)
2. (c) 25. (c)
3. (a) 26. (a)
4. (c) 27. (b)
5. (a) 28. (d)
6. (b) 29. (c)
7. (a) 30. (d)
8. (a) 31. (c)
9. (a) 32. (d)
10. (a) 33. (b)
11. (c) 34. (b)
12. (a) 35. (d)
13. (b) 36. (d)
14. (d) 37. (a)
15. (c) 38. (c)
16. (d) 39. (c)
17. (a) 40. (c)
18. (d) 41. (d)
19. (c) 42. (d)
20. (d) 43. (d)
21. (b) 44. (c)
22. (d) 45. (b)
23. (b) 46. (a)
47. (c)