ĐẠI HỌC QUỐC GIA THÀNH PHỐ HỒ CHÍ MINH

TRƯỜNG ĐẠI HỌC BÁCH KHOA

KHOA ĐIỆN - ĐIỆN TỬ

BÁO CÁO THÍ NGHIỆM

MÔN: THIẾT KẾ VI MẠCH SỐ

LỚP L01 --- HK231

Giảng viên hướng dẫn: Bùi Lê Quốc Doanh

Nguyễn Phan Thiên Phúc

Sinh viên thực hiện Mã số sinh viên

Văn Bá Duy 2010189

Thành phố Hồ Chí Minh - 2023

 LABORATORY 1: MOS DEVICE CHARACTERIZATION

EXPERIMENT 1
Objective: Known NMOS operations and I-V characteristics.
Requirements: Simulate and draw curves I ds=f ( V gs ) and I ds=f ( V ds) of NMOS
currently used.

NMOS characteristic schematic circuit

Keep the value V gs=1V and change the variable V ds from 0 to 1.5 to
characterize the change of I ds with V ds :
Parameter Value
Vbs 0V
Vds 0 - 1.5V
Vgs 1V

Schematic circuit of NMOS characteristics when Vgs = 1V

 Ids = f(Vds) curve when keeping Vgs = 1V constant
Keep the value V gs=1.5V and change the variable V g s from 0 to 1.5 to
characterize the change of I ds with V g s:
Parameter Value
Vbs 0V
Vds 1.5V
Vgs 0 - 1.5V

Schematic circuit of NMOS characteristics when Vds = 1.5V

 Ids = f(Vgs) curve when keeping Vds = 1.5V constant

EXPERIMENT 2

Objective: The effects on IV characteristics when V gs, width and length vary.
Requirements: Simulate and draw curves when V gs, width and length vary.

NMOS characteristic schematic circuit

Characteristics of the change in Ids with Vds at V gs={ 0 , 0.25 , 0.5 ,0.75 , 1.0 } V
Parameter Value
L 50nm
W 90nm
Vbs 0V
Vds 0 - 1.5V
 Vgs {0, 0.25, 0.5, 0.75, 1.0}V

Curve Ids = f(Vds) at Vgs = {0, 0.25, 0.5, 0.75, 1.0}V

Characteristics of the change in Ids with Vds at W ={ 180 ,270 ,360 } nm:
Parameter Value
L 50nm
W {180, 270, 360}nm
Vbs 0V
Vds 0 - 1.5V
Vgs 1V

Curve Ids = f(Vds) at W = {180, 270, 360}nm

 Characteristics of the change in Ids with Vds L= { 90 ,180 , 270 , 360 } nm:
Parameter Value
L {90, 180, 270, 360}nm
W 90nm
Vbs 0V
Vds 0 - 1.5V
Vgs 1V

Curve Ids = f(Vds) at L = {90, 180, 270, 360}nm

EXPERIMENT 3

Objective: Known second order effect of MOS transistor in library currently

used.
Requirements:
The ideal I-V model neglects many effects that are important to moder device.
It is useful to have a qualitative understanding of second order effects to predict their
impact on circuit behavior and to be able to anticipate how devices will change in
future process generations.
These effects are listed as follows.
 Some second order effects in MOS transistor
In fact, body effect and channel length modulation are important when
analyzing the small - signal, and the expression determined I ds. Assemble the testbench
circuit:

Circuit diagram for characterizing NMOS characteristics

Characteristics of the change in Ids with V gs when keeping the value Vds
constant, changing the variable Vgs from 0 to 1 at V bs= { 0.1, 0.55 , 0.9 } V :
Parameter Value
 Vbs 0.1, 0.55, 0.9V
Vds 1V
Vgs 0 - 1V

Mạch schematic đặc tính NMOS khi Vds = 1V

Curve Ids = f(Vgs) when kept intact Vds = 1V at Vbs = {0.1, 0.55, 0.9}V
Characteristics of the change in Ids with Vds when keeping the value Vgs
constant, changing the variable V from 0 to 1 at V bs= { 0.1, 0.55 , 0.9 } V :
Parameter Value
Vbs 0.1, 0.55, 0.9V
Vds 0 - 1V
Vgs 1V
 Schematic circuit of NMOS characteristics when Vgs = 1V

Ids = f(Vds) curve when keeping Vgs = 1V constant at Vbs = {0.1, 0.55, 0.9}V
Trả lời câu hỏi:
 Curve Ids = f(Vds)
 Using curve I ds=f ( V ds) shown - each curve represents a different V gs value.
Any one of these curves can be used to calculate λ. Make sure that V bs is 0V
for this simulation. The formula for calculating λ given two points on the
saturation portion of a single curve is:
I D2− I D1
λ=
I D 1 V DS 2 − I D 2 V DS 1

 V Th0 can be obtained form curve I ds=f ( V ds) shown. Using the saturation portion

of the two curves with equal V ds then V Th0 can be caculated as:

V th 0=
V gs 1 − V gs 2
√ I ds 1
I ds 2

1−
√ I ds1
I ds2

EXPERIMENT 4

Objective: Analyze the operation of pass transistor, transmission gate, and

tristate inverter.
Requirements: Simulate, analyze, and answer questions about these designs.
NMOS discharging:
Vpulse 1:
Parameter Value
 Voltage 1 0V
Voltage 2 1V
Rise time 1ps
Fall time 1ps
Delay 0ns
Pulse width 10ns
Period 20ns

Vpulse 2:
Thông số Value
Voltage 1 1V
Voltage 2 0V
Rise time 1ps
Fall time 1ps
Delay 0ns
Pulse width 10ns
Period 20ns

Parameter Value
R 1kΩ
C 1pF
 Mạch schematic NMOS discharging

VC(t) transient response

NMOS charging:
Parameter Value
Voltage 1 0V
Voltage 2 1V
Rise time 1ps
Fall time 1ps
Delay 0ns
Pulse width 10ns
Period 20ns
C 1pF
Vdd 1V
 Mạch schematic NMOS charging

VC(t) transient response

PMOS discharging:
Vpulse 1:
 Parameter Value
Voltage 1 0V
Voltage 2 1V
Rise time 1ps
Fall time 1ps
Delay 0ns
Pulse width 10ns
Period 20ns

Vpulse 2:
Parameter Value
Voltage 1 1V
Voltage 2 0V
Rise time 1ps
Fall time 1ps
Delay 0ns
Pulse width 10ns
Period 20ns

Parameter Value
R 1kΩ
C 1pF
Vdd 1V
 Mạch schematic PMOS discharging

VC(t) transient response

PMOS charging:
Parameter Value
Voltage 1 0V
Voltage 2 1V
Rise time 1ps
Fall time 1ps
Delay 0ns
Pulse width 10ns
Period 20ns
C 1pF
Vdd 1V
 Mạch schematic PMOS charging

VC(t) transient response

Transmission gate:
 Transmission gate schematic
G A B
1 1 1
1 0 0
0 X Z
Transmission gate truth table
Parameter Value
Voltage 1 0V
Voltage 2 1V
Rise time 1ps
Fall time 1ps
Delay 0ns
Pulse width 10ns
Period 20ns
C 1pF
Vdd 1V
 Mạch schematic transmission gate

Simulate the IN - OUT waveform of the transmission gate

Tristate inverter:
 Tristate inverter: schematic and symbol
EN A Y
0 X Z
1 1 0
1 0 1
Tristate inverter truth table
Parameter Giá trị
Voltage 1 0V
Voltage 2 1V
Rise time 1ps
Fall time 1ps
Delay 0ns
Pulse width 10ns
Period 20ns
C 1pF
Vdd 1V
 Mạch schematic Tristate inverter

Simulate the IN - OUT waveform of the transmission gate

Answer the question:

According to the first check requirement, please let us know which cases you use MOS
device as a switch.
- NMOS Pass Transistor is used as a switch in the discharging phase (figuare
8a)
- PMOS Pass Transistor is used as a switch in the charging phase (figuare 8a)

According to the second check requirement, show us some advantages and

disadvantages when transmission gate is used as a switch.
Advantages:
- Bidirectional Signal Flow
- Low ON Resistance:
- Simple Implementation:
Disadvantages
- Parasitic Capacitance:
- Signal Distortion:
- Power Consumption:
- Complex Control Circuitry:
- Limited Voltage Range:
Comment on the position of Drain and Source with respect to Gate in MOSFET’s
structure? How can you demonstrate them?
Gate:
- The gate is the terminal that controls the flow of current between the source
and drain. It is separated from the semiconductor substrate by the gate oxide.
Source:
- The source is the terminal through which current enters the MOSFET. It is
typically located near the gate.
Drain:
- The drain is the terminal through which current exits the MOSFET. It is
typically located on the opposite side of the gate from the source.
In your opinion, data, transmitted in pass transistor and transmission gate, can just be
flowed in one way, cannot it? Explain your idea?
The behavior of data transmission in pass transistors and transmission gates
depends on their design and how they are implemented in a circuit. Let's
explore these two types of switches:
Idea:
1. Pass Transistor:
- Unidirectional: A pass transistor typically allows data to flow in one
direction. It acts as a switch that connects or disconnects the source and drain
terminals. The direction of data flow depends on the configuration and how
the transistor is used in the circuit.
Transmission Gate:
- Bidirectional: A transmission gate, by design, allows data to flow
bidirectionally. It consists of complementary NMOS and PMOS transistors,
enabling it to pass signals in both directions. By appropriately controlling the
gate signals, you can control the transmission gate to be in an ON state for
either direction of data flow.
Considerations:
- The choice between a pass transistor and a transmission gate depends on
the specific requirements of the circuit. If bidirectional data transmission is
needed, a transmission gate is more suitable. If unidirectional transmission is
sufficient, a pass transistor might be simpler and more power-efficient.
A student tries to move signal A, connected to M1, and M4 in Figure 12(a), to M2, and
M3 shown in Figure 12(b), and he realizes that the function of the circuit does not
change. Do you agree with his thoughts? Show us your opinion.
 (a) schematic of tristate inverter (b) schematic of modified tristate inverter (move
signal A from M1; M4 to M2; M3)
If the student simply moves signal A from M1 and M4 to M2 and M3 without
changing any other connections or components, and the function of the circuit does not
change, it implies that the tristate inverter is designed to be symmetrical or that the
specific function it performs is not affected by the rearrangement of these signals.
I completely agree with that opinion

Propose a method to design tristate buffer.

To design a tristate buffer, several crucial steps need to be followed. Firstly,
clearly define the technical requirements such as voltage levels, fan-out, and
conditions for the buffer to be in a high-impedance state. Then, choose the
appropriate transistor type (NMOS, PMOS, or a combination for CMOS
technology).
Next, design the basic circuit of the tristate buffer, including an enable input to
control the tristate state. Build the enable control circuit to ensure that the buffer
transitions to a high-impedance state when disabled and operates normally
when activated.
Design the output stage to ensure the buffer can meet the specified load
capacitance and ensure it has sufficient noise margins to operate reliably.
Simulate the buffer's operation using Electronic Design Automation (EDA)
tools to verify functionality and performance.
Create a physical layout based on the schematic, considering the impact of the
layout on non-ideal factors. Optimize the design for energy efficiency,
especially if the buffer is intended for low-power applications.
Finally, conduct extensive testing to verify the functionality and performance of
the tristate buffer, address any issues, and refine the design to ensure reliability
and performance under various conditions.
 LABORATORY 2: DIGITAL LOGIC COMPONENTS

EXPERIMENT 1

Objective: Known how to design logic gates using CMOS technology.

Requirement: Student must complete the truth table of NAND2, NOR2, and
EX-OR2, then verify them by running simulation.
NAND2 GATE
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
NAND2 truth table

Mạch schematic cổng NAND2

 NAND2 gate symbol
Parameter Value Note
Voltage 1 0V
Voltage 2 1V
Rise time 1ps
Fall time 1ps Vpulse A
Delay 0ns
Pulse width 10ns
Period 20ns
C 1pF
Vdd 1V
Voltage 1 0V
Voltage 2 1V
Rise time 1ps
Fall time 1ps Vpulse B
Delay 0ns
Pulse width 20ns
Period 40ns
 Testbench cổng NAND2

Simulate the IN - OUT waveform of NAND2 gate