Scribd
Upload
447 views4 pages

HW2 - TCMT - Nhóm A

The document contains RISC-V assembly code solutions for various exercises on translating C code to RISC-V assembly and vice versa. It includes code for storing values in memory in little-endian and big-endian format, performing arithmetic and memory operations on arrays using registers and base addresses, and a minimal nested loop solution.

Uploaded by

Lớp 18DT3 DUT - Bách Khoa Đà Nẵng
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
447 views4 pages

HW2 - TCMT - Nhóm A

The document contains RISC-V assembly code solutions for various exercises on translating C code to RISC-V assembly and vice versa. It includes code for storing values in memory in little-endian and big-endian format, performing arithmetic and memory operations on arrays using registers and base addresses, and a minimal nested loop solution.

Uploaded by

Lớp 18DT3 DUT - Bách Khoa Đà Nẵng
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Tổ Chức Máy Tính – HW2

Nhóm A
Tên Thành Viên: Ngô Quang Bình
Đoàn Minh Tuệ
Bùi Trần Diệp Huy
Hồ Văn Tuấn
Phạm Huy

2.3 For the following C statement, write the corresponding RISC-V assembly code.
Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29,
respectively. Assume that the base address of the arrays A and B are in registers x10 and
x11, respectively.
B[8] = A[i−j];

f g h i j Base address
A B
x5 x6 x7 x28 x29 x10 x11

sub x5, x28, x29 //x5 được lưu trữ bởi f=i-j
sll x5, x5, 3 //dịch trái thanh ghi x5 3 bit = f*8
add x5, x10, x5 //x5 = địa chỉ của A[f]=A[i-j]
ld x10,0(x5) // Tải doubleword từ memory đến register x10 = A[i-j]
sd x10, 64(x11)// lưu trữ doubleword từ memory đến register.
2.4
B[g]= A[f] + A[f+1]
slli x30, x5, 3 // x30 = f*8
add x30, x10, x30 // x30 = &A[f]
slli x31, x6, 3 // x31 = g*8
add x31, x11, x31 // x31 = &B[g]
ld x5, 0(x30) // f = A[f]
addi x12, x30, 8 // x12 = &A[f]+8 (i.e. &A[f+1])
ld x30, 0(x12) // x30 = A[f+1]
add x30, x30, x5 // x30 = A[f+1] + A[f]
sd x30, 0(x31) // B[g] = x30 (i.e. A[f+1] + A[f])2.12 R-type: add x1, x1, x1
2.5 [5] <§2.3> Show how the value 0xabcdef12 would be arranged in memory of a little-
endian and a big-endian machine. Assume the data are stored starting at address 0 and
that the word size is 4 bytes.

2.7 Translate the following C code to RISC-V. Assume that the


variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29,
respectively. Assume that the base address of the arrays A and B are in registers x10
and x11, respectively. Assume that the elements of the arrays A and B are 8-byte
words:
B[8] = A[i] + A[j];
slli x28, x28, 3 // x28 = i*8
ld x28, 0(x10) // x28 = A[i]
slli x29, x29, 3 // x29 = j*8
ld x29, 0(x11) // x29 = B[j]
add x29, x28, x29 // Compute x29 = A[i] + B[j]
sd x29, 64(x11) // Store result in B[8]
2.8 Translate the following RISC-V code to C. Assume that the
variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively.
Assume that the base address of the arrays A and B are in registers x10
and x11, respectively
F=2*(&A)
Addi x30, x10, 8 // x30=&A[1]
Addi x31,x10,0 //x31=&A
Sd x31, 0(x30) //A[1]=&A
Ld x30,0(x30) //x30=A[1] =&A
Add x5,x30,x31 //f=&A +&A = 2*(&A)

2.9 For each RISC-V instruction in Exercise 2.8, sh ow the value of the opcode (op),
source register (rs1), and destination register (rd) fields. For the I-type instructions, show
the value of the immediate field, and for the R-type instructions, show the value of the
second source register (rs2). For non U- and UJ-type instructions, show the funct3 field,
and for R-type and S-type instructions, also show the funct7 field.
addi x30, x10, 8
addi x31, x10, 0
sd x31, 0(x30)
ld x30, 0(x30)
add x5, x30, x31

Intrustion Tybe Opcode Rs1 Rs2 rd Funct3 Funct7 immed


addi x30, x10, I 19 10 x 30 0 x 8
8
addi x31, x10, I 19 10 x 31 0 x 0
0
sd x31 S 35 30 31 x 3 x
0(x30)
add x5, x30, R 51 30 31 5 0 0
x31

Ghi chú: x là trường trống


2.12
R-type: add x1, x1, x1
2.20 [5] <§2.6> For the following C statement, write a minimal sequence of RISC-V
assembly instructions that performs the identical operation. Assume x6 = A, and x17 is
the base address of C.
A = C[0] << 4;

ld x6, 0(x17)
slli x6, x6, 4
2.25.Translate the following C code to RISC-V assembly code. Use
a minimum number of instructions. Assume that the values ofa , b, i, and j are in
registers x5, x6, x7, and x29, respectively. Also, assume that register x10 holdsthe base
address of the array D.
for(i=0; i<a; i++)
for(j=0; j<b; j++)
D[4*j] = i + j;
Solutions:
LOOPI:
addi x7, x0, 0
bge x7, x5, ENDI
addi x30, x10, 0
addi x29, x0, 0
LOOPJ:
bge x29, x6, ENDJ
add x31, x7, x29
sd x31, 0(x30)
addi x30, x30, 32
addi x29, x29, 1
jal x0, LOOPJ
ENDJ:
addi x7, x7, 1
jal x0, LOOPI
ENDI:

2.26 T e code requires 13 RISC-V instructions. When a = 10 and b = 1, this results in 123
instructions being executed.
Solutions:
The code requires 13 RISC-V instructions. When a = 10 and b = 1, this
results in 123 instructions being executed.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy