PIN DIAGRAM OF 8085

It was introduced in 1977 and 8-bit

microprocessor. actual name is 8085 A.
It is single NMOS device. It contains
6200 transistors approx. Its dimensions
are 164 mm x 222 mm. It is having 40
pins Dual-Inline-Package (DIP). These
advanced versions are designed using Pin Diagram of 8086 Microprocessor
HMOS technology. The advanced The Intel 8086 is 40 pin DIP Microprocessor. Here we will see the
versions consume 20% less power actual pin level diagram of 8086 MPU. It uses a 5V DC supply for
supply. The clock frequencies of 8085 its operation. 8086 was the first 16-bit microprocessor available in
are: (8085 A;3 MHz), (8085 AH;3 40-pin DIP (Dual Inline Package) chip. The 8086 uses 20-line
MHz), (8085 AH2 5 MHz), address bus. It has a 16-line data bus. The 20 lines of the address
(8085 AH1 6 MHz) bus operate in multiplexed mode.
AD0-AD15 : (Address/Data bus): These are 16 address/data bus.
X1 & X2 Pin 1 and Pin 2 (Input): These
AD0-AD7 carries low order byte data and AD8 AD15 carries
are also called Crystal Input Pins. 8085
higher order byte data. They are multiplexed with data. When AD
can generate clock signals internally.
lines are used to transmit memory address the symbol A is used
8085 requires external inputs from X 1
instead of AD, for example A0-A15.
and X2.
A16-A19 (Output): High order address bus. These are multiplexed
RESET IN and RESET OUT Pin 36
with status signals. These are the 4 address/status buses. During the
(Input) and Pin 3 (Output):
first clock cycle, 4-bit address status signals.
RESET IN: It is used to reset the microprocessor. It is active low signal. it forces the
S2, S1, S0 : Status pins. These pins are active during T4, T1 and T2
microprocessor to reset itself.
states and is returned to passive state (1,1,1 during T3 or Tw (when
RESET OUT: It is used to reset the peripheral devices and other ICs on the circuit. It is
ready is inactive). Any change in S2, S1, S0 during T4 indicates the
an output signal. It is an active high signal.
beginning of a bus cycle.
SID and SOD Pin 4 (Input) and Pin 5 (Output):
A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are
SID (Serial Input Data): It takes 1 bit input from serial port of 8085. Stores the bit at
multiplexed with corresponding status signals.
the 8th position (MSB) of the Accumulator. RIM (Read Interrupt Mask) instruction is
BHE’/S7 (Output): BHE stands for Bus High Enable Status. It is
used to transfer the bit.
available at pin 34 and used to indicate the transfer of data using data bus D8-D15. During T1 it
SOD (Serial Output Data): It takes 1 bit from Accumulator to serial port of 8085. Takes
is low. It is used to enable data onto the most significant half of data bus, D8-D15. 8-bit device
the bit from the 8th position (MSB) of the Accumulator. SIM (Set Interrupt Mask)
connected to upper half of the data bus.
instruction is used to transfer the bit.
RD (Read)’: it is available at pin 32 and is used to read signal for Read operation It is active
Interrupt Pins
when low.
Interrupt: It means interrupting the normal execution of the microprocessor. When
READY (input): This is the acknowledgement from the memory or slow device that they have
microprocessor receives interrupt signal, it discontinues whatever it was executing. It
completed the data transfer. The signal made available by the devices is synchronized to provide
starts executing new program indicated by the interrupt signal.
ready input to the microprocessor. The signal is active high(1).
Sequence of Steps Whenever There is an Interrupt
INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of
Microprocessor completes execution of current instruction of the program. PC contents
each instruction for determining the availability of the request. If any interrupt request is found
are stored in stack. PC is loaded with address of the new program. Five Hardware
pending, the processor enters the interrupt acknowledge cycle
Interrupts in 8085
NMI :Non maskable interrupt. This is an edge triggered input which results in a type II
1. TRAP 2. RST 7.5 3. RST 6.5 4. RST 5.5 5. INTR
interrupt. A subroutine is then vectored through an interrupt vector lookup table which is located
Classification of Interrupts
in the system memory. NMI is non-maskable internally by software.
Maskable Interrupts: Maskable interrupts are those interrupts which can be enabled
INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt
or disabled. Enabling and Disabling is done by software instructions. List of Maskable
acknowledge cycle.
Intr: RST 7.5, RST 6.5, RST 5.5, INTR
MN/MX’ :Minimum/Maximum. This pin signal indicates what mode the processor will operate
Non-Maskable Interrupts: The interrupts which are always in enabled mode are called
in.
non-maskable interrupts. TRAP is a non-maskable interrupt.
RQ’/GT1′, RQ’/GT0′ :Request/Grant. These pins are used by local bus masters used to forc
Vectored Interrupts: The interrupts which have fixed memory location for transfer of
the microprocessor to release the local bus at the end of the microprocessor’s current bus cycle.
control from normal execution.particular location in memory.
Each of the pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′.
Vectored Interrupts: The addresses to which program control goes: Absolute address
LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed
is calculated by multiplying the RST value with 0008 H.
to gain control of the system bus while LOCK’ is active low(0).
Non-Vectored Interrupts: The interrupts which don't have fixed memory location for
TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will
transfer of control from normal execution. INTR is a non-vectored interrupt.
continue, else the processor remains in an idle state.
Priority Based Interrupts: Whenever there exists a simultaneous request at two or
CLK : Clock Input. Clock signal is provided through Pin-19. It provides timing to the
more pins then the pin with higher priority is selected by the microprocessor. Priority is
processor for operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and
considered only when there are simultaneous requests.
10MHz.
TRAP Pin 6 (Input): It is an non-maskable interrupt. It has the highest priority. It
RESET : This pin requires the microprocessor to terminate its present activity immediately.
cannot be disabled. It means TRAP signal must go from low to high. TRAP is usually
The signal must be active high(1) for at least four clock cycles.
used for power failure and emergency shutoff.
Vcc : It uses +5V DC Power supply at VCC pin 40
RST 7.5 Pin 7 (Input): It is a maskable interrupt. It has the second highest priority. It is
GND : These are ground at VSS pin 1 and 20.
positive edge triggered only. The internal flip-flop is triggered by the rising edge.
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue
RST 6.5 Pin 8 (Input): It is a maskable interrupt. It has the third highest priority. It is
according to the table shown below
level triggered only. The pin has to be held high for a specific period of time.
DT/R : Data Transmit/Receive.
RST 5.5 Pin 9 (Input): It is a maskable interrupt. It has the fourth highest priority. It is
This pin is required in minimum systems, that want to use an 8286 or 8287 data bus transceiver.
also level triggered. The pin has to be held high for a specific period of time.
The direction of data flow is controlled through the transceiver.
INTR Pin 10 (Input): It is a maskable interrupt. It has the lowest priority. It is also level
DEN : Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum
triggered. It is a general purpose interrupt. Used to vector microprocessor to any
system which uses transceiver. DEN is active low(0) during each memory and input-output
specific subroutine having any address.
access and for INTA cycles.
INTA Pin 11 (Output): It stands for interrupt acknowledge. It is an out going signal. It is
HOLD/HOLDA : HOLD indicates that another master has been requesting a local bus. This is
an active low signal. Low output on this pin indicates that microprocessor has
an active high(1). The microprocessor receiving the HOLD request will issue HLDA (high) as
acknowledged the INTR request.
an acknowledgement in the middle of a T4 or T1 clock cycle.
Address Bus: The address bus is used to send address to memory. It selects one of
ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into
the many locations in memory. Its size is 16-bit.
the 8282 or 8283 address latch. It is an active high (1) pulse during T1 of any bus cycle.
Data Bus: It is used to transfer data between microprocessor and memory. Data bus is
of 8-bit.
Addressing modes in 8086 microprocessor
AD0 – AD7 Pin 19-12 (Bidirectional): These pins serve the dual purpose of transmitting
Prerequisite – Addressing modes, Addressing modes in 8085 microprocessor
lower order address and data byte. During 1 st clock cycle, these pins act as lower half
The way of specifying data to be operated by an instruction is known as addressing modes.
of address. This specifies that the given data is an immediate data or an address. It also specifies whether
A8 – A15 Pin 21-28 (Unidirectional) These pins carry the higher order of address bus. the given operand is register or register pair.
The address is sent from microprocessor to memory. These 8 pins are switched to high Types of addressing modes:
impedance state during HOLD and RESET mode. 1. Register mode – In this type of addressing mode both the operands are registers.
ALE Pin 30 (Output): It is used to enable Address Latch. It indicates whether bus MOV AX, BX
functions as address bus or data bus. If ALE = 1 then Bus functions as address bus. If XOR AX, DX
ALE = 0 then Bus functions as data bus. ADD AL, BL
S0 and S1 Pin 29 (Output) and Pin 33 (Output): S0 and S1 are called Status Pins. They 2. Immediate mode – In this type of addressing mode the source operand is a 8 bit or 16 bit data.
tell the current operation which is in progress in 8085. Destination operand can never be immediate data.
IO/M Pin 34 (Output): This pin tells whether I/O or memory operation is being MOV AX, 2000
performed. If IO/M = 1 then I/O operation is being performed. The operation being MOV CL, 0A
performed is indicated by S 0 and S1. If S 0 = 0 and S1 = 1 then It indicates WRITE ADD AL, 45
operation. AND AX, 0000
Table Showing IO/M, S0, S1 and Corresponding Operations Note that to initialize the value of segment register an register is required.
RD Pin 32 (Output): RD stands for Read. low signal. It is a control signal used for MOV AX, 2000
Read operation either from memory or from Input device. MOV CS, AX
WR Pin 31 (Output):WR stands for Write. active low signal. It is a control signal used 3. Displacement or direct mode – In this type of addressing mode the effective address is directly
for Write operation either into memory or into output device. given in the instruction as displacement.
READY Pin 35 (Input): This pin is used to synchronize slower peripheral devices with MOV AX, [DISP]
fast microprocessor. the input at this pin goes high. MOV AX, [0500]
HOLD Pin 38 (Input): HOLD pin is used to request the microprocessor for DMA 4. Register indirect mode – In this addressing mode the effective address is in SI, DI or BX.
transfer. A high signal on this pin is a request to microprocessor to relinquish the hold MOV AX, [DI]
on buses.. ADD AL, [BX]
HLDA Pin 39 (Output): HLDA stands for Hold Acknowledge. The microprocessor uses MOV AX, [SI]
this pin to acknowledge the receipt of HOLD signal. 5. Based indexed mode – In this the effective address is sum of base register and index register.
Base register: BX, BP
HLDA Pin 39 (Output):
Index register: SI, DI
The control of these buses goes to DMA Controller. Control remains at DMA Controller
The physical memory address is calculated according to the base register.
until HOLD is held high. When HOLD goes low, HLDA also goes low and the
MOV AL, [BP+SI]
microprocessor takes control of the buses.
MOV AX, [BX+DI]
VSS and VCC Pin 20 (Input) and Pin 40 (Input):
6. Indexed mode – In this type of addressing mode the effective address is sum of index register
+5V power supply is connected to VCC. Ground signal is connected to VSS. and displacement.
MOV AX, [SI+2000]
MOV AL, [DI+3000]
7. Based mode – In this the effective address is the sum of base register and displacement.
MOV AL, [BP+ 0100]
8. Based indexed displacement mode – In this type of addressing mode the effective address is
the sum of index register, base register and displacement.
MOV AL, [SI+BP+2000]
9. String mode – This addressing mode is related to string instructions. In this the value of SI and
DI are auto incremented and decremented depending upon the value of directional flag.
MOVS B
MOVS W
10. Input/Output mode – This addressing mode is related with input output operations.
IN A, 45
OUT A, 50
11. Relative mode –
In this the effective address is calculated with reference to instruction pointer.
JNZ 8 bit address
IP=IP+8 bit address
 3.Control Bus
The control bus holds the control and timing signals needed to coordinate all of the
computer’s activities. Control and timing information., Memory read/write signal.,

Block diagram of 8086 Microprocessor

Definition: 8086 is a 16-bit microprocessor and was designed in 1978 by Intel. Unlike,
8085, an 8086 microprocessor has 20-bit address bus. Thus, is able to access 2 20 i.e.,
1 MB address in the memory. Registers:
As we know that a microprocessor performs arithmetic and logic operations. And an Registers are high-speed storage locations inside the microprocessor and CPU.
8086 microprocessor is able to perform these operations with 16-bit data in one cycle. Designed to be accessed at much higher speed than conventional memory. Registers
Hence is a 16-bit microprocessor. Thus the size of the data bus is 16-bit as it can are classified according to the functions they perform. CPU consist of many register
carry 16-bit data at a time. and each register used for specific purpose large size of register increase performance
The architecture block diagram of 8086 microprocessor is composed of 2 major units, of CPU. Register fetch > decode> execute the data Type of registers
the BIU i.e., Bus Interface Unit and EU i.e., Execution Unit. 1. Registers EU:
Bus Interface Unit (BIU) The data for the operations are stored in circuits called Registers. A register is like a
The Bus Interface Unit (BIU) memory location where the exception is that these are denoted by name rather than
manages the data, address
numbers. It has 4 data registers, AX, BX, CX, DX and 2 pointer registers SP, BP and 2
and control buses.
index registers SI, DI and 1 temporary register and 1 status register FLAGS. AX, BX,
Fetches the sequenced
instruction from the memory, CX and DX registers has 2 8-bit registers to access the high and low byte data
 Finds the physical address registers. The high byte of AX is called AH and the low byte is AL. Similarly, the high
of that location in the and low bytes of BX, CX, DX are BH and BL, CH and Cl, DH and DL respectively.
memory where the Special purpose register:
instruction is stored and Program counter PC, is used to store the address of the next instruction to be fetched
 Manages the 6-byte pre- for execution.
fetch queue where the Instruction register IR, is used to store the fetched instruction it is also called decode.
pipelined instructions are Memory Address Register MAR, is used to store memory address being used by
stored. CPU when CPU wants to read or write data in memory it store.
The BIU has to interact with Memory Buffer Register MBR, is used to store the coming from the memory or going
memory and input and to the memory
output devices in fetching the instructions and data required by the EU BIU takes care
Stack Pointer Register SPR: stack is set of memory location which data is stored and
of all data and addresses transfers on the buses for the EU like sending addresses,
retrieved in an order. it point to the topmost element of stack.it is called FILO or LIFO
fetching instructions from the memory, reading data from the ports and the memory.
EU has no connection with System Buses so this is possible with the BIU. EU and BIU General registers/Data Registers: are used for temporary storage and manipulation
are connected with the Internal Bus of data and instructions.
An 8086 microprocessor exhibits the property of pipelining the instructions in a queue AX Accumulator register consists of two 8- bit registers AL and AH, which can be
while performing decoding and execution of the previous instruction. This pipelining is combined together and used as a 16-bit register AX. Accumulator can be used for
done in a 6-byte queue. Also, the BIU contains 4 segment registers. Each segment multiplication, division and I/O operations and string manipulation
register is 16-bit.: BX Base register consists of two 8-bit registers BL and BH, which can be combined
1.Code segment register: It is a 16-bit register and holds the address of the together and used as a 16-bit register BX. BX register usually contains a data pointer
instruction or program stored in the code segment of the memory.Also, the IP in the used for based, based indexed or register indirect addressing
block diagram is the instruction pointer which is a default register that is used by the CX Count register consists of two 8-bit registers CL and CH, which can be combined
processor in order to get the desired instruction. together and used as a 16-bit register CX. Count register can be used as a counter in
2. Stack segment register: The stack segment register provides the starting address string manipulation and shift/rotate instructions
of the stack segment in the memory. Like in stack pointer, PUSH and POP operations
DX Data register consists of two 8-bit registers DL and DH, which can be combined
are used in this segment to give and take the data to/from it.
3. Data segment register: It holds the address of the data segment. The data segment together and used as a 16-bit register DX. Data register can be used as a port number
stores the data in the memory whose address is present in this 16-bit register. in I/O operations. In integer 32-bit multiply and divide instruction the DX register
4. Extra segment register: Here the starting address of the extra segment is present. contains high- order word of the initial or resulting number
This register basically contains the address of the string data. EU Flag:
It is to be noteworthy that the physical address of the instruction is achieved by >Overflow Flag (OF) The result is too large positive number, or small negative number
combining the segment address with that of the offset address. when the system capacity is exceeded.
6-byte pre-fetch queue: This queue is used in 8086 in order to perform pipelining. As >Direction Flag (DF) - if set then string manipulation instructions will auto-decrement
at the time of executing and decoding in EU, the BIU fetches the sequential upcoming index registers. If cleared then the index registers will be auto-incremented
instructions and stores it in this queue.
>Interrupt-enable Flag (IF) - enable/disable flag setting this bit enables maskable
The size of this queue is 6-byte. The queue exhibits FIFO behavior., first in first out.
Execution Unit (EU) interrupts,
EU works all the calculation and manipulation work and BIU work as data transfer from >Single-step Flag (TF) - if set then single-step interrupt will occur after the next
memory to microprocessor or ports. The major reason for this separation is to increase instruction
the processing speed of the processor. EU receives program instruction codes and >Sign Flag (SF) - set if the most significant bit of the result is set result of the operation
data from the BIU, stating from where to fetch the data and then decode and execute is negative, then the sign flag is set to 1 else set to 0..
>Zero Flag (ZF) - flag is set to 1 when the result of arithmetic or logical operation is
those instructions.
zero else it is set to 0.set if the result is zero.
ALU:The arithmetic and logic unit carries out the logical tasks according to the signal
>Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the
generated by the CU. The result of the operation is stored in the desired register.
Flag: Like in 8085, here also the flag register holds the status of the result generated AL register.
by the ALU. It has several flags that show the different conditions of the result. >Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the
Operand:It is a temporary register and is used by the processor to hold the temporary result is even.
values at the time of operation. >Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit
The reason behind two separate sections for BIU and EU in the architecture of 8086 is during last result calculation
to perform fetching and decoding-executing simultaneously. EU Pointer: These can be accessed only as 16 bit registers.
Working of 8086 Microprocessor IP - instruction pointer: Always points to next instruction to be executed. IP register
In the previous section, we have discussed the operation of various sections of the BIU
always works together with CS segment register and it points to currently executing
and EU. Now in this section, we will have a look at the overall processing cycle of the
8086 microprocessors. So, basically, when an instruction is to be fetched from the instruction.
memory, then firstly its physical address must be calculated and this is done at the BIU. Stack Pointer (SP) is a 16-bit register pointing to program stack
The physical address of an instruction is given as: Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is
PA = Segment address Χ 10 + Offset usually used for based, based indexed or register indirect addressing.
For example: Suppose the segment address is 2000 H and the offset address is 4356 Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and
H. So, the generated physical address is 24356 H. Here, the code segment register register indirect addressing, as well as a source data addresses in string manipulation
provides the base address of the code segment which is combined with the offset instructions.
address. Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and
The code segment contains the instructions. Each time an instruction is fetched the register indirect addressing, as well as a destination data addresses in string
offset address inside the code segment gets incremented. Further, the desired manipulation instructions.
instruction at that memory location which is present in the form of the opcode is fetched Registers BIU : BIU has 4 segment busses, CS, DS, SS, ES. These all 4 segment
by the microprocessor through the
registers holds the addresses of instructions and data in memory. These values are
data bus.
used by the processor to access memory locations. It also contain 1 pointer register IP.
Suppose the instruction is ADD
BL, CL. But, inside the memory, it IP contains the address of the next instruction to executed by the EU.
will be in the form of an opcode. Segment Registers
So, this opcode is sent to the The memory of 8086 is divided into 4 segments namely
control unit. 1.Code Segment (CS) register is a 16-bit register containing address of 64 KB
The control unit decodes the segment with processor instruction. The processor uses CS segment for all accesses
opcode and generates control to instructions referenced by instruction pointer (IP) register
signals that inform the BL and CL register to release the value stored in it. Also, it 2.Stack Segment (SS) register is a 16-bit register containing address of 64KB
signals the ALU to perform the ADD operation on that particular data. segment with program stack By default, the processor assumes that all data referenced
It is noteworthy that in any instruction, like ADD BL, CL. BL denotes the destination of by the stack pointer (SP) and base pointer (BP) registers is located in the stack
the result of the add operation. This clearly shows that whatever, the operation is segment
performed its result must be stored in the first register i.e., BL for this particular 3.Data Segment (DS) register is a 16-bit register containing address of 64KB segment
example.
with program data By default, the processor assumes that all data referenced by
Let us take
general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data
another example:
Consider an segment
instruction, ADD 4.Extra Segment (ES) register is a 16-bit register containing address of 64KB
CL, 05H. segment, usually with program data By default, the processor assumes that the DI
This means that register references the ES segment in string manipulation instructions
the operand CPU:
which is 05H is to A central processing unit (CPU) is the electronic circuitry within a computer that carries
be added with out the instructions of a computer program by performing the basic arithmetic, logical,
the data present control and input/output (I/O) operations specified by the instructions.
in the CL register CPU is considered as the brain of the computer. CPU performs all types of data
and is stored in processing operations. Uses Memory Circuits to store information. Uses I/O Circuits to
that particular register i.e., CL. In such conditions, the operand is not provided to the communicate with I/O Devices.
control unit as only the opcode is required to be decoded by the CU. Hence the
Bits, Bytes and Double words:
operand is directly provided to the ALU. Also, the status of this result is stored in the
 Each 1 or 0 is called a bit.
flag register. So, whenever, ALU carries out an operation, it simultaneously generates
 Group of 4 bits = Nibble
the result as well as its status.
 Group of 8 bits = Byte
What is a computer bus?  Group of 16 bits = Word
A bus is a communication system in computer architecture that transfers data between  Group of 32 bits = Double words
components inside a computer, or between computers. all the components related Memory
to hardware (wire, optical fiber, etc.) and software, including communication protocol. Information processed by the computer is stored in its memory. Like Program, Data
The following are a few points to describe a computer bus:- Not all accumulated information is needed by the CPU at the same time Therefore, it is
A bus is a group of lines/wires which carry computer signals. more economical to use low-cost storage devices to serve as a backup for storing the
A bus is the means of shared transmission. information that is not currently used by CPU
A number of channels in one bus. e.g. 32 bit data bus is 32 separate single bit Memory Operations:
channels Read (Fetch contents of a location), Write (Store data at a location)
Following are the three components of a bus: – The memory unit that directly communicate with CPU is called the main memory.
1.Data Bus Devices that provide backup storage are called auxiliary memory., The main memory
The data bus is a two-way pathway carrying the actual data (information) to and from occupies a central position by being able to communicate directly with the CPU and
the main memory. Remember that there is no difference between “data” and with auxiliary memory devices through an I/O processor., A special very-high-speed
“instruction” at this level., Width is a key determinant of performance 8, 16, 32, 64 bit memory called cache is used to increase the speed of processing by making current
2.Address bus programs and data available to the CPU at a rapid rate
The address bus, a one-way pathway that allows information to pass in one direction Addressing Data in Memory:
only, carries information about where data is stored in memory. Identify the source or Intel Personal Computer (PC) addresses its memory according to bytes. (Every byte
destination of data. e.g. CPU needs to read an instruction (data) from a given location has a unique address beginning with 0)., Depending to the model of a PC, CPU can
in memory., Bus width determines maximum memory capacity of system., e.g. 8080 access 1 or more bytes at a time, Processor (CPU) keeps data in memory in reverse
has 16 bit address bus giving 64k address space
byte sequence (reverse-byte sequence: low order byte in the low memory address and
high-order byte in the high memory address)
Memory Organization:
Memory is organized into a collection of bytes., Each byte is identified by a number –
Address., Number of bits in an address depends on the processor, Example:- Intel
8086: 20-bit address, Intel 80286: 24-bit address., Data stored in a memory byte –
Contents., Number of bits used in the address determines the number of bytes that
can be accessed by the processor.., Example: If processor uses 20-bit address, it can
access 220 = 1048576 bytes = 1 MB of memory