UNIT II ARM PROCESSOR AND PERIPHERALS SYLLABUS ARM Architecture. Versions - ARM Architecture - Instruction Set - Stacks and Subroutines - Features of the LPC 214X Family - Peripherals - The Timer Unit - Pulse Width Modulation Unit - UART - Block Diagram of ARM9 and ARM Cortex M3 MCU. 2.1, INTRODUCTION Millions of electronic gadgets around the world invade our daily life and we have become completely dependent on them for performing most‘éf our work. A very nice example to justify this would be a smartphone that everyone is quickly adapting to, diie to its varied features. These gadgets are the pleasing results. of the ceaseless developments in the field of electronics. Most of these gadgets are fitted with embedded processors that not only.occupy less space but also ensure that users get a smooth experience while using the device. The ARM processor cores used in most of these devices follow an: architecture that helps them perform efficiently. Nowadays, there are several embedded’ architectures: in use such as ARM architecture developed by ARM Ltd, Atmel’s AVR architecture, TI's MSP430 architecture and many more. However, the extensively used: and most popular embedded architecture amongst many companies is the ARM. Ltd’s» ARM architecture. An ARM Processor is one of a family of CPUs based on the RISC © (Reduced Instruction Set Computer) architecture developed by Advanced RISC Machines (ARM).ARM_ makes , 32-bit and 64-bit RISC. multi-core processors. RISC Processors are designed to perform a smaller number of types of computerFreed ot Reel Tie Sie) (eal isco otha they more il sev gh apd psforin operate at a ih pS ‘roneeded instructions. eng nso res or en FS) BY sing OS omance at ae RISC processors provide Pt rutin $2 COmputi ominnng patsy, RISC PSC (comes aston it computing cone desis such ely wed in consumer eles 3 “ARM preesors ae exten we wrote devies, sch ay media ayes and ot cmon es mia ae an Oe mae ato ie ba i ee iegte ereity GO), The ARM eh enabes «alr di 22 i 2 comet oe ove cmtmiion ma rei iis ve “tee ues serge tue of RM eB i en ui anal pend ofc pve! oan «seu wd gf dk gee ino IM I gn it execs oa ye ces wing ARM imate ‘aps ve bind feu Sar el sone DSP persons. (advo were neon ion. : Monty spat rsa acters i, (ant. econ tess hh petra, Maa vito spor ‘The simplified design of ARM processors enables: more efficient ‘multi-core! processing and easier coding fer developes. While they dn’ have the same r2 compute thoighpat as the prodcts of x86 market lender Intl, ARM process * eeaeeoee Cr Proceso” and Peripiraly Io moving ito the server maker, move that represents 8 large ange in direction and a hedging of tes on its a Pvfomance- pert over 1a 16 24 oF moe ores increases ce by scaling up the speed and sophistication ofeach proceso. uring force sped and power to handle demanding computing werkoeds In comparison, an ARM server uses pehaps hundreds of smaller, less sophisticated, low-power processors tat share processing tks among that ge number instead of just a few highercspacity poceson. Thi spprosch il sometimes referred to as “scaling out” in cont wth the “scaling op” of x86 based servers 2.1.2, HISTORY OF ARM ‘Advanced RISC machine (ARM) is the fit Reduced Instruction Set [Computer (RISC) processor for commercial ss, which is curently being developed by ARM Holdings. The history of ARM processor dates back to 1953 in England when Acom Computers Lid officially lamched an Atom RISC| Management project ater being ispred w design it wm processor by Berle | RISC, one ofthe high-impoct projects under ARPA's (Advanced Research Proje [Agency, now converted to DARPA) VIS pret, dealing with RISC-based microprocessor design led by David Patenon who euaed te term "RISC. As the name suggests it doesnot mean ta the processors wth estan 100 instetion | are qualified to RISC category, bt instead they shold have an highly optimise insti st. ‘ARM in the beginning was Known as Acora RISC sachine. Wih VLSI Iaechinology Ine. a its sion partner, ARM came wp with ARM. the fist ARM| silicon on Apri 26, 1985, which was usd aa second proceso to the BBC Mir fo develop the simslaton software to fissh work onthe suport crs (VIDC, 10C| and MIEMIC) and 0 inccase the opeaing spest ofthe CAD software tse in development of ARM.(2a) “Apple, whilst developing an ene pesos igi asia reultements needs fr i anagem ail, Apple calor ie result of hi enlboration w= “th 43 percent sre ed wil lee. separtecompany. ARM Th fa development section of became he acronym for edvance ‘Some ofthe general ete ‘Lanse general purpose 32-bit Fined 32-instrction 2 Singl-yele execution i possible, Pipstined exces iy ne corpating plat Tun that only ACO ementatin, bute AP ia acorn o develop ARM that both Acom Grou se ME ESL Technoogys In. 28 2 soa exabished i ‘hoor es employed here AF RISC machine RISC ae Histed hers replter banks Hardwired instotion decode foi rede Hea Tne Sen] sm for its Newton, a Pagse machine was e106 10 the TAM hd no integral memory p and Apple Computer| i 1990 Also he advanced research flr that-time, ARM instead of mitocoded ROMS biference between RISC and GSC arhitctures: abe 2.1 ference beeen RISC and CISC architects Com Proesor and Peripherals Complexity inthe micro ae Compiesityin the compile ‘Single register set Mune eis sis | ARCHITECTURE veRgggS ————_ | ya, ARM ARCHITECTURE VERSIONS 7 et» a 1 according (0 the core the that ar grouped iat fen *Y use. The families ent eM, ARDII0, and ARM cores, The poate ceed 8 he ARM, Sn cow ng Toe Cena? ects Sen dnc Sat ee ee, te fester eee Within each ARM fii, tee we sumbe stnageent,ccke and TCM pocsoretenons Acoso pod at he munber of fnilis aac ad eet vom min ok fan St eritions within oh SNe ‘case RISC 1. [Complex insetions aking | Simple instructions taking one ruil yee ele Z| Anyisructon may weirto” | Only LOADISTORE refer to memory = _| memory Not ivlied orl pipelined _| Highly pipelined “4 structions nterted by the | Isrtionsexceuted bythe niro-progrim adware 5. | Varin format Fixed format insractions 6,__[ Many instruction and modes ew isiretions and modes ; Example core even | sgtemettn TSA etancemet ARML int ARM proesor 26bicadesing anv | ARM2 s2-biemulipler s2-bitcoprsennr supp ARMv2a | ARMS Onshipeake Aoi svapinstton ‘Coproceszr 1 foreahe mangement ARM [ARMG and | 32itaddessiog ARMTDL Sept pra pst New modesundefined insrocion tnd sor MM sport vial nemonyIsa enhancement ong miply ARMS [| [seeaeARM ea wt a ate fare Soe swt find operations det adressing mode no longer supported fe for schitectually Taunt Supeset afte ARM VAT rm insets added for changing tte eoween ARM aod Thunb ntancol mip instucions| x DSP-peinsttons Faster mail istrctons ava eelention improved muliprocessor instructions Unaligned and mixed endian data handling New mulimedin ini ‘Arcitecture ARMWAT ARMVSTE ‘cones-A (2 ‘conexcA (64 bit) [ARM follows the nomescatre shown in ae | ees mplemenistions ARM Nonecatre - The leters oF Words afer “ARM we wad Ww adeeb lames “| | x-Family or eres yo Memory Managemen Protsion Unit 2-Cache ‘T16 bit Thumb decoder D-JTAG Debugger M~Fast Multiplier 1-Bmbeddedtn-cicut Emultor (CE) Macrcell 'BBrhanced Iastueton for DSP (sures TDM J azelle (for accelerate JAVA exciton) F Vector Floating-point Unit POSS oo eee ee S~Sjnhésizable Version Explanation ofthe features [T=thumb instruction Set ‘© ARM Processors support bh th 32-bit ARM Inston Set and 168i Thumb Instruction Set. ‘© The original 32-bit ARM Insrstions consists of S2t opcodes which tums out o be a4-byte binary pater. ARMSFase and Real Te Sen) = sr or tit opsodes of 2b binary Ta nin + 16s pe ce ae Seemed eee 2 et eee 2 int meee oe eae A ecm a a acca eee Me ai mew mn sel je ee Oe ene mm acta yamome tA ceo fon Se a ee tenes oe eae Seen aera eet easrares Scene eee mere ties sé small an spe multiplier un Jes to complete & singh! st Multiple unit the clock cyeles rogue aot redoced ad modem ARM Processors it product ina single ele. | ck ie an ware that allows the processor xecuton ol (a gc synthesizable ‘an example in ARM? family of processors i the A gasod LPC2148 Processor or isthe ARMTTDMES archer 122.1, ARM FAMILY cessor a Periph |g The ARM Processor Cores aaa lable a source code, ‘This software core ean te comida understood by the EDA Toots, Using the proceso source code ti ‘of the ARM Processor Possible o moeity the architect Ho 8 format that can te easly |@ The ARMT core haa Von The ARMT cor as Von Neamt, ue thd snd istctions we the sme bus Te see bas tne log ‘excite th acievte ARs Tassos 4 The ARMTTDMI wast fist of : cr rie fessor insode in 1985 by ARM. tiscanetys vey pops ee andi ed may 3B-hit embedded proceso 4. 1 proves very goodpefimaneopver mt. On iia ‘sation inthe ARM? fay the ARMETOMIS {The ARMTTDMLS has these opening caress snd ZNROITTDMI buts lo testa 4 ARM20T isthe mom eile member of he ARNT fit ess it itelades an MMU. The psec he MMU mens be ARNOT Cepabe of handling he Linx ad Mlcosoh embed. atom erating systems The procenn lo ices a wie cate. The estar lca be rncted to higher adie by sting copes 4 Avatervarain isthe ARNTEES presen, abo onesie ‘NOMS i ute ire sine kes est ple 2 ‘ete ARMOSTED insons Tis ero of the ARM DeFed and vot Te Ste Tas provi Sve aesertn at atanced instructing ot out any meray Protein rane Nn a ys 1 Bc of Ses A eh cnn ci ten a iin te oN en sins igo ene Pv 52 ARMTO FAMILY ‘The ARMIO, announce 'e announced in 1999, was designed for perfomance. It — totter te Hare ee ee tow he ARN sritecture, which separates the data D and instruction T buses. ‘vector floating a oa 1 ee “ 0m") es nad aor ity was the ARM920T, whic 1 in the ARMS family was th ic ARMIO pipeline. The VEP signifies ince ineeasesoaing point performance and is complit with the IEEE 754 etm TEBE 754.1985 foaing point 4 The ist pres luge a eprae D+ ache and an MMU, van be used by operating systems fequring, vital Fe ARNOTT ia veraon he ARMODYT bot with 4+ The ARMIODOE ih i proces re 1 ARIE fs rr ARM Neen eee yam ate eum ARNO nc al aan i 8D aor bee 1 1 ht pl Yo ing nd Hh ‘berate AOR ao dt te ee anchitectire v4 instrtons. '& ARMIO26EL.S js very similar tothe ARMSDGELS but wth bth MPU| and MMU. This processor has the pefornance ofthe ARDAIO wth he Aexibiliy ofan ARMS26ELS “The nent process in the ARMS family wére based onthe ARMOE-S core ris coe is sytbeszale version ofthe ARMS cove with the E extensions, The ue two vations the ARMBS6ES and the ARMSSSE-S. Both execu chien TE insroctions. “Thy alo sport the optional embeded trace macrocelETM), which allows a developer to tae instuton and data execution in real ime on the processor Tiss import when debugging ppiaions with time-crieal segment ‘The ARMO46ES inudes TCM, cache, nd an MPU. The sizes of the TCM ani caches are configurable. This processor is designed for use in embedded cont! spplcaions that seque deeminisic’reabtime response. In. contras, tt JARMSGGE does not have the MPU and cache extensions but does bev cousguabie TCM. . lz. ARIAT FAMILY © The ARMII361S, announced in 2003, ves designed for his performance and power ecient applicins. ARMII36VS waste fist processor implementation excel acitecture ARMU6 instructions. © It incorporates an cightstge pipeline with sparse loud sore and ihmetic pipelines, Included in the ARM insrstions ae single instuetion multiple dna (SIMD) extensions for medin oes, specifically designed to increas video frcesing peTomancs,pect i Periph a) fe cB eae rr ito and real time response, ay Phe ARRIGO isan ARMIIRGDS Wi ere eet nt fr eating eae spon Whe Hh eran 6 et Foss ae wd ting pit ni or fst loan imperan ® ed and timing deadtns ae 4 The ComecR finily includes the 723, ARM PROCESSORS ‘cortex RS, Contex-R7 and Conny Ee SES ik Cones “ARN Processors can be vided not PS 4 ARM Classe Proseson, ‘ARM Embedded Prosesors and “ARM Aplin Processor. “gamit Chase poss ince ARMD, ARMO end ARMY ig Pa ATTMDL sil Ge hghest shiping 32 pometo, ARN ers ae sil ed in many all and silo 32-8 doves, a sacmmmocesos “Bren thogh ARMT or other classic ARM Processors can be Use fr fal sie embeded systems, newer embedded ystems are built wing the advanced ARM embeded proceso or the Cortex-M process and Corer R Processors. 5 ARM ConexcM Processors have a Microcontller profile wile te Corer Processors have Real tie profile ARM ConeseM Process are energy eicen, simple to implemen tnd sce mainly developed for advanced embedded applications. ARM| ConerM Procestrs re ier divide int several processor cores lis Corer MO, CortxeMD+, Cortex, Cortex-Mé and CortexMT. [ARM Cort Series of processors provide solution for real in somtedded ystems. They provide high reliabiliy, high fault tolerane|“Fated ond Real Tre Sten) Tin vied iat igh performance, ih © The Caner Pe a processors. Each sub division iceney and ulte-igh eicieney BPE pps several types of proceso 0. Pam A ARCHER nine GSE - Rei "ARM was an acronym for Advanced RISC are Sep ana de 0 fly of came ocr DSA en a RISC CPU desizn developed by British Company ARMY bongs” "ARM architecture has ben jn velo sic insnetion set arbiter “Te aeitecture bas evolved overtime, coves, te pois ae fied 9. ent siace 1980s and most widely usd and starting with the cortex series of na. “plain PofileCorex ~ A series "Realtime Profile” Cortex - serie sae CCovtex-M series | scroonteller Profile ree ne at eel a et ee nnn eh i re but lo supports 16 its or 8 its datatypes. Cm Proceso ond Perpheras 10, ARM processors wie the AHB (AMBA Advanced Highperfomance Bus) ‘The ARM core is considered ot fina functional unite conned by dts bases 'ARM permits proprmming by of ah! eis. 2a nice cmb tpn a pedeclateaate aap Solna ii Cyt tae lo woe a sad energy consumption. I maximise withthe operating sjtemandmeile OS. ns EM Wome 116 bit pte com in tems Interface. AMBA is an established opensource spsicnton fo imercomnects. fenton for enh ARCHITECTURE 1 Arrows represents the flow of ata 1, Lines represent he buses, Il, Boxes represent either an operation sit sorag sr ‘& Data enters the pocestor cove dough data bus. I iter ta item (instruction eect If it is an insotion then th inswction decoder insets Instructions befor they are executed 4 fits a dota then the da item x psd in th eit il tis 32 bitregister, © ARM instruction have 10 ester 1. Ro, Rn source register Ra destination repiser = Source operas ae rd buses Aad. the eit le sing intelArithmetic Lage Unit ALE i aks the He use and we the suit rest bus values RO td store instions 9 ies i tres res eit, important feature of ARN Tor MAC{ Matin scumulte and Ran fom A and irc tothe ester Hle using “paseo Rl Te Ste] the ALU to generate an IM is bared shies = onal eee en = onto a i (esse |S ue er] | Sat ramet 1] 2) ee = ie | Fig 2 Accu of ARE red Ca Presson ond Priperals ‘The ARM architecture species Flowing CPU mad esr cra ones ie wh At any oe in rs du o external iy User Mode ‘rae only nonprvileged mode a systern mode ‘The only privileged mode thats no excting by insrotion that expicly weteree Supervisor mode ‘A piileged mode entered whenever i exceted the CPU is resto whe a SW instetion iw Abort mode ty an exeption ican oly be by the mode bis of he CPSR. | privileged mode that ig entered is entered whenever a exception occurs. Prefeth abor or én abo ob undefined mode ‘A privileged mode that is entered whenever an nd jae se intostion exception li ttereupt mode [A privileged mode that is entered whens = benever thé pressor accepts oF IRQ) (Fast interrupt Mode A privileged mode th red wh proceso sxepts end FQ] at is entered whenever the provesior scents a (a HP raode ‘A hypervisor mode intioduced in ARM V 7A fr corex AS processor fr roving hardvare virtualization support(es) 24:3, PROGRAMMING INST “The ARM acitecure nla Loudon siete (i. Nosoppon for salted ww titres le wo nucTION fotlowing RISC tures memary accesses sim 1632 Ped inrtion with of 32 Bis © 8 ot of decreed ode density fo). Monty sigleclokesleercton Even though thas etre, some ofthe tio nny acer sich te 0206; Moola 6020 ef “Condos execution of mos inscton reducing ba onpesating forthe ak fa ranch predictor (0) Acihmetiinstotion ater conton codes oly when desired wy ‘not athe iesrtion and adress calelations Ponerflindvedadessng modes. Alinkeister leat Fnsion cells. co) ” modes andthe underying hardware. The instucton defines what il do ode cen ccumstres, Insncon tn havea variety of characterising: 1. ined ver variable ength 2. Addresing modes 3. Numbers of operands 4. Types of operon supported “Two priory level neopt subsystem with switched register banks. The inscion st of the computer defies the intrfice between software “teed ed Rel Tne Ste] xy decoting sn pipelining athe ral sign features ate sed in sch overhead nd) Sot brel shir whieh canbe used without performance penalty with ardor Cg bresesr ond Perils Pe [ARMT isa Von Neumann architecture aching an i raat. 1, The standard ARM word 32 tong “The word may be divided in a be divided no foe bt bcs [ARM T allows ade upo52 Bit og. An ade ee ress refers t a byte not a end. Word has location 0 We | has location 4 ‘Word 2 as location 8 soon “The ARM processor can be congue a sir itl edin mode oped mote ste sina wed Init enlian mde th lowe order eter Svein in te ow ner bis oF ie it supports tw basic pes Bree | woe oat [om] ow] ‘Fi. 2.2. Bye Orgmnications win an ARM wor Boeraen ‘lg, 2.2 Bye organo within ax ARM word Inti endian mode the lowest order yte stored i the highest its fe word; a [pes operates oe wr se ean Se pen oe et oc Si a we a mem oo ae 2 er pig 3 tC esr ran ae nace ep eps ape! Pe irecly reference main "re aa pecan mst Sst be ode rere gil siing Peon ee rey rate CPR ee fang nt ifr ns ren f hat aides or. in two's complement bit est when he esl aati 1, The negative OY ita ‘she ois se when every it of he et 8 27 3 recur ( itt when there ira cry otf te operations a etre (¥) it et when an aimee operation results In an oveflow. ine 8,6, ¥2i X= (@+8)-6 Y= atheros = ()(S) RUN(aac Pee (2) ES Sten] [pines intense _{ RIS ein ares [RA ‘MN | move he NOT ofthe 32-612 2.5.4.2, SARREL SHIFTER “tata processing insotions a within the arithmetic Tog a eet pet nef te ARM Pon ih a AL ray pte noe of te sue et eh 2A ie amber of poston efi iter the ALU, Th eM ee power nd ext of many proces operations. Tver da procesing istreton tht do 04 ws Eesple. the MUL (natpy), CL2 (count lea (Ganedemurted 32-8 oinseactons. “ge dtaproeesinginstrtion ht donot se the are hi, fi Ze the MUL (ips), CLZ (cunt lading zero), sed QADD| (dgned eunted 32-itadinsewctions. se the bare Si, for ‘2:r0), and QADD| (ce | eee ee Fig. Bese T N shift operations aa Immediate 7 ae ig. 24 Bare shifter end ALU ei ie ‘Table 2.2 Barrel shifter operations = = Mnemonic | Description Shift | Result Shift amounty er tes a isk. logical shift left. |x a a : —— rotate ightBaetateated Tien) | gre on erp = } = — 9 | Lecisltiwiee AND ote sa | Rant open — {|| | Poe tittsseeeteen ies Termes) ee ei | ORK [tsetse OR ove 328i | [Sameer [amas (| | eects Tee | eee [ean | 0 "ORoftwns2itvaes —[Rermman | | j ee ne [ Rm. ROR # shift BIC_| logical bit clear (AND NOT) [Reea, | | ome ee 439, comestton rang ; = Ra RK j inset aeaancne “he omarion isto are wea conga ort | t | | fee Thy upset rr fag Nis ssontng eas eek ee : | itu ont i er “Fo cameos tons pee aon and sbtrastion of 32-5 send aren yuan nstraction>(ceond>{S} Rd, Roy Ns [RcresNvery | [ra-meen RSD | revere boactofrwo32it |RE=N—Ro | va RSC [revenencbeatwithennyof | RA=N—Rn= ear Ns) 02-5 vaes 586 | sabre withcany of 9052 -Ra-N~ Hay Nas) sales SUB [bone oseitvaes | RAD Ro—N 25.2.4 Logical instructions Logical iastuetione perfor bitwise logical operons on the two sou egies sn instruston>{){S) Rd, Ro, N were N's the result of he esc. After the hts have bsen se te inersana, ese fw by using conditional execution. synan: instruction» (} Ra, content ato tne] ‘ena [compare negated fags setasareofRa=N cur [compare fags setasa ral of RaW “THQ | test for equality of wo AsgssetasareultofRaaN | co FRaAN ‘sr | testbits ofa 32-bit value fags cetasareul ofa EN 25.1.6. Multiply instructions ‘The multiply instrations multiply the contents of put of rps and. depending upon the instruction, accumulate the ets in with ater ei. The erg malities accumulate onto pai of eis repesening a tht vale. Te eal esl is placed ina destination regi oc pu of ees Syntax: MLA (){S) Ray Ri, Bs, Ra MUL{)(S) Ra, Rn, Re MLA MOL. |raliply Syatan:(){S) RULo REM Ros RS ni ar ne | Ricrmms | ultiply and accumlaea ea Te | Tired wai eum Trai, RaLa) = SOL dete IRdHi, RéLo} + (in * Rs) Ted ai (Ra, Rata) = SMU [see mp ve iat “cgay ecomaielng fa Riba) = ‘vita [ose atin tat neal = ants) TA | wad ma (Rat, Rata) + AU | se is at [ac | pair Ses 1252. BRANCH INSTRUCTIONS ‘A bach nstreton changes the flow of excetion or thie pe of intrusion allows programs to have’ subroutines, ifthen-le vcr, and loops, The change of execution flow forces the program counte| «pe te pon toa new adres, The ARMVSE insuston set inches four dec fs sd to calla vou, 8 stored inthe as be within approximately 32 49 are icin the epsr. Whe nb bi instructions st 7, races are used 10 change execution ows re [Boch nstraction encoding by wing bee 53. LOAD-STORE INSTRUCTIONS te ops tne Mp secre re ae “These instructions are’ sed for moving ‘The data t3 oe ot a ler recent dt os es Bs csire- anno sanaring each scons Symas:Bfcond>) abel [ Blsond>) i BX{econd>) Ren |. [LDR [toad word into a reise Rd-<-menilares) BLX{ceond>) label Rw | [stn [save tye or word om avec | Ra-> mendes) 8 [rane peal Me | [to | oad byte nto ester Ra mene) | ane wa pen label F 7 fr adress ofthe next intraton ater] | | | [STRB | save byte om ereiter a> mentees) tent e_[ bam extange ye= Rid Oxi, T= Rm & 1 [EDR [ieed baliwot nw arene ne Ie mets) o> label, T= 1 pe= Ran & Oxia, P= Ran & 1 Je adios of the éatinsirtion ae ‘BUX | traneh eehange wit nk ~Ysave balvord nt a else@ : ny, Enbeced ond Real Tine Sen] Cpa Presto en Perihral Tom | load multiple registers a) cma rion Ra apy TLDRSB | lood signed byte into a register ‘Rd <- Sign Extend Aevemmfoddress)) = (ra Mess + a) ted Ra <- Sign Extend (ersfadress)) TLDRSH | lod signed halfword into register 2532. singleresterload tore adresing modes : Fae ARM fnsouction st provides dierent modes for addesing memory. rhc incorporate one ofthe ipexing methods: peinx wih write ack, Description | start aad Ty preindex and pos inde | rss | od addres | pp ‘Toble index metiods incrementater | Ra ae oe | increment betore_[ Rava wtaeits Index Method Data address | Example | renin register | decrementater [Rance [Rp samlccwin want [ema [tae otet [DR x0. (eAar | | | aan Saale =a ee [isna.n.es | |e egsssos ennai Posindox tment] [bse fet | LDR 0 rl #4 eee ee ener ates eee ee ses load multiple ison: simi, he pa pei (sing 12bitoset encoded in the instruction. “Reglter means the address is caleuated using the specific epise’s coments. ‘Sealed means the adress is ealeulted bare shit operation ata onto the stack) uses store mulipleiaseucion When using a stack you ave to die wheter he sack wil gop for down in memory. stock iether ascending (A) x descenig (| ‘Ascending stacks grove towards higher memory aeses incon descending stacks grow tovard oer memory ase, “Whan we use a ful stack (Py the wack pir sits 168 as thatthe last used or il Ioeaton (ep pons 0 he ste 0 stock), In contrat, if we wee an empty sac () the sp i 1 teres tani he it used or my aan i is afer Ins item on the sok) ase address register and a sing the base address repister and a 2.5.3. Multiple-Regster Transfer Tadestre util instructions ea transfer multiple registers between memon andthe procesvor ina single instuction. The transfer occurs fom a base sre] register in pointing into memory. Muliple-repster transfer instructions are mer Citeient from single-reiser transfers for moving blocks of data around meémor and saving and restoring context and stacks. ‘Syntax: {) SWE number vt | software interrupe "$e addres ofinseand SP sve par Porvector +08 pst mede= sve (asi RQ interes) 1255. PROGRAM STATUS REGISTER INSTRUCTIONS ||) te ARM instruction set provides two inn | program status resister (por). The MRS insrucian tances te cence | ier tener o sp into aes. Inthe revere det te MGR tr ees Saracen tee ‘Syntax: MRS () Ré,epsrspar= “| mse () ) } Rd.R {Ro} Pelds | PapsI24301 Sue 1629 enerson 9) Com 'SWP | swapa word between memory and aegis | tmp mem32{R] en a smem32{Rq] Ren Le Ida ae Ra= ump ‘wap a bye between memory anda register | tmp = mem8{Rn} meme] = Rin Fig. 26 putt Rd= tmp MRS [copy program status register to «| RE per ‘Swap cannot be iteroped by any ter instruction or anyother bus access. We general-purpose register sy th system “holds the bus” unl he anasto is complete, MSR | move a general-purpose reise to | pel] =m '25.4, SOMWAREINTERRUPT INSTRUCTION ‘A software inept instution ($WH) causes a software interrupt exception, which provides mechanism for application to cal operating system routines. rogram statu register ‘move an immediate piel] = immediate Program stats registerFra nt RealTime Sten] 255. Coprocessor instructions ‘esd to ester the instruction set CoproeeSsor can nna provide nigel computsion caabiliyo¢ B= wsed 0 cant the can Chet epntem icing caches and memory management, The coprocessor i Mrocceng reyister transfer, an memory tansy CCoprosesor introns ste insttions Hostage data inerstons ‘Syntax: CDP{} cp, apsodel, C2, Cn (oped) “MIRCIMCR>{-] { ep, C8, addressing “CoP | copmeesor dhs proceising perform an opéation ins coprocessor MRC NCR we coprocessor rite ranser—move dati tofiom coprocessor registers Toad and store blocks @f memory 255.2. Coprocessor35 Instruction Syntax (CPAS is called the system control coprocessor. Both MRC and MCR| nsinetons are used to read and write to CPIS, where register Ra isthe core denination rites, Cis the pimary register, Cris the secondary’ register, opcode? is a secondary register modifier. We may occasionally have secondary register ealed “extended reste.” 2.6. STACKS AND SUBROUTINES ‘A subroutine is reusable program module. Amin program ean cal or jump the subroutine dae ot mare ines. The sack is used in several ways when subroutines ae called In his se we wil eam about ‘& How tote subroutines and ell them fom the main program. | Ways to pas parameters to and fom subroutines “© The function ofthe tack andthe stack pointer, ca roc en Pripirae a ‘How (create and se stn gag : ofan delay A avon PrN mde te Frequent the subrooine ict by epg a 8 OF cling ald, progam contol is transfered from the mag oO © Ubon i hen the subroutine Snishesexceuting, consis eo Sebo re sack provides the means of connecting the sumone oe a roa, bs. STACK stack is actually just an area of ee Aes memory whore i xia. For this reason, register RIS is refered to so he mk se ese "0 the stack pointer (SP), Make the stack and the stack pine. The ‘hack is an area of memory the stock pointers ltr isthe addres ofthe last valve pushed onto the stack. ns @ @ Fle. 27, Pate and sack analogy 10 compute steck operation (hen rom ‘AMbrocomputeregicering bile)ess erase sn cae armel tien anomie am ia ieee some plates. Si mfp ca Per ape parca emer fe et ep of Ge sk. Fg) an (0 sre is Pernt Seco mcasac etree you consider te usage of the Pines, ju ie tht the lst plate pa nto the ates remaved fom he ack Thus the rack a st in rst out ora io eevee, Te sack operates in exact same waynes itis also refered ts 1 Fo don arose. The push inacons fst decrement he stack pine by Score sd hen soe ope 80 byes f data othe tack Conse wat pens if register SP cots the adress 012000 00FF aid the iter RO cnsns he vale Ox6B. Exeaing the aston PUSH (RO} fs cements he sack pin by oe, 99 reper SP is now Ox2000.0FE. and pues he value 0x ont th sack t memory locaton 0x2000.00FE. The POP {RO} intron st pts te contents ofthe top of sck into the RO register and ten nrementthe ck pointer yon. “hea ing you vil be wig the ack fr is ving dia when subst is cle Fer exp, one your min program ss reptersRO-RS, You cll browne tht i going to ele some vale and pass i back to the main ropa. Aer yo el he sou, ou an just pus al he data onthe tack Fete exc any nsrucons ine bowtie The subroutine ten we alte ese internal use and store the data a te sin program news in oe ofthe memaryJoeations. At the end of te pus fa INE MSTRUCTONS GO HERE foray La bor Por ft : Por faa l242. CALLING A SUBROUTINE You witl reall, the program counter, o register PC (RIS), lvays contains the sss ofthe next instruction to be executed ina pogram.Caling asst i |nlar to an unconditional branch the program jumps to a diferent addres ster than the next address. The difference is tht when the subroutine finishes -resuing, contol gots back to the instruction afer he subroutine cll inthe sin peer. : | ADL insircton causes the address ofthe next memory istrstion tobe pushed onto R14 (Link Repister or LR) and the argument of BL. 1 be loaded ino the _|Pbmm counter. The argument of BL isthe staring adress of the subroutine. Bu, [se yu write your program, you just give ita name andthe assembler Figures ou [fet Attend of a ubrouting hinson BX LR aes wh va I {tein LR to be loaded into the program su. _ | this way, the instruction after the BL. in the main program is the next oxe| | Note that if the value of register LR is changed within your subroutine‘nbeed ad Real Te Sten] =a . —_——_—— (ce, ty cling Ouse o Inch eis LR nut be sverestored onthe sack ee ey preserve Ke vale. In gsneral itis a good habit to use instrtions poh (LR} and pop (LR) atthe beginning and end of ech evbroutins, 2, PARAMETER PASSING ee aes ped he mbrouine byleving he an nse, aan aag he ous oe A pence is aed tk 1 he ep nnvng he tino cg te da Ti he yy ower we psn zeny es is pean tig sed he route fin lt, his co eect synate tiger of sig prance. The tan ee tes ped eon ths cle ally fc, iegenmtogocmen alent pment 2.64, SOFTWARE DELAYS ‘One way of resin a spesfe delay isto wrt subrouin hat contains Lop, -te in the lop takes to execute canbe calculated by ang up the total number of elk eyes inthe loop and mutpyig this bythe period, T, of one clockeyete This isthe inverse ofthe clack frequency. The numberof times the lop exesies| can be adjusted to create diferent delay, This loop counter canbe passed tothe subroutine soit an be used for different length delays 2; Subroutine creat dey, 3 $DELAY_CLOCKSIs he counter whichis 5; decremented to 20 gy preteen I 6 Daley LOR Ra, = DELAY CLOCKS Set dolay ost 7 eal suas Re, m2, #1 < :oeremant count ° BNE cel =n at z10, do again ° ax OR tum when done Fig, 2 Subrowine implement software dea oop conning 1 oop igor consis OF OR 109. The fy Phas to insur js wet | lock eel and BNE is 3 tions, SUBS and BNE. i Bocce {0 SUBS adn MM ap nea Sine lope vt eo gla forthe eat DT. whee T isthe coc penn Tr This gives a| eens oms We RVG N= 1 fora dey of 7 Snes Ee ny ste shore dy spent BS 8 yf = ns. The max valve For N she Ingest iy na a BRS kin delay of (t4204.967295) x 62.508= 107.745 179 miner {fa longer delay is needed, an outer lop is adjeg ener ae st 1 0 otherwise he subroutine wil ge Make sue that ne of te into init oop, 27, FEATURES OF THE LPC 214 X FAMILY 6 soca sitaManG nicmninain tw Ge TIS euTIDMS CPU wit resin emerson ET a mente i ce el fo 2 KD SI2KD. A T2Ri wide memory ces ants ce ee [ct cae 251 cote atte nonmmeren [ree cade sae peo, he ahenaive 16 Tht ote me yr an 309 wh nina proraner ey, De eo Eview power cosuncon, LPCZIIAZ NGM ae eae cee Bete ec hey recuse sm te pra a ses commnicon ins ging fom 8 USB 20 Pp ei nt UAT, SP, SSP to Cb onl oncp SRAM 84D ep 030 ee devices very wll sie er commie gays a poe fever son monn, vie reaping, poi bo rt ie na igh roses owe ||. Yarious 32-bit timers, single or diol 10-8it ADC(S, 10-bit DAC, PWM! _ flames and 45 fast GPIO ince wih upto nine ede or level seve exe