Ch-1 Microcontroller 8051: basics

1.1 Introduction
Microcontroller stands for a Controller which is of Micro size.
Microcontroller works on digital signals in bit level to control some process, i.e., a collection of
job/ tasks designed to meet certain objectives in the form of certain outputs. A microcontroller’s
size is small compared to its enormous capacity.
1.2 Evolution of Relevant Technology
It all started with General Purpose Microprocessors followed by Bit-Slice Processor. Later Special
purpose Processors like Digital signal processors and Microcontrollers were developed.
A General Purpose Microprocessor is an open-ended processor which is generic in nature to suit in
variety of applications. An additional set of hardware makes it complete and useful for physical
applications. In a bit slice processor a group of hardware and software instruction sets comes as
SLICE and one such SLICE can be connected to an existing one to enhance functionality. Special
purpose processors come with certain facilities that are introduced into a single-chip for dedicated
application. Each of these chips is self-sufficient to suit certain applications and needs hardware
for expanding functionality.
A DSP (Digital Signal Processor) is used for high speed extensive computation required in signal
processing. A microcontroller is used for special-purpose signal processing and has built-in blocks
for interfacing with external world. Application examples of microcontroller are Microwave Oven,
washing machine, sewing machine, auto ignition system, smart toys, smart DVD players, different
controllers in automobiles etc.
1.3 Generalized Architecture

Microprocessor Microcontroller

1.4 Differences between Microprocessor and Microcontroller

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Microprocessor is utilized for general purpose use whereas microcontroller is used for special
purpose signal processing. Microprocessor has no internal memory (ROM for code, RAM for
data), I/O interfacing system, timers whereas microcontroller has all these. Microprocessor needs
to be interfaced with external memory, I/O interfacing system, timers. Ratings of these
components can be selected based on use. Microcontroller has internal memory, timers etc of
fixed ratings and used for specific purposes only. Microprocessor is used for variety of
applications and accordingly ratings RAM, ROM, Timers, I/O interfacing chips are selected.
Microcontrollers are specially designed for specific purpose use only and ratings of internal
functionalities are accordingly decided. A microprocessor is a basic block for microcontroller
itself, while the latter contains few more functionalities in a single chip along with the basic
microprocessor or CPU.

Real picture of microcontroller with chip and oscillator labeled

1.5 Basic Block Diagram of 8051

In 1981, Intel Corporation introduced an 8-bit microcontroller called the 8051. This
microcontroller has 128 bytes of on-chip RAM, 4K bytes of on-chip ROM, two timers, one serial
port and four ports all on a single chip. The 8051 is an 8-bit processor as its CPU can work only
on 8 bits of data at a time. Data larger than 8 bits have to be broken into 8-bit pieces to be
processed by the CPU.

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Although the 8051 can have a maximum of 64K bytes of on-chip ROM, many manufacturers have
put only 4K bytes on the chip.
CPU contains ALU and Control units. ALU is responsible for carrying out Arithmetic and logical
operations. Four I/O ports P0, P1, P2, P3 each has 8-bits. P2 is dedicated address bus, while P0
contains AD0 to AD7 bits and hence can be used as both address and data bus. This is done to
reduce number of pins. P1 and P3 are dedicated data ports. All the four ports work by default as
output port. A port is configured as input port by sending 1 to each pin of that port. TxD and RxD
are serial pins, used for serial data transmission and reception. EA (External Access) becomes 0/1
while accessing external/ internal memory (both RAM and ROM) respectively. PSEN (Program
store Enable) becomes 0 while accessing external code memory (ROM). ALE (Address Latch
Enable) becomes 1 while it contains address bits in AD 0-AD7 and becomes 0 when it contains data
bits there. This signal is used to demultiplex the address and data bus.
Address bus size is 16 bit and the corresponding pins are A 15-A0. Data bus size is 8 bit and the
corresponding pins are D7-D0. Size of both external data memory (RAM) and code memory
(ROM) that can be interfaced with 8081 is 64KB as the chip has 16 bit address bus (16 address
bits corresponds to 216=64K location and word size in 8051 is 8bit or 1 byte).
1.6 memory map of 8051
8051 microcontroller has 4kB internal ROM. This ROM contains 4k words each of one byte or 8
bit capacity. The range of address location is 0000H to 0FFFH (i.e., 0 to 4096 or 4X1024 in
decimal). The chip has 128 byte internal RAM. Hence the range of address location is 00H-7FH.
This contains 4 register banks (byte addressable only), 16 memory locations which are both bit
and byte addressable and general stack space. A total 16 number of internal special function
registers, also known as SFRs, are there in 8051 in a manner similar to internal RAM.

Internal RAM space

00h-1Fh byte locations refer to four register banks (banks 0 to 3), each of 8 byte size, as shown
above. This portion is only byte addressable. 20H-2FH contains a total of 16 byte locations, each
of which are bit addressable.

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 Detailed bit-addresses for byte locations 20H-2FH

8 bit-level addresses for byte location 20h

Hence these 16 byte locations each have 8 bit addressable locations within as shown above in.
SFRs are the memory area that controls specific functionality of 8051 processor. In the range 80h
– FFh, only 21 memories are occupied by SFRs, rests are physically non-existent. These SFRs are
accessed either by their name, or by their byte – address. The table below shows the details of
SFRs.
Name Function/Description Byte Whether Bit-
Address Addressable
B Arithmetic F0H Yes
A/ACC Accumulator E0H Yes
PSW Program Status Word D0H Yes
IP Interrupt Priority B8H Yes
P3 I/O Port Latch B0H Yes
IE Interrupt Enable A8H Yes
P2 I/O Port Latch A0H Yes
SBUF Serial Port Data Buffer 99H No
SCON Serial Port Control 98H Yes
TH1 Timer-1 High Byte 8DH No
TH0 Timer-0 High Byte 8CH No
TL1 Timer-1 Low Byte 8BH No
TL0 Timer-0 Low Byte 8AH No
TMOD Timer/Counter Mode Control 89H No
TCON Timer/ Counter Control 88H Yes
PCON Power Control 87H No
DPH Addressing External Memory 83H No
DPL Addressing External Memory 82H No
SP Stack Pointer 81H No
P1 I/O Port Latch 90H Yes
P0 I/O Port Latch 80H Yes

The left side picture shows the bit level

diagram of PSW. (D4, D3) is used to select
the register bank as following:
(0, 0): select bank-0

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(0, 1): select bank-1
(1, 0): select bank-2
(1, 1): select bank-3
The two 16 bit registers in 8051 are Program Counter (PC) and Data Pointer (DPTR).
1.7 Oscillator waveform
Pulse train generated by the oscillator is as shown below.

One state (S) = One Phase -1 half (P1) + One Phase -2 half (P2).
One Machine Cycle (M) = 6 states (numbered S1 through S6).
One Machine Cycle (M) = 12 Clock Cycles. One Machine Cycle (M) = 12 / Clock Frequency
Two most common oscillator frequencies in 8051 are 12 MHz and 11.0592 MHz.

Ch-2 addressing modes in 8051

2.1 Introduction
The CPU can access data in various ways. The data could be in a register, or in a memory, or be
provided as an immediate value. These various ways of accessing data are called addressing
modes. In this chapter we discuss 8051 addressing modes with some examples.
The five main addressing modes are immediate addressing, Register addressing, direct addressing,
Register Indirect addressing and indexed addressing. Most of these have applications in both data
transfer instructions and arithmetic instructions.
2.2 Immediate addressing Mode
Data, which is a part of the instruction, is directly loaded into the register or memory location in
case of immediate addressing. Application examples of data transfer instructions are as below.
MOV A, #2Ah A<< 2Ah Value 2Ah is moved to A
MOV A, #0D6h A<< D6h If starting character is within A-F, start with 0
MOV DPTR, #8B9Ch DPTR<< 8B9Ch
MOV R2, #0EAh R2<< EAh Value EAh is moved to R2

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Instructions MOV A, MOV DPTR, MOV R2 are called Mnemonics. Their equivalent Hex-codes
are called Opcodes. Examples of immediate addressing in arithmetic operation are given below.
ADD A, #08h A<< A+08h Value 08h is added to A and result is stored in
A
ADDC A, #08h A<< A+08h+C Value 08h is added to A along with Carry and
result is stored in A
SUBB A, #0B1h A<< A-B1h-C Value B1h is subtracted from A along with
carry and result is stored in A

2.3 Register addressing Mode

Register names are used as part of mnemonic. This register may be a general purpose one (R 0-R7)
or may be an SFR. Examples of register addressing in data transfer operation are given below.
Accumulator will be one register in these instructions.
MOV A, R6 A<< R6 Data is moved from R6 register to A
MOV R2, A R2<< A
Examples of register addressing in arithmetic operation are given below. Accumulator will be a
part of instruction here.
ADD A, R3 A<< A+R3 Content of Register R3 is added to A and
result is stored in A
ADDC A, R3 A<< A+R3+C Content of Register R3 is added to A along
with Carry and result is stored in A
SUBB A, R4 A<< A-R4-C

2.4 direct addressing Mode

All of the 128 byte of internal RAM and the SFRs may be addressed directly using the appropriate
single-byte address. When address is less than 80h, it is a valid memory location. For addresses
80h onwards, SFRs are addressed.
Data transfer examples for direct addressing are shown below.
MOV 5Ch, A M5C<< A Data at A is moved to the memory location 5C
MOV 99h, #46h M99<< 46h Value 46h is moved to
MOV R0, 12h R0<< M12 Data moved from location 12h to R0 register
Here R0 is of bank-0 by default. In fact, here addressing is mixed in nature, as both register
addressing and direct addressing is there.
MOV 00h, 12h M00 << M12
Here 00h is the absolute address of R0 of bank-0. Hence address may be called its name as well as
by its address.
MOV 99h, A M99 << A

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Evidently the address 99h (greater than 80h) refers to the SFR SBUF. Thus, it is equivalent to
write: MOV SBUF, A : Register addressing.
Arithmetic operation examples for direct addressing are shown below. Accumulator will be part of
instruction here.
ADD A, 4Eh A<< A+M4E Data from location 4E is added to A and
result is stored in A
ADDC A, 4Eh A<< A+ M4E +C Data from location 4E is added to A along
with Carry and result is stored in A
SUBB A, 4Eh A<< A- M4E -C Data from location 4E is borrowed from A
along with Carry and result is stored in A

2.5 Indirect addressing Mode

The indirect addressing mode uses a register. Content of this register is the address of a memory.
Data transfer examples for indirect addressing are shown below.
MOV @R1, #2Ah MR1<< 2Ah Value 2Ah is moved to the memory location
pointed by (/contained in) R1
MOV @R1, 4Fh MR1<< M4F Content of location 4Fh is moved to memory
location pointed by R1 (ex-34H)
MOV A, @R1 A<< MR1 Content of memory location pointed by R1 is
moved to A
MOV @R0, D0h MR0<< MD0 MR0<< PSW

Indirect addressing must NOT refer to any SFR. Hence the below set of instructions are not valid.
MOV R1, #D0h
MOV @R1, #23h
First line makes R1 to point to PSW (an SFR). Now we can’t send any value (say, 23h for
example) to PSW by addressing R1 indirectly.
Also only R0 and R1 are used in indirect addressing.
Arithmetic operation examples for indirect addressing are shown below.
ADD A, @R0 A<< A+MR0 Data from location pointed by R0 is added to
A and result is stored in A
ADDC A, @R0 A<< A+ MR0 +C Data from location pointed by R0 is added to
A along with carry and result is stored in A
SUBB A, @R0 A<< A- MR0 -C Data from location referenced by R0 is
borrowed from A along with Carry and result
is stored in A

2.6 Indexed addressing Mode

In this mode the 16-bit address in a base register is added to a positive offset to form an effective
address for jump instruction. The base Register in the jump instruction is the data pointer and the
positive offset is held in the accumulator. For the move instructions, the base register can either be

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the data pointer or the program counter. The positive offset is in the accumulator. Few examples
of this type are shown below.
JMP @A+DPTR
MOVC A,@A-DPTR
MOVC A,@A+PC
2.7 Relative addressing Mode
Sometimes this is also called program counter relative addressing. This addressing mode is used
only with certain jump instructions. A relative address (or offset) is an 8-bit signed value, which is
added to the program counter to form the address of the next instruction executed. An example of
this type is shown below.
JZ rel_addr
Two more types of addressing are there in 8085. Absolute addressing mode has only two
instructions ACALL (absolute call) and AJMP (absolute jump). Long addressing mode also has
two instructions LCALL addr16 and LJMP addr16.

Ch-3 Instructions in 8051

3.1 Introduction
We have already seen various data transfer and arithmetic instructions and their uses while
discussing various addressing modes of 8051. More applications of the above and other types of
instructions will be discussed one after the other in this chapter.
3.2 external data moves
MOVX @DPTR, A MDPTR<< A DPTR holds 16 – bit address
MOVX A, @DPTR A << MDPTR DPTR holds 16 – bit address
MOVX A, @R0 A<< MR0 8 – bit address
MOVX @R0, A MR0<< A 8 – bit address
All external data moves must involve Accumulator. R0 or R1 can address 256 bytes, whereas
DPTR can address 64K bytes. MOVX is normally used with external RAM or I/O addresses.
There are two sets of RAM addresses between 00h and FFh – one internal, and another external. –
selected by the particular type of instruction used and by the status of EA pin (=0 for external data
moves) as well.
3.3 external Code-memory (read-only) data moves
MOVC A, @A+DPTR A<< MDPTR+A Offset is in A and relative address is in DPTR
MOVC A, @PC PC<<PC+1 PC is incremented first. Offset is in A and
A<< MPC+A relative address is in PC.

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These instructions will work when the pins EA and PSEN both holds value=0.
3.4 data exchange
XCH A, R5 A <->R5 Exchange A with R5
XCH A, 0F3h A <->MF3 Exchange A with content of location F3h
XCH A,@R1 A<->MR1 Exchange A with the content of location
pointed by R1
XCHD A,@R0 Exchange lower nibble of A with lower nibble
of MR0. Upper nibbles remain unaffected.
SWAP A Exchange upper nibble of A with lower nibble
of A
3.5 Stack memory and relevant instructions
This is a memory area where data is transferred on LIFO (Last – In First
- Out) basis. While storing data, Stack Pointer (SP) is incremented first.
Then data is stored into memory. And while reading data, data is read
from memory first. Then SP is decremented. This SP holds address of
Stack Memory.

Example-1: PUSH

MOV 81h, #38h SP<< 38h

PUSH 09h SP<< SP+1
MSP<< M09h
Here the value 38h is sent to the Stack pointer (Memory location 81h in RAM). Now PUSH
instruction does two functions. First, it increments the SP, which now points to 39h. Then data
from location 09h is sent to the location pointed by SP (, i.e., 39h). Hence effectively data moves
from location 09h to location 39h.
Example-2: POP

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 MOV 81h, #39h SP<< 39h
POP 08h M08h <<MSP /M39H
SP<< SP-1
Here the value 39h is first sent to the Stack pointer. Now POP instruction does two functions.
First, data from the location pointed by SP (, i.e., 39h,) is sent to 08h. Then SP is decremented
making it to point 38h henceforth.
SP is set to 07H when 8051 is reset. This is R7 of bank – 0. The first push Opcode would write
data to R0 of bank – 1. SP should be initialized to an internal RAM address likely to be used in the
program. SP must not hold address beyond 7Fh, the maximum address of internal RAM. The
direct addresses will be used for R0 – R7, not their names, as the stack memory does not know
which memory is in use.
3.6 multiplication & division
(1) Multiplication:
MUL AB B A<<A*B
There should not be any space or comma between A and B in the instruction. Higher and lower
bytes of the result are stored in B and A respectively. If the result is fitted within one byte (i.e.,
less than FFh), B=00h and OV = 0. Else OV will be set. Carry flag is always cleared to zero.
Example-1
MOV A, #7Bh A<< 7Bh
MOV 0F0H, #02h B << 02h Same as MOV B, #02h
MUL AB A<< F6h, B<< 00h, OV<< 0
00F6h

Example-2
MOV A, #7Bh A<< 7Bh
MOV 0F0H, #0FEh B << FEh Same as MOV B, #0FEh
MUL AB A<< 0Ah, B<< 7Ah, OV<< 1
7A0Ah
(2) Division:
DIV AB B A<< A/B
There should not be any space or comma between A and B in the instruction. A holds the quotient
and B holds the remainder.
Division by zero yields undefined result in A and B, and OV = 1.
3.7 Logical operations
3.7.1 Byte level logical operations
3.7.1.1 Rotate Operations: Work only on A
(i) RL A: Rotate the Accumulator left by single field

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(ii) RLC A: Rotate the Accumulator left by single field with carry

Rotate left by single – field means

multiplication by 2, provided there is
zero-filling from right side and no ‘1’
is lost after shifting.

(iii) RR A: Rotate the Accumulator right by single field

(iv) RRC A: Rotate the Accumulator right by single field with carry

Rotate right by single – field means division by 2, provided there is zero-filling from left side and
no ‘1’ is lost after shifting.
3.7.1.2 AND Operation
ANL A, #7Bh A<< A and 7Bh ANL=AND Logical
ANL A, 7Bh A<< A and M7B
ANL 7Bh, A M7B << A and M7B
ANL A, Ri A << A and Ri, Ɐi = 0(1)7
ANL A, @Ri A << A and MRi, i=1,2
ANL 7B, #7Bh M7B << M7B and 7Bh

3.7.1.3 OR Operation
ORL A, #7Bh A<< A or 7Bh ORL=OR Logical
ORL A, 7Bh A<< A or M7B
ORL 7Bh, A M7B << A or M7B
ORL A, Ri A << A or Ri, Ɐi = 0(1)7
ORL A, @Ri A << A or MRi, i=1,2
ORL 7B, #7Bh M7B << M7B or 7Bh

3.7.1.4 XOR Operation

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 XRL A, #7Bh A<< A xor 7Bh XRL=XOR Logical
XRL A, 7Bh A<< A xor M7B
XRL 7Bh, A M7B << A xor M7B
XRL A, Ri A << A xor Ri, Ɐi = 0(1)7
XRL A, @Ri A << A xor MRi, i=1,2
XRL 7B, #7Bh M7B << M7B xor 7Bh

3.7.1.5 Other Operations

CLR A Clear Accumulator
CLR 7Bh Clear the Memory location 7Bh
CLR Ri Clear the content Register Ri
CLR @Ri Clear the memory location referenced by Ri

Though the above set of examples work on byte addressable locations (Accumulator /Register),
logical and/or/xor operations are carried out in a bit-wise fashion internally, i.e. , for each bit
location (say, D0-D7 ) logical operations are carried out separately resulting a single bit output for
that location.
No flag is affected unless the direct address refers to PSW in all the above three operations. Only
internal RAM and SFR are logically manipulated. Latch data is used in logical operation when
port is destination. Pin data is used in logical operation when port is source.
Example-1: ANL P0, A P0 << P0 and A
In this example P0 acts as both destination and source.
Now Latch does not allow port to act both ways in a single
instruction. Hence, instruction takes latch as source of data
and result, which is saved in to Latch, is called latch data.

Example-2: ANL A, P0 A<< A and P0

Latch allows port to act as input - port in a single
instruction. Hence, instruction gets data from pin, called
Pin data.

Example-3: What will be the content of the accumulator after the execution of the steps (a)
and (b) as given below in 8051?
MOV A, #98h
ORL A, #57h -----------(a)
ANL A, #34h -----------(b)
A: 98h = 1001 1000
(a) 1001 1000 = 98h=A

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 0101 0111 = 57h
A= 1101 1111 = DFh (Ans)
(b) 1101 1111 = DFh=A
0011 0100 = 34h
A= 0001 0100 = 14h (Ans)
Example-4: What will be the content of the accumulator and carry flag after execution of
steps (a) and (b) as given below in 8051?
MOV A, #2Bh
SETB C
RLC A ------------(a)
RR A ------------(b)
A: C=1, A= 2Bh = 0010 1011
(a) C=0, A= 0101 0111= 57h (left rotation involving carry).
(b) C=0, A= 1010 1011= ABh (right rotation without involving carry).

3.7.2 Bit level logical operations

Internal RAM has a portion of it as bit – addressable region. Byte addresses for that region are in
the range 20h to 2Fh.

Now, Starting bit-address of any location= (Byte-address – 20h) x 08h. This is further explained in
the table below.
Byte-Address Starting Bit-Address
20h 00h
21h 08h
22h 10h
23h 18h

(i) Example-1: Set D2, D4, D5 bit of memory location 22h.

MOV 22h, #34h

This is the byte level instruction, where MOV works on byte-
address 22h

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 SETB 12h
SETB 14h
SETB 15h

This instruction SETB sets the corresponding bit referenced by the bit-address.
(ii) Example-2: To clear D4 of Accumulator:
CLR ACC.4
ACC is used for Accumulator in bit-based instruction.
A is used for Accumulator in byte-based instruction. To clear complete Accumulator CLR A
instruction is used.

3.7.2.1 Bit level logical operations: general examples

CLR C C<<0 ,i.e., clear carry bit

CLR bit, eg, CLR 46h Clear the bit addressed by ‘bit’ (46h here)
SETB C C<<1 ,i.e., set carry bit
SETB bit, eg, SETB 46h Set the bit addressed by ‘bit’ (46h here)
CPL C Complement carry bit
CPL bit Complement the bit addressed by ‘bit’
ANL C, bit C<<C and ‘bit’
ANL C, /bit C<<C and complement of ‘bit’
Original bit does not change
ORL C, bit C<<C or ‘bit’
ORL C, /bit C<<C or complement of ‘bit’
Original bit does not change
XRL C, bit C<<C xor ‘bit’
XRL C, /bit C<<C xor complement of ‘bit’
Original bit does not change
MOV C, bit C<< bit addressed by ‘bit’
MOV bit, C bit addressed by ‘bit’<< C

MOV works with byte address with only one exception as above.
Bit level addresses as applicable to SFRs are as below:
SFR Name Byte Address Bit Address
A E0h E0h-E7h
B F0h F0h-F7h
IE A8h A8h-AFh
IP B8h B8h-BFh
P0 80h 80h-87h
P1 90h 90h-97h
P2 A0h A0-A7h
P3 B0h B0h-B7h
PSW D0h D0h-D7h
TCON 88h 88h-8Fh

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 SCON 98h 98h-9Fh

Byte – address of these SFRs = bit-address of D0 (Least Significant Bit) of these SFRs.
3.8 other operations and few comments
(i) Decimal Adjust Accumulator: DA A
It converts hexadecimal number in A into equivalent binary coded decimal number.
The conversion rule is that if Hex digit > 9, digit=digit+6.
The conversion is automatically carried out by the instruction provided. ‘DA A’ comes just after
ADD or ADDC instruction. Numbers taking part in addition previously must be within the range
0-9h. If original byte is greater 9, addition performed is a hexadecimal addition and hence ‘DA A’
instruction will not work.
(ii) Overflow Flag (OV) << C7 xor C6, where C7 means carry out of bit-D7 and C6 means carry
out of bit-D6
(iii) Carry (C) << bit from D-7
(iv) Auxiliary Carry (AC) << bit from D-3
(v) INC increments the content of a register/ DPTR, DEC increments the content of a register/
DPTR,
3.9 Program Counter & program execution in 8051
PC or program counter is 16-bit SFR. It increments automatically when program control goes to a
line of instruction and it holds the address of next instruction as shown below.

If Instruction-3 is a branching instruction, it overwrites PC with a new address during execution.

At the end of execution of instruction-3, program control goes to the address of instruction
pointed to by PC and not going to instruction-4. This is shown in the figure below.

3.10 branching instructions in 8051

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Three types of branching instructions exist in 8051. These are Relative branching, Short Absolute
branching and Long Absolute branching.
3.10.1 Relative branching
Only one byte of data (+127 to -128) need to be specified in signed format. The jump address is
calculated by adding the data byte with the present value of PC. Specifying one byte only saves
program bytes and speeds up program execution. The program using relative branching can be
located anywhere in the space of program address without re-assembling the code to generate
absolute address. That all the addresses jumped, are within a range of -128 to +127, is a
disadvantage.
Relative branching are of two types-
conditional and unconditional.
In conditional branching, content of PC is
changed by instruction conditionally and
permanently. This conditional branching is
again of two types- bit jumps and byte jumps.
In Bit jump conditional branching, jump
condition is tested on the status of a particular
bit. In Byte jump conditional branching, jump
condition is tested on the status of a particular
byte.
In the case of unconditional branching, content of PC is changed by instruction permanently.
 Relative Branching: Conditional: bit jumps:
Mnemonics Operations
JC rel_addr Jump relative if the carry flag is 1
JNC rel_addr Jump relative if the carry flag is 0
JB b, rel_addr Jump relative if the addressable bit ‘b’ is 1
JNB b, rel_addr Jump relative if the addressable bit ‘b’ is 0
JBC b, rel_addr Jump relative if the addressable bit ‘b’ is 1 and clear ‘b’ to 0.
When the bit used in a JBC instruction is a port bit, the SFR
latch for that port is read, tested and altered.
 Relative Branching: Conditional: byte jumps:
Mnemonics Operations
1. CJNE A, Compare the content of A with the content of the direct
addr, rel_addr. address ‘addr’. If they are NOT equal, then jump to rel_addr;
If A < content of addr, C = 1, else C = 0.
2. CJNE A, Comparison is with immediate byte ‘n’h, other operations
#nh, rel_addr. remaining same.
3. CJNE Ri, Comparison is between content of Ri and immediate byte
#nh, rel_addr. ‘n’h, other operations remaining same.
4. CJNE @Ri, Comparison is between content of address in Ri and
#nh, rel_addr. immediate byte ‘n’h, other operations remaining same.

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 5. DJNZ Ri, Decrement register by 1 and jump to relative address if the
rel_addr. result in Ri is not zero; No flag is affected.
6. DJNZ addr, Decrement the content of direct address by 1 and jump to
rel_addr. relative address if the result in the content is not zero; No flag
is affected.
7. JZ rel_addr. Jump to relative address if A = 0; The flags and A are not
changed.
8. JNZ rel_addr. Jump to relative address if A ≠ 0; The flags and A are not
changed.

 Relative branching: unconditional: byte jump:

Mnemonics Operations
1. SJMP jump to relative address unconditionally; No flag is affected.
rel_addr.

3.10.2 Branching subroutine

Program control goes from main program to a different address to execute a group of instructions.
After execution, control returns to the address of main program yet to be executed. Thus, content
of PC is saved temporarily in stack memory before branching to a different area. This is performed
by call instruction. It is taken back in to PC again before going to the address in main program.
This is performed by return instruction.
Demonstration of execution of call instructions:

©AnirbanM@Dept of EE, Ghatal Govt Polytechnic 17

Now new address is loaded into PC and the subroutine is executed. Hence the sequence of
operations carried out by microcontroller is as shown below.
SP << SP + 1
MSP << PCL
SP << SP + 1
MSP << PCH
PC << new address
An example of this is LCALL addr, where addr is address of the subroutine to be executed.
Demonstration of execution of return instructions:
SP is decremented again and PC regains old address in main
program yet to be executed. RET
is the instruction for return. The
sequence of operations is as
below.

PCH << MSP

SP << SP - 1
PCL << MSP
SP << SP - 1
3.11 Instructions affecting flag
Mnemonics Flags Affected
ADD C, AC, OV
ADDC C, AC, OV
ANL C, addr C
CLR C C=0
CPL C C inverted
DA A C
DIV C=0, OV
MOV C, addr C
MUL AB C=0, OV
ORL C, addr C

©AnirbanM@Dept of EE, Ghatal Govt Polytechnic 18

 RLC A C
RRC A C
SETB C C=1
SUBB C, AC,OV
CJNE C

 parallel ports in 8051

All the four ports P0-P3 are by default output ports. A port pin is configured as an input pin by
sending 1 to it and a complete port is configured as input port by sending FFh to it. Likewise, a
complete port or a pin can be configured as output by sending 00h or 0 respectively. Pins of port
P3 have alternate functions as shown below.
P3 Bit Function Pin
P3.0 RxD 10 Serial Communications
P3.1 TxD 11
P3.2 INT0 12 Communications
External
P3.3 INT1 13 Interrupts
P3.4 T0 14 Timers
P3.5 T1 15
P3.6 WR 16 Read/Write signals for
P3.7 RD 17 external memories

CH-4 Programming in 8051

4.1 Introduction
Input file written in mnemonics has an
extension .asm. The assembler creates the *.obj
intermediate file, *.hex output file for processing
and *.lst file containing detailed information.

4.2 Assembler Directives

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Assembler directives are pseudo instructions. Assembler is guided by the directives regarding its
role that it has to do next with the mnemonics.
#1. ORG addr Originate the subsequent code starting at address ‘addr’
Example
ORG 0400h
MOV R2, #06h
This is same as the program written in hex code below-

#2. num EQU 28h ‘num’ is just a name used for 28h. It is NOT a memory where 28h
is stored
Examples
numx EQU 3Bh hex format
numx EQU 00111011b binary format
numx EQU 59 decimal format
numx EQU 59d decimal format
#3. ALE92: DB 3Ah the data 3Ah is stored in address labeled as ALE92
Examples
ALE92: DB 3Ah hex data stored in label ALE92
ALE92: DB 58 decimal data stored in label ALE92
ALE92: DB 58d decimal data stored in label ALE92
ALE92: DB 01011011b binary data stored in label ALE92
ALE92: DB 3Ah, 40h, 2Ch, 0C1h 4 data stored in consecutive memory locations
in the form of an array, address being started from ALE92
ALE92: DB “hello” 5 ASCII data stored in consecutive memory
locations in the form of an array, address being started from ALE92
#4. ALE92: DW 0D43Ah the data 3Ah is stored in address labeled as
ALE92, and the data D4h is stored in address labeled as ALE92+1
#5. END/.END last line of source file (*.asm)
Assembly level program must be sequentially written, while assembler directives need not be
sequential.
4.3 Programming examples
1. Write a program to add two 16-bit numbers. The numbers are 2E5Fh and A3B4h. Store
the sum in R7 (higher byte), R6 (lower byte), R5 (carry).

©AnirbanM@Dept of EE, Ghatal Govt Polytechnic 20

LOWNUM1 EQU 5Fh lower byte of number 1
LOWNUM2 EQU B4h lower byte of number 2
HIGHNUM1 EQU 2Eh higher byte of number 1
HIGHNUM2 EQU A3h higher byte of number 2
ORG 0000h
CLR C
MOV R5, #00h R5<< 00h
MOV A, #LOWNUM1 A<< lower byte of number 1
ADD A, #LOWNUM2 A<< A+ lower byte of number 2
MOV R6, A R6<< lower byte of result
MOV A, #HIGHNUM1 A<< higher byte of number 1
ADDC A, #HIGHNUM2 A<< A+ higher byte of number 2+ C
JNC NEXT
INC R5 R5<< carry generated in second addition
NEXT: MOV R7, A R7<< Higher byte of result
END

2. Write a program to get hex data in the range 00-FFh from port-0 and convert it to
decimal. Save the digits in R5, R6, R7(LSB).
Illustration:
1) Let input hex data=DAh is available from port-0
Decimal equivalent of the number=13x16+10=218.
2) Using instruction DIV AB, Divide 218 by 10.
Here quotient=A=21 and remainder=B=8.
3) Store B in R7.
4) Again divide A (=21) by 10.
At this, A=quotient=2, B=remainder=1.
5) Store B in R6.
6) Finally Store A in R5.
Program:
PORTHIGH EQU 0FFh
DECRADIX EQU 10d decimal 10
ORG 0000h
MOV P0, #PORTHIGH configure P0 as input port
MOV B, #DECRADIX
MOV A, P0
DIV AB divide by decimal 10
MOV R7, B save lower digit in R7
MOV B, #DECRADIX
DIV AB divide by decimal 10
MOV R6, B save middle digit in R6
©AnirbanM@Dept of EE, Ghatal Govt Polytechnic 21
MOV R5, A save higher digit in R5
END

3. Write a program to subtract two 8 bit numbers.

LOWNUM EQU 5Fh
HIGHNUM EQU 2Eh
ORG 0000h
MOV R5, #00h
CLR C
MOV A, #HIGHNUM A<< number 1
SUBB A, #LOWNUM A<< A-number 2-C(=00H)
MOV R6, A R6<<Result
JNC NEXT
INC R5 R5<<borrow generated
NEXT: END

4. Write a program to multiply 2 8 bit numbers.

LOWNUM EQU 5Fh
HIGHNUM EQU 2Eh
ORG 0000h
CLR C
MOV A, #HIGHNUM
MOV B, #LOWNUM
MUL AB
MOV R6, A
MOV R5, B
END
5. Write a piece of program to Switch from bank0 to bank3.
SETB PSW.3
SETB PSW.4
6. Write a program to generate time delay.

©AnirbanM@Dept of EE, Ghatal Govt Polytechnic 22

 D MOV
LO
EL MOV
R3,#N3
LO
O MOV
R2,#N2
TA
A DJNZ 2 (1+2
O R1,#N1
P2
KE
Y:
DJNZ
R1,
DJNZ N N1+2{1+(1+2N
P1
:: R2,
TAKE
R3, 1 )N2 1+2)N2+2
: LOOP1
LOOP2 m/c }N3 m/c
m
/
c
Machine cycles required for the instructions MOV Ri, #N and DJNZ Ri, Label are 1 and 2
respectively.
⸫ Total machine cycles required for the above program is 1+ {3+ (3+2N1) N2} N3.
⸫ Maximum machine cycles = 1+ {3+ (3+2 x 255) x 255} x 255
= 3, 33, 58, 591
Now, each machine cycle =12 clock cycles
=12x (1/clock freq.)
=12x (1/11.0592MHz)
=12x (1/11.0592) micro-sec.
=1.085 micro-sec.
⸫Total delay generated= 33358591 x 1.085 micro-sec
= 36.196 sec.
Selecting N1=22, N2=15, N3= 13,
Time delay generated = [1+ {3+ (3+2 x 22) x 15} x 13] x 12 x (1/11.0592) x 10-6
=9.99 msec

7. BCD to HEX Conversion:

MOV R0, #20h location of the BCD data
MOV A, @R0 copy input data to accumulator
MOV R2, A keep a copy of data at R2
SWAP A swap the higher and lower nibble of data
ANL A, #0Fh keep only the lower nibble (higher nibble of original data) at A
MOV B, 0Ah keep decimal 10 at SFR B
MUL AB multiply A with B (decimal 10)
MOV R3, A store the result into register R3
MOV A, R2 bring the original data at accumulator
ANL A, #0Fh keep only the lower nibble of original data at A

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ADD A, R3 add value of R3 into accumulator
MOV R0, #30h location of storage of HEX data
MOV @R0, A store output data
END
Conversion between HEX and ASCII, sorting, maximum/minimum number: EXERCISE for
STUDENTS.

CH-5 timer & Counter in 8051

5.1 Introduction
In-built timer/ counter functionality are not there in microprocessor. A distinct advantage of
timer/counter in 8051 is their ability to run in the background even when the microcontroller
remains busy in program execution. Timer counts up at each machine cycle (i.e., after 12 clock
cycle) or at external pulse. Two timers are there in 8051, namely timer-0 and timer-1. Mode of
timer operation can be set through TMOD SFR. Timers
increment from an initial value, called initial count.
Initial Count is stored either in TL, or in TH, or in both,
depending on the timer-mode selected. Timer operation starts when TR0 or TR1 bit in TCON is
set by programmer to 1. When the timer overflows, i.e., when the timer/ counter rolls back from
the highest value (=2n for an n-bit counter) to zero, TF0 or TF1 bit in TCON is set to 1. To restart
the timer/counter, both TF0 (or TF1) and TR0 (or TR1) are to be cleared.
5.2 tmod and tcon SFR
SFR TMOD (89h)
Bit combinations and description for each mode
of timers are given in the table below.

M1 M0 Mode Description
0 0 0 13- bit timer
0 1 1 16-bit timer
1 0 2 8-bit auto reload
mode
1 1 3 Split timer mode

©AnirbanM@Dept of EE, Ghatal Govt Polytechnic 24

SFR TCON (88h)
Here, TR-1 and TR-0 bits are set to start Timer-
1 and Timer-0 respectively. On the other hand,
TF-1 and TF-0 are overflow flags for Timer-1
and Timer-0 respectively.
5.3 Timer modes in 8051
(i) Mode 0: 13-bit Timer Mode:
This mode is no longer used in new development and it is compatible with its predecessor, the
8048. In this mode the count stops at 2 13-1 = 8191, and hence the total count is 8192. In this mode
after the overflow occurs (i.e. after the TF0/TF1 bit is set), to go on continuing operation of timer/
counter, the TH0 and TH1 registers are to be loaded with initial count (IC) value after clearing the
TF0/TF1 and TR1/TR0 bit.
(ii) Mode 1: 16-bit Timer Mode:
In this mode the count stops at 216-1 = 65535, and hence the total count is 65536. In this mode also
after the overflow occurs (i.e. after the TF0/TF1 bit is set), to go on continuing operation of timer/
counter, the TH0 and TH1 registers are to be loaded with initial count (IC) value after clearing the
TF0/TF1 and TR1/TR0 bit.
Here, number of machine cycle= 65536-Initial Count (IC), where IC = TH x 256+TL
12
T d= ×no . of machine cycles
clock frequency
Hence time delay generated with this IC, =
12
× ( 65 ,536−IC )
f

(iii) Mode 2: 8-bit Timer Mode:

In this mode the counter counts 8 bit. Hence, the maximum count value is 2 8-1=255 and the total
count is 256. In this mode only the TL0/TL1 works as the counter and the value of IC remains
stored in the TH0/TH1 SFR. Every time overflow occurs, unlike the previous two modes, there is
no requirement to reload the IC value in the TH0/TH1 and TL0/TL1. Here the value of IC from
TH0/TH1 gets automatically loaded into the corresponding TR0/TR1 and to continue operation of
timer/counter, we only need to clear and set the appropriate bits as done in previous two modes.
(iv) Mode 3: Split Timer Mode:

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In this mode, only Timer-0 is used by splitting into two separate modes. Here TL0 SFR is used as
the new timer-0 .TR0 is used to start/stop this timer and the TF0 work as the corresponding timer
overflow flag. Here TH0 SFR is used as the new timer-1 .TR1 is used to start/stop this timer and
the TF0 work as the corresponding timer overflow flag.
5.4 Timer Programming in 8051
The steps to write a timer program is following:
(i) Select Timer-0 / Timer-1,
(ii) Decide whether Timer runs on internal machine cycle (as Timer) or on external clock cycle at
appropriate pin (as counter),
(iii) Accordingly set / reset GATE & C/T bits of SFR TMOD,
(iv) Select Timer mode through TMOD,
(v) Set Initial Count (IC),
(vi) Start Timer by setting TRx bit.
(vii) Check Timer overflow bit TFx.
(viii) Clear Timer overflow bit TFx, once it is set.
(ix) Stop Timer by clearing TRx bit.
Example: 1. Write a program to generate a square wave of 100Hz frequency at pin P2.3 on crystal
frequency 11.0592 MHz.

In this program, every time the timer-0 runs in timer mode for 5 ms and then the output bit is
complemented (0 becoming 1 and 1 becoming 0). This way a half cycle of 5 ms is obtained for the
continuous square wave with time period 10 ms, i.e., frequency 100 Hz. Every time the timer

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overflows and both TF0 & TR0 bits are cleared, IC value is loaded into TH0 and TH1 SFRs and
TR0 is set to run the timer continuously.
Example: 2. Write a program for counter-1 in mode-2 to count the pulses present at pin T1.
Display the pulse count available at TL1 through port P2.
As the pulse is available at the pin T1
(P3.5), the timer-1 (Timer-1 is responds
to pulses at T1 and Timer-1 is responds
to pulses at T0) is to be used in counter
mode.

Here only the timer-1 will be activated

for operation, hence all the 4 bits
corresponding to timer-0 are cleared as
the values they hold are of no use.

CH-6 interrupts in 8051

6.1 Introduction
Interrupt is an external/internal signal appearing at some pins of microcontroller. The
microcontroller suspends execution of main program temporarily after completing the execution
of current instruction once an interrupt is received. The microcontroller attends the signal by
executing a subroutine. After executing the subroutine program control returns to main program to
execute rest of the program.
8051 attends signals by two methods. These are as follows.
1. Status-check method-
 Controller checks status signal continuously
 Controller is tied in a loop primarily for checking status
 May execute main program intermittently

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  Significant Time wasted for checking status
 Writing program is relatively easy
2. Interrupt-driven method-
 Controller continues executing main program ‘freely’
 It goes to execute a subroutine after being interrupted
 A time-efficient program
 Sometimes memory-efficient too
Total 5 interrupt signals are attended by 8051 microcontroller. These are as following.
 Timer-0 overflow: TF0
 Timer-1 overflow: TF1
 Reception/ transmission of serial character: when RI / TI bit is set
 External event-0: signal at P3.2 (INT0)
 External event-1: signal at P3.2 (INT1)
INT0 and INT1, when high, can initiate timer depending on status of TMOD.
INT0 and INT1, when active low/ on negative age, can act as interrupt signal.
6.2 activation of interrupt system
Two conditions for activation of interrupt system are- (i) presence of interrupt signal and (ii)
presence of interrupt system. These two must be satisfied simultaneously.
Condition-1: When interrupt signal is present
When interrupt flag bits are set, microcontroller assumes that interrupt signal is present.
Interrupt Interrupt Description Causes for bit-set
Flag Bits
IE0 External-0 Presence of appropriate signal at P3.2 (∫ 0 ) pin
TF0 Timer-0 overflow When timer-0 overflows
IE1 External-1 Presence of appropriate signal at P3.3 (∫ 1) pin
TF1 Timer-1 overflow When timer-1 overflows
RI/ TI Serial bit Reception/ On completion of Reception/ Transmission of serial
Transmission data
Interrupt Flag bits are within Timer Control (TCON) SFR.
When 1: Interrupt signal to be negative edge
sensitive at INTx
When 0: Interrupt signal to be low level
sensitive at INTx
Condition-2: When interrupt system is present
Interrupt system is enabled through bits in Interrupt Enable (IE) SFR.

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 EA bit must be 1. This is a necessary but not
sufficient condition. ES is used to recognize
TI and RI. EX1 and EX0 are used to activate
interrupt signals.

Example-1
1. Write a program to enable Timer-0 interrupt.
MOV IE, #88h (or)
SETB ET1
SETB EA
2. Write a program to enable External-0 interrupt on edge-sensitive signal.
SETB IT0
SETB EX0
SETB EA
6.3 Polling Sequence, Interrupt priority & Interrupt Sequence:
When more than one interrupt is activated, microcontroller, while busy in executing main
program, searches for interrupt signal at the background. Sequence of such events is called Polling
Sequence. The sequence is as shown below-
1. External-0 interrupt
2. Timer-0 interrupt
3. External-1 interrupt
4. Timer-1 interrupt
5. Serial interrupt.
Interrupt priority:
In spite of having polling sequence, interrupt priorities can forcibly be changed by user. If
priorities of two interrupts are kept same, sequence of interrupt service will be as per polling
sequence. Interrupt priorities are controlled by IP SFR.

Rules of Interrupt Priority:

 Nothing can interrupt a high-priority interrupt, not even another high-priority interrupt.
 A high-priority interrupt may interrupt a low-priority interrupt.
 A low-priority interrupt is serviced if no other interrupt is already executing.
©AnirbanM@Dept of EE, Ghatal Govt Polytechnic 29
  If two interrupts occur at the same time, the interrupt with higher priority will be serviced
first.
 If two interrupts of same priority occur at the same time, one interrupt will be serviced first
as per polling sequence.
Interrupt Sequence: it is the sequence to be followed when an interrupt is triggered.
 Current value in PC is saved on the stack, low-byte first.
 Interrupts of the same and lower priorities are blocked.
 In case of Timer interrupts, the corresponding interrupts flags (TF0 & TF1) are
automatically cleared.
 In case of External interrupts, flags (IE0 & IE1) automatically reset when interrupts signals
are negative edge sensitive.
 In case of External interrupts, flags (IE0 & IE1) has to be cleared by user in the beginning
of service routine when interrupt signals low level sensitive
 Program execution transfers to the corresponding interrupt handler vector address (call
address) after it is loaded in to PC
 The interrupt handler routine contains a jump instruction only in order to point to the
service routine only.
 This is because space for writing program is too small (8 locations, i.e., 8 bytes maximum).
 The instruction RETI written at the end of service routine makes popping off the stack
content in to PC to restore normal program execution.
 Interrupt status is restored to its pre-interrupt status.
Interrupt Handler Address:

Interrupt Flag Interrupt

Handler
Address
External-0 IE0 0003h
Timer-0 TF0 000Bh
External-1 IE1 0013h
Timer-1 TF1 001Bh
Serial RI/ TI 0023h
It may be noted that the spacing between two consecutive addresses is only 8 bytes. So, separate
Interrupt Service Routines (ISRs) are required. These are subroutines invoked by ISR call.
6.4 Register Protection:
Contents of registers used in main program may be altered by interrupt service routine. Registers
must be protected from such corruption.
Remedy:
 Push the contents of registers in to stack before its use within service routine.
 Use registers freely inside the service routine.
 Pop off the content from stack and return to main program.
Format of the program:
SERVRT: Reset bits in IE SFR for To save from further interruption of
©AnirbanM@Dept of EE, Ghatal Govt Polytechnic 30
 high priority interrupts the service routine

PUSH ACC Register Protection

PUSH PSW
PUSH DPL
PUSH DPH
PUSH B
PUSH 00h 00h is used to store contents of R0
-------------
Main part of subroutine
-------------
POP 00h
POP B
POP DPH
POP DPL
POP PSW
POP ACC
RETI
Example- program to switch on and off the buzzer connected to P1.4 at every external interrupt.
BUZ equ P1.4
org 0000h
sjmp MAIN /*jump to start of the program*/
org 0003h /*ISR for external interrupt 0*/
cpl BUZ /*toggle the buzzer pin output*/
clr IE0 /*clear interrupt flag*/
reti /*return to main program*/
MAIN: /*start of program*/
setb EA /*Enable interrupts*/
setb EX0 /*Enable external interrupt0*/
setb BUZ /*set the buzzer pin output*/
Jmp $
end /*End of the program*/

CH-7 Applications of microcontroller 8051

7.1.1 Generation of Triangular Waveform:

ORG 0000h
MOV P1, #00h Configure P1 as output port
CLR A Clear the accumulator

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UP: MOV P1, A Send the accumulator value to port P1
INC A Increment accumulator: rising edge of waveform
CJNE A, #0FFh, UP Go on incrementing until the accumulator reaches FFh
DOWN: MOV P1, A Send the accumulator value to port P1
DEC A Decrement accumulator: falling edge of waveform
CJNE, #00h, DOWN Go on decrementing until the accumulator reaches FFh
SJMP UP Go back to start of rising edge generation
END
The initial value of accumulator is 00. Then its value is continuously incremented till the value
FFh (=25510) is attained. This creates the rising edge of the triangular waveform. Next the value of
accumulator will continuously go on decrementing until it becomes zero again. This is the falling
edge of the waveform. Again the value will have to be incremented as before and this repetition of
rising edge followed by falling edge will continue to generate a continuous triangular waveform.
This wave can be made symmetrical by passing the waveform through a difference op-amp with
the use of some suitable reference voltage for subtraction.
7.1.2 Generation of Staircase Waveform:

ORG 0000h
CLR C clear the accumulator
MOV A, #00h send 00 to accumulator
MOV P1, A send the accumulator value to port P1
UP: ACALL DELAY call the delay function
ADD A, #10h add with accumulator 10h
MOV P1, A send the value of accumulator to P1
CJNE A, #50h, UP go on increasing the value of accumulator until it reaches 50h
DOWN: ACALL DELAY call the delay function
SUBB A, #10h subtract 10h from accumulator
MOV P1, A send the value of accumulator to P1
CJNE A, #00h, UP go on decreasing the value of accumulator until it reaches 00h
SJMP UP go back to the start of the program
DELAY: MOV R0, #20d delay function: arbitrary values of R0, R1 & R2 are taken

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L2: MOV R1, #20d
L1: MOV R2, #20d
L0: DJNZ R2, L0
DJNZ R1, L1
DJNZ R0, L2
RET return to the main program
END
Initial value of the accumulator is 00. Then it will go on increasing by 10h each time until the
value of 50h is attained. This is the rising part of the waveform. Next the value of accumulator has
to go on decreasing by 10h each time until the value of accumulator drops to 00 again. This is the
falling part of the waveform. The accumulator will stay at each value for some time to generate
steps of the staircase. This is done by introducing a certain time delay once a new value is
attained. This basic waveform will be repeated to generate the continuous waveform. Selection of
time delay has to be so adjusted that desired time period is obtained at the output.
This wave can be made symmetrical by passing the waveform through a difference op-amp with
the use of some suitable reference voltage for subtraction.
7.2 Measurement of Frequency:
Here, the signal, frequency of which is to be measured,
is fed at the pin T1 (P3.5). Prior to this the sinusoidal
signal needs to be converted to its equivalent
rectangular form using other circuit elements (like
Schmitt trigger). Now timer/counter-0 has to run in timer mode starting with initial count (IC)=0
for 14 number of complete cycles to generate time interval of checking of 1 so that it can detect
number of pulses received per second. Timer/counter-1 is run in counter mode and it counts
number of pulses at input pin T1 starting with initial count (IC) =0, so that the first pulse will
move the counter to count value of 1.

ORG 0000h
RPT: MOV TMOD, #15h configure timer-1 as timer and timer-0 as counter
SETB P3.4 configure P3.4 pin as input
MOV TL0, #00h set 0 as higher byte of initial count of counter
MOV TH0, #00h set 0 as lower byte of initial count of counter
SETB TR0 start counter
MOV R0, #14d R0 is so set that timer-1 runs for 1 second
AGAIN: MOV TL1, #00h set 0 as higher byte of initial count of timer
MOV TH1, #00h set 0 as lower byte of initial count of timer
SETB TR1 start timer
BACK: JNB TF1, BACK go on until the timer overflows
CLR TF1 clear the timer overflow
CLR TR1 stop the timer

©AnirbanM@Dept of EE, Ghatal Govt Polytechnic 33

DJNZ R0, AGAIN go on continuing with the timer operation until 1s elapses
MOV A, TL0 send the lower byte of counter to accumulator
MOV P2, A send the accumulator to port 2
MOV A, TH0 send the higher byte of counter to accumulator
MOV P1, A send the accumulator to port 1
SJMP RPT go back to the initial point
END
12 12
T d= ×no . of machine cycles × ( 65 ,536−0 )
11. 0592×10 6 11. 0592×106
= =71111.11x10-6 sec,
after each cycle of timer operation.
⸫Total time delay generated for 14 (⸪R0 = 14d) such cycles is (71111.11x10 -6 x 14) = 0.996s ≈
1s.
7.3 Bidirectional Control of DC Motor:

A simple program to operate a basic H-Bridge is as follows.

ORG 0000h
MAIN: CLR P1.0
CLR P1.1
CLR P1.2
CLR P1.3

©AnirbanM@Dept of EE, Ghatal Govt Polytechnic 34

 SETB P2.7
MONITOR: JNB P2.7, CLOCKWISE
SETB P1.0
CLR P1.1
CLR P1.2
SETB P1.3
SJMP MONITOR
CLOCKWISE: CLR P1.0
SETB P1.1
SETB P1.2
CLR P1.3
SJMP MONITOR
END

©AnirbanM@Dept of EE, Ghatal Govt Polytechnic 35