IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308

DESIGN AND IMPLEMENTATION OF SYNCHRONOUS 4-BIT UP

COUNTER USING 180NM CMOS PROCESS TECHNOLOGY

Yogita Hiremath1, Akalpita L. Kulkarni2, J. S. Baligar3

1
PG Student, Dept. of ECE, Dr.AIT, Bangalore, Karnataka, India
2
Associate Professor, Dept. of ECE, Dr.AIT, Bangalore, Karnataka, India
3
M.Tech. Coordinator, Dept. of ECE, Dr.AIT, Bangalore, Karnataka, India

Abstract
In this paper design of synchronous 4-bit up counter is proposed using master-slave negative pulse-triggered D flip-flops. The
master slave D flip-flop is implemented using 8 nand gates and an inverter. The counter is provided with additional synchronous
clear and count enable inputs. The main objective is to optimize the layout of the synchronous 4-bit up counter in terms of area.
The design is implemented using Cadence Virtuoso schematic editor and simulated using Cadence Virtuoso analog design
environment at 180nm CMOS process technology. The optimized layout of the counter is designed using Cadence Virtuoso Layout
Suite. The counter has transistor count of 210. The estimated power of the counter is 97.90μW and delay is 20.39ns.

Keywords: Area, Cadence, Counter, Delay, Master-slave D flip-flop, Nand gate, Power and Synchronous.
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1. INTRODUCTION design, Cadence Virtuoso Layout Suite that speeds up the

physical layout of the design and Cadence Assura Physical
Counting is a fundamental function of digital circuits. A Verification reduces overall verification time because it
digital counter consists of a collection of flip-flops that incorporates a fast and intuitive debug capability integrated
change state (set or reset) in a prescribed sequence. The within the Virtuoso custom design environment. It helps to
primary function of a counter is to produce a specified easily recognize, fix, extract and compare errors.
output pattern sequence. For this reason it is also a pattern
generator [2]. This pattern sequence might correspond to the Several counter circuits have been proposed targeting on
number of occurrences of an event or it might be used to design accents such as power, delay and area. Among those
control various portions of a digital system. In this latter designs synchronous counters using master-slave D flip-
case each pattern is associated with a distinct operation that flops have been widely used. The paper is organized as
the digital system must perform. follows: in section 2, the design of the proposed counter is
presented. In section 3, the schematic and layout are
There are tremendous applications of a counter in the digital presented. In section 4, the simulation results are given and
consumer electronics market. A counter can play a vital role discussed. The area, power and delay of the counter are
in several circuits ranging from a simple display to complex estimated. Finally a conclusion will be made in the last
microcontroller circuits. Some of the apparent applications section.
of a counter are: frequency divider in phase-locked loops,
frequency synthesizers, signal generation and processing
2. THE PROPOSED COUNTER
circuits, microcontrollers, digital memories and in digital
clock and timing circuits. Synchronous counter is the most popular type of counter. It
typically consists of a memory element, which is
A counter is another example of a register [2]. As in the case implemented using flip-flops and a combinational element,
of a register each of the 0-1 combinations that are stored in which is traditionally implemented using logic gates. Logic
the collection of flip-flops that comprise the counter, that is gates are logic circuits with one or more input terminals and
the output pattern, is known as a state of the counter. The one output terminal in which the output is switched between
total number of states is called its modulus. Thus if a two voltage levels determined by a combination of input
counter has „m‟ distinct states, then it is called a modulus-m signals. The use of logic gates for combinational logic
counter or mod-m counter. The order in which the states typically reduces the cost of components for counter circuits
appear is referred to as its counting sequence. to an absolute minimum, so it remains a popular approach.

The proposed synchronous 4-bit up counter is implemented Synchronous counters have an internal clock, whereas
using Cadence EDA tool [1]. The tool provides asynchronous counters do not. As a result, all the flip-flops
sophisticated features such as Cadence Virtuoso schematic in a synchronous counter are driven simultaneously by a
editor which provides sophisticated capabilities which speed single, common clock pulse. In an asynchronous counter,
and ease the design, Cadence Virtuoso Visualization and the first flip-flop is driven by a pulse from an external clock
Analysis which efficiently analyzes the performance of the and each successive flip-flop is driven by the output of the
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IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308

preceding flip-flop in the sequence. This is the essential Master changes its state when clock is high while the latter
difference between synchronous and asynchronous counters. changes its state when clock is low. When the clock is high
The propagation delay of synchronous counter is the master tracks the value of D but since the slave is in
comparatively lower than asynchronous counter. Its inactive state, Qs also remains unchanged. When the clock
performance is also better from a reliability perspective signal goes low, the master goes to inactive state and the
because there is no glitch. slave which is now in active state tracks the value of Qm.
While clock is low, Qm does not change its value. Thus only
2.1. Master-Slave D Flip-Flop once during the clock cycle the slave can undergo change in
its value. It can also be observed that only during the
A master-slave D flip-flop is created by connecting two transition from high to low, the output gets change. This
gated D latches in series and inverting the enable input to transition is referred to as "negative pulse-triggered" [5].
one of them. It is called master-slave because the second
(slave) latch in the series only changes in response to a
change in the first (master) latch [2]. The term pulse-
triggered means that data is entered on the rising edge of the
clock pulse, but the output does not reflect the change until
the falling edge of the clock pulse. Master-slave flip-flops
can be constructed to behave as a J-K, R-S, T or D flip-flop.

The purpose of master-slave flip-flops is to protect a flip-

Fig-2: Master-slave D flip-flop with clear input
flop‟s output from inadvertent changes caused by glitches
on the input. Master-slave flip-flops are used in applications
Fig.2 shows the implementation of master-slave D flip-flop
where glitches may be prevalent on inputs. The master-slave
with clear input. The circuit is designed using the truth table
configuration has the advantage of being pulse-triggered,
given in table.2. When the clr (clear) input goes high,
making it easier to use in larger circuits, since the inputs to a
irrespective of the inputs D and clock, the output goes low.
flip-flop often depend on the state of its output.
Table-2: Truth table of master-slave D flip-flop with clear
input
Clr Clk Qn+1 (next state)

0 0 D

0 1 Qn (present state)

1 X 0

Fig-1: Master-slave D flip-flop 2.2. Synchronous 4-Bit Up Counter

Fig.1 shows negative pulse-triggered master-slave D flip- The proposed synchronous 4-bit up counter has 3 AND
flop. It responds on the negative edge of the enable input gates, 4 XOR gates and 4 master-slave D flip-flops. Same
(usually a clock). The circuit consists of two D flip-flops clock pulse is given to each flip-flop. So with every clock
connected together. When the clock is high, the D input is pulse the counter counts one step up. It is an up counter and
stored in the first latch, but the second latch cannot change starts from 0000. Then with clock pulse counts like 0001,
state. When the clock is low, the first latch's output is stored 0010, 0011, 0100 up to 1111. Then it starts from 0000 again.
in the second latch, but the first latch cannot change Q0 is the LSB and Q3 is the MSB.
state. The result is that output can only change state when
the clock makes a transition from high to low. The master-slave D flip-flop actually works at the falling
edge of the clock. But because it is a master slave
Table-1: Truth table of master-slave D flip-flop configuration [8], it actually stores the input at rising edge
and it is given to the output at the falling edge of the clock.
Clk Qn+1 (next state) So change in counter output is observed in the falling edge
of the clock.

0 D There are 2 additional inputs in the counter, count enable

(CE) and clear (clr).
1 Qn (present state) 1. Count Enable (CE) input: If CE=0, then counter
stops counting. IF CE=1, each clock pulse results in
a counting action.

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IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308

2. Clear (clr) input: If clr=1, then the counter output The schematic diagram of inverter, NAND gate, AND gate
clears to 0000. If clr=0, each clock pulse results in and XOR gate are as shown in fig.4.
a counting action.

The control logic of the counter is as follows: The XOR gate

complements each bit. The AND chain causes complement
of a bit if all the bits toward LSB from it equal 1.The Count
Enable forces all outputs of AND chain to 0 to “hold” the
state.

Fig-4(a): Inverter schematic diagram

Fig-3: Synchronous 4-bit up counter

3. SCHEMATIC AND LAYOUT

The proposed counter is implemented in Cadence EDA tool.
The transistor level diagram is implemented using Cadence Fig-4(b): NAND gate schematic diagram
Virtuoso schematic editor [1]. The optimized layout is
designed using Cadence Virtuoso Layout Suite.

3.1. Schematic
The implementation of the synchronous 4-bit up counter
will be performed progressively by implementing and
creating instances of the components of the counter
independently and subsequently using all the components
together to create the counter. The schematic diagram of all
the components are built using PMOS and NMOS
transistors with the following specifications.

Length : 180 nm
Total width : 2 μm
Finger width : 2 μm
Fingers :1
S/D metal : 400 nm
Threshold : 800 nm Fig-4(c): AND gate schematic diagram

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IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308

3.2. Layout
The optimized layout of all the gates, master-slave D flip-
flop and synchronous 4-bit up counter are designed using
sea of gate arrays concept in order to reduce the area. All the
layouts are designed using 180nm CMOS process
technology [1]. The cadence tool helps to verify layout
versus schematic effectively.

Fig-4(d): XOR gate schematic diagram

Using the instances of inverter, NAND gate and AND gate

gates discussed above, master-slave D flip-flop is
implemented as shown in fig.5. Subsequently using the
instances of master-slave D flip-flop, AND gate and XOR
gate the proposed synchronous 4-bit up counter is
implemented as shown in fig.6.

Fig-7(a): Inverter layout

Fig-5: Master-slave D flip-flop schematic diagram

Fig-7(b): NAND gate layout

Fig-6: Synchronous 4-bit up counter schematic diagram Fig-7(c): AND gate layout

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IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308

4. SIMULATION RESULTS
The layouts of master-slave D flip-flop and synchronous 4-
bit up counter are simulated and the transient responses are
analyzed using Cadence analog design environment.

Fig-10(a): Transient response of master-slave D flip-flop

Fig-7(d): XOR gate layout

The final layout of the master-slave D flip-flop is designed

by integrating the layout instances of the NAND gates and
subsequently the layout of the synchronous 4-bit up counter
is designed by integrating the layout instances of the basic
AND, XOR gates and master-slave D flip-flop.

Fig-10(b): Transient response of counter with CE=1, clr=0

Fig-8: Master-slave D flip-flop layout

Fig-10(c): Transient response of counter with CE=1, clr=1

Fig-9: Synchronous 4-bit up counter layout Fig-10(d): Transient response of counter with CE=0, clr=0

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Table-3: Transistor count, delay and power estimation of BIOGRAPHIES

the gates, flip-flop and counter
Circuits Transistor Delay Power Yogita Hiremath completed her Bachelor
count of engineering at Hirasugar Institute of
Technology, Nidasoshi, Karnataka, India
Inverter 2 11.04 ns 4.70 μW in 2012. She is pursuing Master in
Technology at Dr. Ambedkar Institute of
NAND gate 4 20.92 ns 5.22 μW Technology, Bangalore, Karnataka, India.
Her areas of interest are VLSI Design and digital design.
AND gate 6 195.50 ps 7.87 μW
Akalpita L. Kulkarni completed her
XOR gate 6 5.985 ns 9.93 μW Bachelor of Engineering in ECE branch at
PDACEM, Gulbarga, Karnataka, India in
Master-slave D 42 11.22 ns 26.23 μW 1990. She completed her Masters Degree
flip-flop in Applied Electronics at Anna University,
Synchronous 210 20.39 ns 97.90 μW Chennai, India in 1998. She is working as
4-bit up counter Associate Professor in ECE department at Dr.Ambedkar
Institute of Technology, Bangalore, Karnataka, India. Her
5. CONCLUSIONS areas of interest include Microprocessors and
In this paper, synchronous 4-bit up counter has been Microcontrollers.
implemented, simulated and analyzed. The performance of
the counter is assessed in terms of area, delay and power Dr. J. S. Baligar completed his Ph.D. in
consumption. The main goal to optimize the layout is met 2003 from Bangalore University in
satisfactorily using Cadence tool with the sea of gate arrays Electronic Science Department. He has
concept. The logic and characteristics of the master-slave D published around 10 papers in
flip-flop and synchronous 4-bit up counter are easily international journals. He is working as
verified with the simulation results. Thus we present the Associate Professor in ECE department at
design and implementation of synchronous 4-bit up counter Dr.Ambedkar Institute of Technology, Bangalore,
which is optimized in terms of area. Karnataka India. His areas of interest are RF circuit design,
micro strip antennas and VLSI design.
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