Counters

Overview
◼ Ripple Counter
◼ Synchronous Binary Counters
◼ Design with D Flip-Flops
◼ Design with J-K Flip-Flops

◼ Serial Vs. Parallel Counters

 Counters
◼ A counter is a register that goes through a
predetermined sequence of states upon the
application of clock pulses.
◼ Counters are categorized as:
◼ Ripple Counters:
The FF output transition serves as a source for
triggering other FFs. No common clock.
◼ Synchronous Counter:
All FFs receive the common clock pulse, and the
change of state is determined from the present
state.
Example: A 4-bit Binary Up
Counter (Ripple Counter)
Operation:
◼ The least significant bit (Q0) is
complemented with each
negative-edge clock pulse input.
◼ Every time that Q0 goes from 1
to 0, Q1 is complemented.
◼ Every time that Q1 goes from 1
to 0, Q2 is complemented.
◼ Every time that Q2 goes from 1
to 0, Q3 is complemented, and so
on.
 Example: A 4-bit Binary Up
Counter (Ripple Counter)

Less Significant
Bit output is Clock
for Next Significant Bit!
(Clock is negative edge)

Recall...

+
 Example (cont.)
◼ The output of each FF is connected to the
C input of the next FF in sequence.
◼ The FF holding the least significant bit
receives the incoming clock pulses.
◼ The J and K inputs of all FFs are connected
to a permanent logic 1.
◼ The bubble next to the C label indicates
that the FFs respond to the negative-going
transition of the input.
 A 4-bit Binary Down
Counter (Ripple Counter)
◼ Use direct Set (S) signals instead of
direct Reset (R), in order to start at 1111.
◼ Alternative designs:
◼ Change edge-triggering to positive
◼ Connect the complement output of each FF
to the C output of the next FF in the
sequence… (homework!)
 Ripple Counter Summary
FF Edge FF output used as Clk Counter type
Triggering for next stage FF

NEG Q UP

NEG Q’ DOWN

POS Q’ UP

POS Q DOWN
 ◼ Q1 complemented on every
clock edge
Q2 complemented if Q8=0,
Q8 Q4 Q2 Q1
◼
Q1 goes from 1 to 0. Q2
cleared if Q8= 1 and Q1
goes from 1 to 0
◼ Q4 complemented when Q2
goes from 1 to 0
◼ Q8 complemented when
Q4Q2 = 11, Q1 goes from 1
to 0. Q8 cleared if either
Q4 or Q2 is 0 and Q1 goes
from 1 to 0
Synchronous Binary Counters
◼ The design procedure for a binary counter is
the same as any other synchronous sequential
circuit.
◼ The primary inputs of the circuit are the CLK
and any control signals (EN, Load, etc).
◼ The primary outputs are the FF outputs
(present state).
◼ Most efficient implementations usually use T-
FFs or JK-FFs. We will examine JK and D flip-
flop designs.
Synchronous Binary Counters:
J-K Flip Flop Design of a 4-bit Binary Up Counter
Synchronous Binary Counters:
J-K Flip Flop Design of a Binary Up Counter (cont.)
Synchronous Binary Counters:
J-K Flip Flop Design of a Binary Up Counter (cont.)
Synchronous Binary Counters:
J-K Flip Flop Design of a Binary Up Counter (cont.)
Synchronous Binary Counters:
J-K Flip Flop Design of a Binary Up Counter (cont.)

logic 1 Q0
J JQ0 = 1
C
KQ0 = 1
K

JQ1 = Q0
J Q1
KQ1 = Q0
C
K

J Q2 JQ2 = Q0 Q1
C KQ2 = Q0 Q1
K

J Q3 JQ3 = Q0 Q1 Q2
C KQ3 = Q0 Q1 Q2
K

CLK
Synchronous Binary Counters:
J-K Flip Flop Design of a Binary Up Counter with EN and CO

EN = enable control
signal, when 0 counter
remains in the same
state, when 1 it counts

CO = carry output signal,

used to extend the
counter to more stages

JQ0 = 1 · EN
KQ0 = 1 · EN
JQ1 = Q0 · EN
KQ1 = Q0 · EN
JQ2 = Q0 Q1 · EN
KQ2 = Q0 Q1 · EN
JQ3 = Q0 Q1 Q2 · EN
KQ3 = Q0 Q1 Q2 · EN
Fig. 6.12 C0 = Q0 Q1 Q2 Q3 · EN
Thank You
 Serial Vs Parallel Counters
◼ If serial gating (chain of gates, info ripples
through) is used
→ serial counter
◼ If serial gating is replaced with parallel
gating (this is analogous with ripple-logic
replaced with carry-lookeahead logic in our
adder designs)
→ parallel counter
◼ Advantage of parallel over serial counter:
faster in certain occasions (1111 → 0000)
Up-Down Binary Counter

clock Q0
n-bit
Up-Down Q1
UD Counter ••
•
Qn-1

UD = 0: count up
UD = 1: count down
A countdown binary counter
can be constructed as shown in Fig. 6.12

except that
the inputs to the AND gates must come from
the complemented outputs, instead of
the normal outputs, of the previous flip‐flops
 Synchronous BCD Counter

The table shows an output y, which is equal to 1 when the present state is 1001.

In this way, y can enable the count of the next‐higher significant decade while the same
pulse switches the present decade from 1001 to 0000.
Synchronous BCD Counter
Binary Counter with Parallel Load
Counters employed in digital systems quite often require a parallel‐load capability for
transferring an initial binary number into the counter prior to the count operation.

(Next slide) gives the logic diagram and symbol of a 4-bit synchronous
binary counter with parallel load capability.
 BCD counter

◼ The binary counter

with parallel load can
be converted into a
synchronous BCD
counter by
connecting an
external AND gate
to it.

A counter with a parallel load can be used to

generate any desired count sequence.
 BCD counter (cont.)
◼ The counter starts with an all-zero output.
◼ As long as the output of the AND gate is 0, each
positive clock pulse transition increments the counter
by one.
◼ When the output reaches the count of 1001, both Q0
and Q3 become 1, making the output of the AND gate
equal to 1. This condition makes Load active, so on the
next clock transition, the counter does not count, but
is loaded from its four inputs.
◼ The value loaded then is 0000.
In (b) the NAND gate detects the count of 1010, but as soon as this count occurs, the register is cleared.

The count 1010 has no chance of staying on for any

appreciable time, as the register goes immediately to 0.

A momentary spike occurs in output A0 as the count

goes from 1010 to 1011 and immediately to 0000.

The spike may be undesirable, and for that reason, this configuration is not recommended.
 Arbitrary Sequence Counter
▪ Counters can be designed to generate any desired sequence of states.

▪ A divide‐by‐N counter (also known as a modulo‐N counter) is a counter that goes

through a repeated sequence of N states.

◼ Given an arbitrary sequence, design a counter that will

generate this sequence.
◼ Procedure:
◼ Derive state table/diagram based on given sequence
◼ Simplify (using K-maps, etc)
◼ Draw logic diagram

◼ Example: Use D-FFs to draw the logic diagram for

sequence generator (counter) for: 0 → 7 → 6 → 1 → 0
(000 → 111 → 110 → 001 → 000)
 Counter with Unused States

• A sequential circuit with n flip‐flops may use fewer than the maximum
possible number of states ( 2n ).

• States that are not used are not listed in the state table.

• In simplifying the flip‐flops input equations, the unused states may be treated as
don’t‐care conditions or may be assigned specific next states.

• Once the circuit is designed and constructed, outside interference during

its operation may cause the circuit to enter one of the unused states.

• The circuit should eventually go into one of the valid states so that it can
resume normal operation.

• If the unused states are treated as don’t‐care conditions, then after designing the
circuit, the effect of the unused states MUST be investigated from the analysis of
the designed circuit.
 Counter with Unused States
Consider a specific counter specified in Table below

The count sequence of the counter is not straight binary, and two states,
011 and 111, are not included in the count. Don’t Care cases
Note: Since there are two unused
states, 011 and 111, we analyze the
circuit to determine their effect.

If the circuit happens to be in

state 011 because of an error
signal, the circuit goes to state
100 after the application of
a clock pulse.
 RING COUNTER
Timing signals that control the sequence of operations in a digital
system can be generated by a shift register or by a counter with a
decoder.

A ring counter is a circular shift register with only one flip‐flop being
set at any particular time; all others are cleared.

The single bit is shifted from one flip‐flop to the next to produce the
sequence of timing signals.
RING COUNTER

The initial value of the register is 1000

and requires Preset/Clear flip‐flops.

The single bit is shifted right with every

clock pulse and circulates back from T3
to T0.

Each flip‐flop is in the 1 state once

every four clock cycles and produces
one of the four timing signals

Each output becomes a 1 after the

negative‐edge transition of a clock pulse
and remains 1 during the next clock
cycle.
 RING COUNTER
• For an alternative design, the timing signals can be generated by a two‐bit counter
that goes through four distinct states.

• The decoder decodes the four states of the counter and generates the required
sequence of timing signals.
 RING COUNTER
• To generate 2n timing signals, we need either a shift register with 2n flip‐flops OR
an n ‐bit binary counter together with an n ‐to‐2 n ‐line decoder.

• For example, 16 timing signals can be generated with a 16‐bit shift register
connected as a ring counter OR with a 4‐bit binary counter and a 4‐to‐16‐line
decoder.

• In the first case, 16 flip‐flops needed. In the second, 4 flip‐flops and 16 four‐input
AND gates for the decoder needed.

NOTE

• It is also possible to generate the timing signals with a combination of a shift

register and a decoder.

• That way, the number of flip‐flops is less than that in a ring counter, and the
decoder requires only two‐input gates. This combination is called a
Johnson counter .
 JOHNSON COUNTER

A k ‐bit ring counter circulates a single bit among the flip‐flops to provide
k distinguishable states.

The number of states can be doubled if the shift register is connected as a

switch‐tail ring counter.

A switch‐tail ring counter is a circular shift register with the

complemented output of the last flip‐flop connected to the input of the
first flip‐flop.
JOHNSON COUNTER Starting from a cleared state, the
switch‐tail ring counter goes through a
sequence of eight states

The eight AND gates (NOT SHOWN)

listed in the table, when connected to the
circuit, will complete the construction of
the Johnson counter

Since each gate is enabled during one

particular state sequence, the outputs of
the gates generate eight timing signals in
succession.

The decoding follows a regular pattern:

- The all‐0’s state is decoded by taking
the complement of the two extreme
Flip‐flop outputs.
- The all‐1’s state is decoded by taking
the normal outputs of the two
extreme flip‐flops.
- All other states are decoded from an
adjacent 1, 0 or 0, 1 pattern in the
sequence.
 JOHNSON COUNTER One disadvantage of this circuit is that
if it finds itself in an unused state,
it will persist in moving from one invalid
state to another and never find its way
to a valid state.

One correcting procedure:

Disconnect the output from flip‐flop B

that goes to the D input of flip‐flop C
and
instead enable the input of flip‐flop C by
the function
DC = (A + C)B
where DC is the flip‐flop input equation
for the D input of flip‐flop C.

NOTE
Johnson counters can be constructed for any number of timing sequences.
- The number of flip‐flops needed is one‐half the number of timing signals.
- The number of decoding gates is equal to the number of timing signals, and
only two‐input gates are needed.
Thank You