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Sheet 6 Digital (ECE 221)

This document is a chapter summary for a course on digital and logic circuits. It outlines various exercises involving the design of combinational logic circuits, including circuits with multiple inputs and outputs, decoders, subtractors, comparators, and other Boolean logic functions. Solutions are to be designed using techniques like Karnaugh maps, decoders, multiplexers, and minimizing the number of gates. The chapter aims to help students learn how to systematically design combinational logic circuits to perform various computational tasks.

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22 views2 pages

Sheet 6 Digital (ECE 221)

This document is a chapter summary for a course on digital and logic circuits. It outlines various exercises involving the design of combinational logic circuits, including circuits with multiple inputs and outputs, decoders, subtractors, comparators, and other Boolean logic functions. Solutions are to be designed using techniques like Karnaugh maps, decoders, multiplexers, and minimizing the number of gates. The chapter aims to help students learn how to systematically design combinational logic circuits to perform various computational tasks.

Uploaded by

01326567536m
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Horus University in Egypt (HUE) Digital & Logic Circuits

Faculty of Engineering (ECE 221)


Mechatronics Department Sheet (6)

Sheet (6)
Chapter 5: Combinational Logic Circuits

5.1 Design a combinational circuit with three inputs and one output.

(a) The output is l when the binary value of the inputs is less than 3. The output is 0 otherwise.

(b) The output is l when the binary value of the inputs is an even number.

5.2 Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and
C. When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input.
When the binary input is 4, 5, 6, or 7, the binary output is two less than the input.

5.3 An ABCD-to-seven-segment decoder is a combinational circuit that converts a decimal


digit in BCD to an appropriate code for the selection of segments in an indicator used to
display the decimal digit in a familiar form. The seven outputs of the decoder (a, b, c, d, e, f,
g) select the corresponding segments in the display, as shown in Fig. P5.3

(a) The numeric display chosen to represent the decimal digit is shown in Fig. P5.3

(b) Using a truth table and Karnaugh maps, design the BCD-to-seven-segment decoder
using a minimum number of gates. The six invalid combinations should result in a blank
display.

FIGURE P5.3

5.4 Design a four-bit combinational circuit 2's complementor. (The output generates the
2's complement of the input binary number.) Show that the circuit can be constructed with
exclusive-OR gates. Can you predict what the output functions are for a five-bit 2's
complementer?
Page 1 of 2
Horus University in Egypt (HUE) Digital & Logic Circuits
Faculty of Engineering (ECE 221)
Mechatronics Department Sheet (6)

5.5 Design a half-subtractor circuit with inputs x and y and outputs Diff and Bout. The
circuit subtracts the bit’s x - y and places the difference in D and the borrow in Bout.

(a) Design a full-subtractor circuit with three inputs x, y, Bin and two outputs Diff and
Bout. The circuit subtracts x - y - Bin, where Bin is the input borrow, Bout is the output
borrow, and Diff is the difference.

5.6 Design a combinational circuit that compares two 4-bit numbers to check if they are
equal. The circuit output is equal to 1 if the two numbers are equal and 0 otherwise.

5.7 Using a decoder and external gates, design the combinational circuit defined b y the
following three Boolean functions:

(a) F1 = x'yz' + xz (b) F1 = (y' +x)z

F2 = xy'z' + x'y F2 = y'z' + xy' + yz'

F3 = x'y'z' + xy F3 = (x' + y)z

5.8 Implement the following Boolean function with a multiplexer

(a) F (A, B, C, D) = Σ (0, 2, 5, 8, 10, 14)

(b) F (A, B, C, D) = Π (2, 6, 11)

5.9 Implement a full adder with two 4 X 1 multiplexers.

With our best wishes,

Prof. Dr. Omer Alkelany Dr. Mohammed Kamal

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