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MIC 11 - Assembly Language For 8086

The document discusses the instruction set of the Intel 8086 microprocessor. It describes that the 8086 instruction set forms the core of Intel's processor family and consists of data transfer, arithmetic, logical, string manipulation, control transfer, and other instructions. The instructions are classified based on the number of bytes and examples of common instructions are provided for each category like MOV, ADD, AND, LOOP. The document also discusses pipeline stages and provides an example to calculate clock cycles for a sequence of instructions.

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60 views17 pages

MIC 11 - Assembly Language For 8086

The document discusses the instruction set of the Intel 8086 microprocessor. It describes that the 8086 instruction set forms the core of Intel's processor family and consists of data transfer, arithmetic, logical, string manipulation, control transfer, and other instructions. The instructions are classified based on the number of bytes and examples of common instructions are provided for each category like MOV, ADD, AND, LOOP. The document also discusses pipeline stages and provides an example to calculate clock cycles for a sequence of instructions.

Uploaded by

omar hany
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Assembly Language

for 8086
Lesson 11
Ch 6

Dr. Mohammed Majid Al Khalidy


6.3. 8086 Instruction Set

The Intel 8086 Instruction Set is the core of the


entire series of processors created by Intel. Some
instructions have been added to this set to
accommodate the extra features of later designs,
but the set shown here contains the basic
instructions understood by all of the processors.
The 8086 instruction set consists of the following
instructions:

Dr. Mohammed Majid Al Khalidy 2


• Data Transfer Instructions move, copy, load exchange, input
and output.
• Arithmetic Instructions add, subtract, increment,
decrement, convert byte/word and compare.
• Logical Instructions AND, OR, exclusive OR, shift/rotate and
test.
• String Manipulation Instructions load, store, move,
compare and scan for byte/word.
• Control Transfer Instructions conditional, unconditional, call
subroutine and return from subroutine.
• Input/Output Instructions.
• Other Instructions setting/clearing flag bits, stack
operations, software interrupts, etc.

Dr. Mohammed Majid Al Khalidy 3


Classification of Instructions
The Intel 8086/8088 instructions are classified into the
following groups based on number of bytes in the instruction as
given below:

➢One-byte instructions
➢Two-byte instructions
➢Three-and four-byte instructions
➢Five-and six-byte instructions

Dr. Mohammed Majid Al Khalidy 4


Assembly instructions used in 8086
microprocessor
1. Data transfer instructions– move, load exchange, input,
output.
• MOV :Move byte or word to register or memory .
• IN, OUT: Input byte or word from port, output word to port.
• LEA: Load effective address
• LDS, LES Load pointer using data segment, extra segment .
• PUSH, POP: Push word onto stack, pop word off stack.
• XCHG: Exchange byte or word.
• XLAT: Translate byte using look-up table.

Dr. Mohammed Majid Al Khalidy 5


2. Arithmetic instructions – add, subtract, increment, decrement,
convert byte/word and compare.
• ADD, SUB: Add, subtract byte or word
• ADC, SBB :Add, subtract byte or word and carry (borrow).
• INC, DEC: Increment, decrement byte or word.
• NEG: Negate byte or word (two’s complement).
• CMP: Compare byte or word (subtract without storing).
• MUL, DIV: Multiply, divide byte or word (unsigned).
• IMUL, IDIV: Integer multiply, divide byte or word (signed)
• CBW, CWD: Convert byte to word, word to double word
• AAA, AAS, AAM,AAD: ASCII adjust for add, sub, mul, div .
• DAA, DAS: Decimal adjust for addition, subtraction (BCD numbers)

Dr. Mohammed Majid Al Khalidy 6


3. Logic instructions – AND, OR, exclusive OR, shift/rotate and test
• NOT : Logical NOT of byte or word (one’s complement)
• AND: Logical AND of byte or word
• OR: Logical OR of byte or word.
• XOR: Logical exclusive-OR of byte or word
• TEST: Test byte or word (AND without storing).
• SHL, SHR: Logical Shift rotate instruction shift left, right byte or word? by
1or CL
• SAL, SAR: Arithmetic shift left, right byte or word? by 1 or CL
• ROL, ROR: Rotate left, right byte or word? by 1 or CL .
• RCL, RCR: Rotate left, right through carry byte or word? by 1 or CL.

Dr. Mohammed Majid Al Khalidy 7


4. String manipulation instruction – load, store, move,
compare and scan for byte/word

• MOVS: Move byte or word string


• MOVSB, MOVSW: Move byte, word string.
• CMPS: Compare byte or word string.
• SCAS S: can byte or word string (comparing to A or AX)
• LODS, STOS: Load, store byte or word string to AL.

Dr. Mohammed Majid Al Khalidy 8


5. Control transfer instructions – conditional, unconditional,
call subroutine and return from subroutine.

• JMP: Unconditional jump .it includes loop transfer and subroutine and
interrupt instructions.
• JNZ: jump till the counter value decreases to zero.It runs the loop till
the value stored in CX becomes zero

Dr. Mohammed Majid Al Khalidy 9


6. Loop control instructions-
• LOOP: Loop unconditional, count in CX, short jump to target address.
• LOOPE (LOOPZ): Loop if equal (zero), count in CX, short jump to target
address.
• LOOPNE (LOOPNZ): Loop if not equal (not zero), count in CX, short jump
to target address.
• JCXZ: Jump if CX equals zero (used to skip code in loop).
• Subroutine and Interrupt instructions-
• CALL, RET: Call, return from procedure (inside or outside current
segment).
• INT, INTO: Software interrupt, interrupt if overflow.IRET: Return from
interrupt.

Dr. Mohammed Majid Al Khalidy 10


7. Processor control instructions-
Flag manipulation:

• STC, CLC, CMC: Set, clear, complement carry flag.


• STD, CLD: Set, clear direction flag.STI, CLI: Set, clear interrupt
enable flag.
• PUSHF, POPF: Push flags onto stack, pop flags off stack.

Dr. Mohammed Majid Al Khalidy 11


Sample GATE Question
Consider the sequence of machine instructions given below:
MUL R5, R0, R1
DIV R6, R2, R3
ADD R7, R5, R6
SUB R8, R7, R4

▪ In the above sequence, R0 to R8 are general purpose


registers.
▪ In the instructions shown, the first register stores the result
of the operation performed on the second and the third
registers.
▪ This sequence of instructions is to be executed in a pipelined
instruction processor with the following 4 stages:
Dr. Mohammed Majid Al Khalidy 12
MUL R5, R0, R1
DIV R6, R2, R3
ADD R7, R5, R6
SUB R8, R7, R4

(1) Instruction Fetch and Decode (IF),


(2) Operand Fetch (OF),
(3) Perform Operation (PO), and
(4) Write Back the Result (WB).

▪ The IF, OF and WB stages take 1 clock cycle each for any instruction.
▪ The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock
cycles for MUL instruction and 5 clock cycles for DIV instruction.
▪ The pipelined processor uses operand forwarding from the PO stage
to the OF stage.

Dr. Mohammed Majid Al Khalidy 13


The number of clock cycles taken for the execution of the above
sequence of instructions is ___________
(A) 11
(B) 12
(C) 13
(D) 14

Answer: (C)
Explanation:

Dr. Mohammed Majid Al Khalidy 14


Flag Register
The 8086 has a 16-bit flag register. This register is also called
Program Status Word (PSW).

Dr. Mohammed Majid Al Khalidy 15


16
Dr. Mohammed Majid Al Khalidy 17

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