EEA051 - Digital Logic

數位邏輯

Chapter 6
Registers and Counters
• Clocked sequential circuit
– No flip-flops → reduce to combinational circuit
– No combinational circuit → remain a sequential circuit
吳俊興 • registers and counters
高雄大學 資訊工程學系 • Register: a group of flip-flops capable of storing one bit of
information
– n-bit register consists of a group of n flip-flops capable of storing n bits
December 2004 • Counter: a register going through a predetermined sequence
of states

6-1 Registers • Simplest register: consisting of

only flip-flops without any gates
6-2 Shift Registers
• Example 6-1: 4-bit register
6-3 Ripple Counters – positive edge trigger
6-4 Synchronous Counters – When the clear input goes to 0, all
6-5 Other Counters flip-flops are reset. The R inputs
must be maintained at logic 1 during
6-6 HDL for Registers and Counters normal clocked operation
Parallel load • shift register: a register capable of shifting its binary
• loading: the transfer of new information into a register information in one or both directions
• Example Fig. 6-3: each clock pulse shifts the contents of the
• parallel loading: all the bits of the register are loaded
register one bit position to the right
simultaneously with a common clock pulse – serial input: determines what goes into the leftmost flip-flop
– Load control – serial output: taken from the output of the rightmost flip-flop
Approaches to register with parallel load • Shift control: make the shift occur only with certain pulses
– inhibiting the clock
• controlling the clock input signal with an enabling gate: – control through the D inputs (shown later)
uneven propagation delays between the master clock and
the inputs of flip-flops
• controlling the D inputs: ensure that all clock pulses arrive
at the same time anywhere in the system

serial transfer: information is transferred one bit at a time by

load=1 shifting the bits out of source register into destination register
• data are transferred • The serial output (SO) of
into the register with register A is connected to
the next positive edge
of the lock the serial input (SI) of
load=0 register B and the SI of
• outputs are connected register A itself
to their respective • The shift control input
inputs determines when and
how many times the
•The feedback connection registers are shifted
is necessary because the
D flip-flop does not have a • serial vs. parallel
“no change” condition
•The clock pulses are
applied to the C inputs at
all times
Register A holds the augend and register B holds the addend
The most general shift register has the following capabilities:
– Initially, register A and carry flip-flop are cleared to 0
All the numbers are transferred serially into B and added to A

•parallel adder: use

registers with parallel
load
– # of full adders = # of bits
– faster
– combinational circuit
•serial adder: use shift
registers Unidirectional shift register: capable of shifting in one direction only
– requiring less equipment
Bidirectional shift register: capable of shifting in both directions
– only one full adder
– sequential circuit universal shift register: has both shifts and parallel load capabilities

Has all the

Design a serial adder using a JK FF capabilities
•Assume 2 shift registers as input listed above
•Obtain state table with FF input/outputs
•Obtain input and output equations
•Draw the circuit

Selection inputs
control the mode
of operation

Shift registers are often used to interface

Ai digital systems situated remotely from
no full-adder Ai+1
Ai-1 each other
Ii
counter: a register that goes through a prescribed sequence of
states upon the application of input pulses
– may occur at a fixed interval of time or at random
– may follow the binary number sequence or any other sequence of states
• Decade decimal counter: 0 ~ 9
– n-bit binary counter: n flip-flops counting in binary from 0~2n-1 • Need at least 4 flip-flops, similar to a binary
Two categories counter, but state after 1001 is 0000
– Ripple counters: FF output transition serves as a source for triggering Q8 Q4 Q2 Q1
0 0 0 0
other 0 0 0 1 Q1: count input
0 0 1 0 Q2: Q1 negative-edge and Q8 = 0
• Binary ripple counter 0
0
0
1
1
0
1
0 Q4: Q2 negative-edge
0 1 0 1
• BCD ripple counter 0 1 1 0 Q8: Q1 negative-edge and Q2=Q4=1
0 1 1 1
– Synchronous counters: inputs of all FF receive the common clock 1
1
0
0
0
0
0
1
0 0 0 0
• discussed in Sections 6-4 and 6-5

•One single count input

•Output of each FF connected to C •n-decade counter: count from 0 to 10n-1
input of next higher-order FF
•Three approaches •Input to nth decades come from Q8 of the previous (n-1)th decade
– from T
– from JK: J and K inputs tied together •When Q8 in one decade goes from 1 to 0, it triggers the count
– from D: complement output connected for the next higher-order decade while its own decade goes from
to the D input
9 to 0
Every time Ai goes
from 1 to 0, it
complements Ai+1
(Negative trigger)

A3 A2 A1 A0
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
Binary count-down counter 1 0 1 1
1 0 1 0
• use positive-trigger T 1 0 0 1
flip-flops instead 1 0 0 0
0 1 1 1
• synchronous counter: clock pulses are applied to inputs of all FF
• 3-bit binary counter with T flip-flops
• similar to 4-Bit synchronous count up
binary counter

A3 A2 A1 A0 • least significant position: complemented

1 1 1 1
1 1 1 0 with every pulse
1 1 0 1
1 1 0 0
• any other positions: complemented if all
1 0 1 1 lower significant bits are equal to 0
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0

• least significant position: complemented

with every pulse
• any other positions: complemented if all up down operation
lower significant bits are equal to 1 1 x count up
0 1 count down
0 0 no change
• It can be extended to any number of
A3 A2 A1 A0 stages, with each stage having an
0 0 0 0
0 0 0 1 addition FF and an AND gate that gives
0 0 1 0 the output of 1 if all previous FF outputs
0 0 1 1
0 1 0 0 are 1 an up-down binary counter
0 1 0 1
0 1 1 0 • It can be triggered with either the using T flip-flops
0 1 1 1 positive or the negative clock edge
1 0 0 0
1 0 0 1 • It can be either of the JK-type, the T-
1 0 1 0
1 0 1 1
type, or the D-type with XOR gates
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
 count from 0000 to 1001 and back to 0000
The AND detects the The NAND detects the
occurrence of state 1001 and occurrence of state 1010 and
then the counter reloads 0 then the counter is cleared to 0

minterms 10 to 15 are taken as don’t-care terms

4 T flip-flops, 5 AND gates, and 1 OR gate

Load an initial binary number into the counter prior to the count operation
• Divide-by-N counter (modulo-N counter): a counter that goes
through a repeated sequence of N states
• Counters can be used to generate timing signals to control
the sequence of operations in a digital system
• Counters can be constructed also by means of shift registers
• The sequence of counters may follow the binary count or
may be any other arbitrary sequence
• non-binary counters
– Ring counter
It can be used to generate – Johnson counter
any desired count sequence
 switch-tail ring counter: a circular shift register with the complement output
•Outside interference may cause a circuit to enter one of the unused states of the last flip-flop connected to the input of the first flip-flop
•Example: – double the number of states for a ring counter (Figure 6-17a)
Johnson counter: a k-bit switch-tail counter with 2k decoding gates to
provide outputs for 2k timing signals
Connecting Figure 6-18a
with 8 AND gates listed
Figure 6-18b to complete
the construction of the
Johnson counter
two unused states: 011 and 111
Simplified equations: • Disadvantage: it never finds its
JA=B KA=B way to a valid state if it is at an
unused state
JB=C KB=1 We need to analyze the
circuit to determine the -Correcting: DC = (A+C)B
JC=B’ KC=1 • # of FF = ½ # of timing signals
effects of unused states!
• # of 2-input decoding gates
Self correcting counter: if it happens to be in an unused state, it eventually = # of time signals
reaches the normal counter sequence after one or more clock pulses

• ring counter: a circuit shift register with only one flip-flop being set an any
particular time, all others are cleared. The single bit is shifted from one flip- Chapter 6 Registers and Counters
flop to the next to produce the sequence of timing signals
• Two approaches: (a) ring-counter (b) counter and decoder
6-1 Registers
• k-bit ring counter: k flip-flops to provide k distinguishable states 4-bit register, register with parallel load
6-2 Shift Registers
4-bit shift register, serial shift register, serial adder,
second-form serial adder, universal shift register
6-3 Ripple Counters
4-bit binary ripple counter, count-down counter,
BCD ripple counter, multi-decade BCD counter
6-4 Synchronous Counters
4-bit synchronous binary counter, count-down
counter, up-down binary counter, BCD counter,
binary counter with parallel load
6-5 Other Counters
ring counter, Johnson counter