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Expt 1

Verilog is a hardware description language used to describe digital circuits. It allows concurrent execution and modeling at different levels of abstraction from behavioral to gate level. Key building blocks include modules to describe circuit functions and testbenches to provide test stimuli. The document provides an example of a behavioral, dataflow, and gate-level module for a simple expression, as well as a testbench module to simulate and display the output. Exercises are given to implement an excess-3 to 2421 code converter and 3-bit magnitude comparator at different levels of abstraction using Vivado simulator.

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23 views4 pages

Expt 1

Verilog is a hardware description language used to describe digital circuits. It allows concurrent execution and modeling at different levels of abstraction from behavioral to gate level. Key building blocks include modules to describe circuit functions and testbenches to provide test stimuli. The document provides an example of a behavioral, dataflow, and gate-level module for a simple expression, as well as a testbench module to simulate and display the output. Exercises are given to implement an excess-3 to 2421 code converter and 3-bit magnitude comparator at different levels of abstraction using Vivado simulator.

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f20211662
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‭Experiment 1‬

‭Basics of Verilog HDL‬

‭What is Verilog?‬
‭●‬ ‭Verilog is a Hardware Description Language and not a software programming language.‬
‭●‬ ‭Used to describe the working of digital circuits.‬
‭●‬ ‭In programming, execution starts from the main function and proceeds further.‬
‭●‬ ‭In HDL, concurrent execution of statements is possible.‬
‭●‬ ‭Verilog‬‭allows‬‭the‬‭design‬‭of‬‭circuits‬‭at‬‭a‬‭high‬‭level‬‭of‬‭abstraction‬‭(behavioral‬‭level)‬‭as‬‭well‬‭as‬
‭the lower implementation levels (gate level)‬
‭●‬ ‭Verilog‬ ‭was‬ ‭developed‬ ‭by‬ ‭Gateway‬ ‭Design‬ ‭Automation‬ ‭in‬ ‭1986‬ ‭and‬ ‭was‬‭later‬‭acquired‬‭by‬
‭Cadence in 1990.‬
‭●‬ ‭Designers‬‭can‬‭develop‬‭an‬‭executable‬‭functional‬‭specification‬‭that‬‭describes‬‭the‬‭components'‬
‭exact behavior.‬
‭●‬ ‭Decisions about cost, performance, power, and area can be made earlier.‬
‭●‬ ‭Tools‬ ‭that‬ ‭automatically‬ ‭manipulate‬ ‭the‬‭design‬‭for‬‭verification,‬‭synthesis,‬‭optimization,‬‭and‬
‭bitstream generation are available.‬
‭●‬ ‭Verilog allows the designer to mix and match all levels of abstractions in a design.‬
‭●‬ ‭It‬‭allows‬‭designers‬‭to‬‭talk‬‭about‬‭what‬‭the‬‭hardware‬‭should‬‭do‬‭without‬‭actually‬‭designing‬‭the‬
‭hardware itself.‬
‭●‬ ‭Building blocks in Verilog:‬
‭➔‬ ‭Module:‬
‭Circuit functions are described inside a module.‬
‭It starts with a keyword‬‭module‬‭and ends with a keyword‬‭endmodule‬‭.‬
‭Syntax:‬
‭module‬‭<module_name> (<inputs, outputs>) ;‬
‭……………‬
‭<internal_function>‬
‭………….‬
‭endmodule‬
‭➔‬ ‭Testbench:‬
‭Used for testing the defined circuit function inside the module.‬
‭Provide random input data/stimulus for verifying the correctness of the circuit.‬
‭Define this block separately and do not include it along the module block.‬
‭Syntax:‬
‭module‬‭<testbench_name>;‬
‭…………..‬
‭endmodule‬
‭●‬ ‭Levels of abstraction:‬
‭➔‬ ‭Behavioral/Procedural Level:‬
‭Highest level of abstraction.‬
‭The‬ ‭design‬ ‭at‬ ‭this‬ ‭level‬ ‭is‬ ‭similar‬ ‭to‬ ‭an‬ ‭algorithm‬ ‭and‬ ‭very‬ ‭similar‬ ‭to‬ ‭‘C’‬
‭programming.‬
‭Modules are developed with little consideration of hardware.‬
‭Example: Out = (A.B) + (C.D)‬
‭module‬‭exp1(Out, A, B, C, D);‬
‭input‬‭A, B, C, D;‬
‭output‬‭Out;‬
‭reg‬‭Out;‬
‭always‬‭@(A or B or C or D)‬
‭begin‬
‭if‬‭(A & B)‬
‭Out = 1;‬
‭else‬
‭Out = #10 (C & D);‬
‭end‬
‭endmodule‬
‭➔‬ ‭Dataflow/Functional Level:‬
‭The design specifies how data flows between registers.‬
‭It‬ ‭is‬ ‭useful‬ ‭for‬ ‭designing‬ ‭complex‬ ‭functions‬ ‭that‬ ‭are‬ ‭not‬ ‭realized‬ ‭by‬ ‭gate-level‬
‭modeling.‬
‭Example: Out = (A.B) + (C.D)‬
‭module‬‭exp1(Out, A, B, C, D);‬
‭input‬‭A, B, C,‬‭D;‬
‭output‬‭Out;‬
‭assign‬‭#10 out‬‭= (A & B) | (C & D);‬
‭endmodule‬
‭➔‬ ‭Gate/Structural Level:‬
‭Basic level of modeling.‬
‭The‬ ‭module‬ ‭is‬ ‭implemented‬ ‭in‬ ‭terms‬ ‭of‬ ‭logic‬ ‭gates‬‭(AND,‬‭OR,‬‭NOT)‬‭and‬‭their‬
‭interconnections.‬
‭Example: Out = (A.B) + (C.D)‬
‭module‬‭exp1(Out,‬‭A, B, C, D);‬
‭input‬‭A, B, C,‬‭D;‬
‭output‬‭Out;‬
‭wire‬‭tmp1,tmp2;‬
‭and‬‭u1 (tmp1,‬‭A, B);‬
‭and‬‭u2 (tmp2,‬‭C, D);‬
‭or‬‭#20 (Out, tmp1,‬‭tmp2);‬
‭endmodule‬
‭●‬ ‭Testbench example:‬
‭module‬‭test;‬
‭reg‬‭r1, r2, r3, r4;‬
‭wire‬‭o;‬
‭exp1 e1 (.A(r1), .B(r2), .C(r3), .D(r4), .Out(o));‬
‭initial‬
‭begin‬
‭reg‬‭[3:0] i;‬
‭for‬‭( i = 0; i < 16; i = i + 1)‬
‭begin‬
‭{ r1, r2, r3, r4 } = i [3:0];‬
‭#30‬‭$display‬‭(“r1r2r3r4 = %b%b%b%b, o = %b”, r1, r2,‬‭r3, r4, o);‬
‭end‬
‭end‬
‭endmodule‬

‭Take Home Exercises:‬


‭Note: Xilinx Vivado Simulator has to be used to implement the exercises‬
‭1.‬ ‭Implement an excess-3 to 2421 code conversion using gate-level modeling.‬
‭2.‬ ‭Implement a 3-bit magnitude comparator using the following:‬
‭●‬ ‭Gate level modeling‬
‭●‬ ‭Behavioral modeling‬
‭●‬ ‭Data flow modeling‬

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