Design and Implementation of RAM and

16 Bit ALU using HDL(Hardware Description Language)

Mini Project Submitted for the partial fulfillment of the requirement for the
award of the degree of

Bachelor of Technology
in
Electrical Engineering

Dr. A.P.J. Abdul Kalam Technical University, Lucknow

Submitted by

Shyama Poddar(210091020058)

Under the guidance of

Mr. Naveen Kumar Bind
Assistant Professor,
Electrical Engineering Department

Session: 2023-24 (ODD)

JSS MAHAVIDYAPEETHA
JSS Academy of Technical Education, Noida
Department Of Electrical Engineering
C-20/1, Sector – 62, Noida- 201301
 TABLE OF CONTENTS

Page No.

DECLARATION.......................................................................................................................ii

CERTIFICATE ………............................................................................................................iii

ACKNOWLEDGEMENT…....................................................................................................iv

ABSTRACT…..........................................................................................................................v

INTRODUCTION......................................................................................................................1

COMBINATIONAL CHIP SET-1............................................................................................3

COMBINATIONAL CHIP SET-2...........................................................................................15

SEQUENTIAL CHIP SET………...........................................................................................20

LIST OF ACCESSED RESOURCES……………….............................................................30

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 DECLARATION

I hereby declare that this submission is my own work and that, to the best of my
knowledge and belief, it contains no material previously published or written by
another person nor material which to a substantial extent has been accepted for
the award of any other degree or diploma of the university or other institute of
higher learning except where due acknowledgement has been made in the text.

Signature of Student-:

Student’s Name: Shyama Poddar

Roll No: 2100910200058

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 CERTIFICATE

This is to certify that 5th Semester Mini Project/ Internship Report titled
“Design and Implementation of RAM and 16 Bit ALU using
HDL(Hardware Description Language) ” which is submitted by Shyama
Poddar (2100910200058) in partial fulfillment of the requirement for the award
of degree B. Tech in Department of Electrical Engineering of J.S.S Academy of
Technical Education, Noida, affiliated to Dr. A.P.J. Abdul Kalam University,
Lucknow is a record of the candidates’ own work carried out by them under
my supervision. The matter embodied in this thesis is original and has not been
submitted for the award of any other degree.

Mr Naveen Kumar Bind

Assistant Professor,
Electrical Engineering Department,
JSS Academy of Technical Education, Noida.

Signature of Supervisor

ACKNOWLEDGEMENT
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We have made efforts in this project. However, it would not have
been possible without the kind support and help of many
individuals and organizations.I would like to extend my sincere
thanks to all of them.

We are highly indebted to Dr Sanjeev Kumar Sharma(Head of

department), and Mr. Naveen Kumar Bind(Assistant Professor) for
their guidance and constant supervision as well as for providing
necessary information regarding the project & also for their support
in completing the project.

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 ABSTRACT
An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic
and logical operations. It represents the fundamental component of a computer's
CPU.

RAM is a high-speed, addressable, and volatile memory system that computers

use to store and retrieve data quickly during their operation.

Hardware Description Languages (HDLs) are specialized programming

languages for designing and simulating electronic circuits and systems, aiding
in digital hardware design and verification.

This project, titled "Design and Implementation of 16-bit RAM and ALU,"
delves into the intricacies of creating a robust and efficient memory and
arithmetic logic unit (ALU) system with a focus on a 16-bit architecture. The
primary objective of this endeavor is to develop a reliable Random Access
Memory (RAM) module and Arithmetic Logic Unit, essential components in
digital computing systems.

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 Introduction
The focus of this project is building an ALU chip and RAM chip starting from a nand
gate. To achieve this basic logic gates will be constructed from the nand gate. Using
these basic logic gates, 16 bit variant of the basic logic gates are constructed along
with multiplexor , demultiplexor and their 16 bit variants. Using all these chips, the
ALU is constructed which is an integral part of the Von Neumann computer
architecture.

For the construction of RAM a similar approach is followed , a 1 bit register is

constructed using using a multiplexor and D flip flop. Using this 1 bit register, a 16
bit register is further constructed. From this a RAM8,RAM16,RAM512,RAM4K and
finally a RAM16K module is constructed.

Block diagram for ALU

1
Block diagram for RAM

2
 Combinational Chip Set-1
A typical computer architecture is based on a set of elementary logic gates like And,
Or, Mux, etc., as well as their bit-wise versions And16, Or16, Mux16, etc. (assuming
a 16-bit machine). These gates form the elementary building blocks from which we
will later construct the computer's CPU and RAM.

1. Chip name: Not

Description: Not gate
Functionality: out = not in
HDL Code:

Circuit Representation:

2. Chip name: And

Description: And gate
Functionality: out = 1 if (a == 1 and b == 1)
0 otherwise

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HDL Code:

Circuit Representation:

3. Chip name: Or
Description: Or gate

Functionality: out = 1 if (a == 1 or b == 1)
0 otherwise

HDL Code:

Circuit Representation:

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 4. Chip name: Xor
Description: Xor gate
Functionality: out = not (a == b)
HDL Code:

Circuit Representation:

5. Chip name: Mux

Description: Mux gate

Functionality: for i = 0..15 out[i] = a[i] if sel == 0

b[i] if sel == 1

HDL Code:

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Circuit Representation:

6. Chip name: DMux

Description: DMux gate
Functionality: {a, b} = {in, 0} if sel == 0
{0, in} if sel == 1
HDL Code:

Circuit Representation:

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 7. Chip name: Not16
Description: 16-bit Not gate

Functionality: for i=0..15: out[i] = not in[i]

HDL Code:

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Circuit Representation:

8. Chip name: And16

Description: 16-bit And gate

Functionality: for i = 0..15: out[i] = (a[i] and b[i])

HDL Code:

Circuit Representation:

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 9. Chip name: Or16
Description: 16-bit Or gate

Functionality: for i = 0..15 out[i] = (a[i] or b[i])

HDL Code:

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Circuit Representation:

10.Chip name: Mux16

Description: 16-bit multiplexor

Functionality: for i = 0..15 out[i] = a[i] if sel == 0

b[i] if sel == 1

HDL Code:

11.Chip name: Mux4Way16

Description: 16-bit/4-way mux

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Functionality: * out = a if sel == 00
b if sel == 01
c if sel == 10
d if sel == 11

HDL Code:

Circuit Representation:

12.Chip name: Mux8Way16

Description: 16-bit/8-way mux

Functionality: out = a if sel == 000

b if sel == 001
etc.
h if sel == 111

HDL Code:

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Circuit Representation:

13.Chip name: DMux4Way

Description: 4-way demultiplexor

Functionality:

HDL Code:

Circuit Representation:

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 14.Chip name: DMux8Way

Description: 8-way demultiplexor:

{a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000
{0, in, 0, 0, 0, 0, 0, 0} if sel == 001
{0, 0, 0, 0, 0, 0, 0, in} if sel == 111

Functionality: {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000

{0, in, 0, 0, 0, 0, 0, 0} if sel == 001
etc.
{0, 0, 0, 0, 0, 0, 0, in} if sel == 111
HDL Code:

Circuit Representation:

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14
 Combinational Chip Set-2

1.Chip name: HalfAdder

Description: Half Adder

Functionality: Computes the sum of two bits

HDL Code:

Circuit Representation:

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 2.Chip name: FullAdder
Description: Full Adder
Functionality: Computes the sum of three bits
HDL Code:

Circuit Representation:

3.Chip name: ALU

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Description: Arithmetic Logic Unit
Functionality: * Computes one of the following functions:
* x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y,
* x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs,
* according to 6 input bits denoted zx,nx,zy,ny,f,no.
* In addition, the ALU computes two 1-bit outputs:
* if the ALU output == 0, zr is set to 1; otherwise zr is set to 0;
* if the ALU output < 0, ng is set to 1; otherwise ng is set to 0.
*/

// Implementation: the ALU logic manipulates the x and y inputs

// and operates on the resulting values, as follows:
// if (zx == 1) set x = 0 // 16-bit constant
// if (nx == 1) set x = !x // bitwise not
// if (zy == 1) set y = 0 // 16-bit constant
// if (ny == 1) set y = !y // bitwise not
// if (f == 1) set out = x + y // integer 2's complement addition
// if (f == 0) set out = x & y // bitwise and
// if (no == 1) set out = !out // bitwise not
// if (out == 0) set zr = 1
// if (out < 0) set ng = 1

HDL Code:

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Circuit Representation:

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Sequential Chip Set

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1.Chip name: Bit

Description: 1-bit register

Functionality: 1-bit register:

If load[t] == 1 then out[t+1] = in[t]
else out does not change (out[t+1] = out[t])

HDL Code:

Circuit Representation:

2.Chip name: Register

Description: 16-bit register

Functionality: 16-bit register:

If load[t] == 1 then out[t+1] = in[t]
else out does not change

HDL Code:

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Circuit Representation:

3.Chip name: RAM8

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Description: 16-bit / 8-register memory

Functionality: Memory of 8 registers, each 16 bit-wide. Out holds the value

* stored at the memory location specified by address. If load==1, then
* the in value is loaded into the memory location specified by address
* (the loaded value will be emitted to out from the next time step onward).
*/
HDL Code:

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Circuit Representation:

4.Chip name: RAM64

Description: 16-bit / 64-register memory

Functionality: Memory of 64 registers, each 16 bit-wide. Out holds the value

* stored at the memory location specified by address. If load==1, then
* the in value is loaded into the memory location specified by address
* (the loaded value will be emitted to out from the next time step onward).

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HDL Code:

Circuit Representation:

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25
5.Chip name: RAM512

Description: 16-bit / 512-register memory

Functionality: Memory of 512 registers, each 16 bit-wide. Out holds the value:
- stored at the memory location specified by address. If load==1, then
- the in value is loaded into the memory location specified by address
- (the loaded value will be emitted to out from the next time step onward)

HDL Code:

26
Circuit Representation:

6.Chip name: RAM4K

Description: 16-bit / 4096-register memory

Functionality: Memory of 4K registers, each 16 bit-wide. Out holds the value:

-stored at the memory location specified by address. If load==1, then
-the in value is loaded into the memory location specified by address
(the loaded value will be emitted to out from the next time step onward)

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HDL Code:

Circuit Representation:

7.Chip name: RAM16K

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Description: 16-bit / 16384-register memory

Functionality: Memory of 16K registers, each 16 bit-wide. Out holds the value:
-stored at the memory location specified by address. If load==1, then
-the in value is loaded into the memory location specified by address
(the loaded value will be emitted to out from the next time step onward).
HDL Code:

Circuit Representation:

List of Accessed Resources

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 The Elements of Computing Systems: Building a Modern Computer from First Principles :Book by
Noam Nisan and Shimon Schocken
 DESIGN AND IMPLEMENTATION OF 8 BIT AND 16 BIT ALU USING VERILOG
LANGUAGE MANIT KANTAWALA Dept. of Electronic & Communication Global Institute of
Technology, Jaipur
 A Synthesis Course in Hardware Architecture, Compilers, and Software Engineering :Shimon
Schocken, Noam and Nisan Michal Armoni

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