Physical Design Flow Inputs Floorplan EL Placement en cTS _—_ Post-CTS ee | ee Routing eo Sign-Off Checks a Tape-Out Inputs «© Ubraries ©. Techile (.tf-> Synopsys, tech-lef-> Cadence )+ tt contains all the technology related parameters. Unit Tite info © Unit Height (site row height ) © Unit width { Placement Grid ~ Fill X1 size) + Metal Layer details © Minawidth ‘© Min-Spacing ‘= Metal Pitch + Fat Metal Spacing Table + ViALayer details + MinSpace * Single-Cut Via © Multi-Cut via © TWA (tlut-> Synopsys , captbl or qrctech > Cadence ) * R& Cvalues for each metal & via layer in sq micron ) = CBEST/CWORST/RCWORST/RCBEST/TYPICAL ‘9 Timing / Logical / Power Library (lib or db ) = Itcontains the following details ‘© Timing (in the form of 7x7 table ) © CellRise Delay © CellFall Delay © Output Rise Transition ‘© Output Fall Transition (© Setup/Hold Timing Requirements Power ( in the form of 7x7 table ) © Leakage Power ©. Internal Power © Area (Cell Area) ‘© CCS Library ( More accurate, 2% correlation to actual spice simulation ) ‘© NLOM Library (Less accurate, 7% correlation to actual spice simulation ) © Physical Library (lef / FRAME / NOM model ) = Itcontains the following details © Cell size ( Width x Height ) Allowed Orientations © RO, R180, MX, MY ete + Cell Class © CORE- Standard Cells © BLOCK~Macros © PAD=I0 Pads © PIN Details layer © Direction © Location & size + Obstruction/Routing Blockage Details, "Different Types . Library Exchange Format (Used in Cadence & Siemens/AtopTech ToolsFRAM ~ FRAME View ( Used In Synopsys IC-Compiler } + NDM = New Data Model (Used in Syopsys 1 Compiler 2 & Fusion Compton Netlist (Gate level ) © Design Functionality in Verilog gate level netlist format. 'S0C ( Synopsys Design Constraints - Timing Constraints ) ‘© Clock Definitions * create_clock = create_generated_clock © Clock Attributes. * set_clock_latency ( Not useful for PD Engineers, but + set_clock_uncertainty + set_clock_groups set_sense set_clock_transition set_min_pulse_width group_path © DRV Constraints + set_max_transition = set_max_fanout = set_max_capacitance © Constant Definitions * set_case_analysis, © Path Exceptions = set_multicycle_path + set_false_path = set_disable_timing © Max/Min Delay + set_max_delay + set_min_delay © 1/0 Delay definitions = set_input_delay * set_output_delay = set_load = set_input_transition * set_driving_cell Push-down Floorplan ~ DEF/TCL ( Block shape & IO ports placement } ©. FP DEF—read it using “read_def or defin” commands. © TCL file —Just source it inside the tool shell. 0 fp—read it using “read_floorplan” cmd UPF — Unified Power Format ( If the design contains Low Power Methodologies ) © PG Port & Net details © PG Logical Connection ( connect_pg or globalNetConnect } © Power Domain details ‘+ Multi-Supply ( 0.8V & 1.3V) "ON/OFF ( Using Power-Switches ) Level-Shifter Policies during Synthesis) oo°0 State Retention Cell Pol © PST—Power State Table Scan-DEF ( Needed for scan-chain re-order )© Sean Chain Detalls © Registers belonging to particular scan-chain ECOOEOOHO Below points are for interview purpose Ho HM I tot to Link Library: (Tlming Ib for all the cells used In the design) * RTL/Gate-Level Netlist may contaln hand instantiated std cells and macros. You need to read them Inside tool, so that the tool understands the timing/logical/power Info. Target Library: (Timing lib - Optimization Engine will pick/use the cells from these libs) * During the Opt, the tool would use the cells from these target libs. Sanity Check: Netlist Checks ( cmd : check_design or check_netlist ) © No Floating Inputs or Nets No Multi-Driven Nets No Black-Box or Empty Modules Output connected to P/G No Combinational Feedback Loops No Assign Statements © SDC Checks ( cmd : check_timing ) 0 _Un-constrained Endpoints © Missing Clock Definitions Registers driven by Multiple Clocks © Missing I/O delays © Combinational Loops ary ) ( Not applicable for ICC2 & Fusion Compiler ) © Library Checks ( cmd : check_I ‘0 Check if there is any physical or timing model is missing for the cells. © Library consistency check ( PIN direction should be same across LEF & LIB ) Zero Wire Load Model Timing Check ( Netlist Vs SOC Check ) ‘© cmd : set_zero_interconnect_delay_mode true cmd : report_qor © cmd: report_timing © Make sure your design is meeting setup with zero wire-delay. Netlist Vs Floorplan Checks ( cmd: check_pin_placement ) © Allthe 1/0 ports should’ve assigned physical location. © No1/0 ports short. © No1/O ports near the corners ( Causes Congestion & Routing issues ) ooo ° Floorplan © Goal © Minimize the Die-Size/AreaAvoid the dead-area/void-spaces Minimize the Congestion Minimize the Timing Viol Reduce the wire length Making routing easy © Reduce IR drop ( Better PG Routing } ‘* Floorplan Shape initialization © Read the Push-down FP or manually initialize the shape. © read_def or defin ( DEF format } © source (TCL file ) © read_floorplan or readFPlan (.fp ) © Manually Initialize the shape & place the IO Ports ( bottom-up approach ) ‘+ Macro Placement © Group the Macros based on hierarchy modules. © Fly-line based connectivity analysis. © Data-flow diagram. © Guidelines * Place the Macros around the core/periphery. ‘High Priority: Where no 10 ports present. ‘* Make sure to place the macros where less no of I/O ports present. * Provide more space for routing if more I/O ports are present. * Don’t place any Macros in the middle as it might cause congestion issues. "Place the Macros in middle only if the macro is timing critical. * Add partial (allowed only 30%) blockage to avoid cong around macro. "Take care of Macro Orientations ( Poly should be vertical - 28nm & below ) + Placement Blockages © Add Placement Blockages wherever needed/applicable. ‘Soft Blockage in Macro Channels. * Partial Blockages in notch area. "Hard Blockages if any area needs to be kept empty. ‘+ Perform PG Routing © Establish PG logical connection ( connect_pg, globalNetConnect } © PG Nets~To be Routed. No.of stripes Stripe width Stripe Pitch Follow-pin / Std Cell Rail creation © PGVIA Addition ‘* Floorplan Checks © No Macro Overlaps Macros placed on placement grid No 1/0 ports short 1/0 ports should be present on routing track Clock 10 ports should have NDR (DW-DS) All the Macros and 1/0 ports should have fixed attribute ‘No blocked ports/pins Enough Channel between Macros. At least 1 VDD & VSS stripe should be present in the Macro channel. No PG nets short & opens. Commands ec000 co00 0000000000check_pin_assignment check_legality check_pg_connectivity check_pg_dre check_pg_missing_vias check_Ivs Pre-Place + Goal © Adding Physical cells & Placing Critical logic cells © Endcap ( Avoids cell damage near edges & helps in having a clean NW at the boundaries) © TAP ( Avoids Latch-up violation ) ‘© 1/0 or Boundary buffer ( Improves the I/O signal transition ) © Spare Cells ( Will be used for ECO roll in during re-spin ) Std Cell Placement © Goal °° oo Place all the std cells inside core area. Meet the timing requirements. Reduce the std cell utilization. Reduce the routing congestion. Minimal cell density, pin density and congestion hot-spots Reduce the wire-length ( Global Routing Wires ) Reduce the Power HI Placement Process of placing the unplaced standard cells in the core area. The tool determines the location for all the cells based on the Macro placement. Timing is high priority during the placement. Tool analyzes the timing and optimizes the violating paths. Tool analyzes the routing congestion based on global routing and optimizes it. ‘Area recovery on the paths that are having a huge positive setup slack. + Types of Placement ‘© Timing Driven ( Timing will be High priority, Congestion will be Medium priority ) ° ° ° Congestion Driven ( Timing will be Medium priority, Congestion will be High priority ) Power Driven ( Power will be High priority, others will be Medium priority ) Area Driven ( Area recovery will be High priority, others will be Medium priority ) © Inputs/Checks ° ° ° ° Floorplan Completed DB. Fixed attribute for all the IO Ports, Hard Macros and pre-placed cells. Critical Path Groups if any "= group_path -from -to -weight 10 Placement Blockages ( Add missing blockages & remove if any blockage is unwanted ) Scan-DEF ( Scan-Chain info, required for scan-chain re-ordering ) Bounds, Regions & Groups ( Guide the tool to place the cells in the given area ) Local Cell Density Limits ( Max 90% local density }° ° ° Keen out or Cel Padding (Appt on complex ea ike GAL & ADL. fo reduce the cong Apply the dont_use cell list & dont_touch lst Make sure to follow IP integration guidelines if any. + Placement Steps ° ° Global Placement ( Seed for the detail placement ) * Divides the design into small bin "Places the std cells inside each bin & cells are approximately placed. i.e GRC + Cells are placed module-wise based on the macro placement. = Std cells may or may not legalized. Timing is not analyzed Detail Placement ( Multiple iterations till the goals are met ) = Legalize the cells = Timing Opt = DRVOpt = Congestion Opt + Tie-Cells addition * Scan-chain re-ordering = HENS ( High Fanout Net Synthesis ) «Timing Optimization at Placement stage ° ° © 0000000 In most of the designs approximately 30% of the paths will be timing critical. Timing driven placement with high effort. Incremental Timing Optimization. Allowing LVT cells for optimizations ( <5% of LVT cells ). Create Path groups for critical paths & apply more weightage. Enable the useful-skew while performing timing optimization. Bounds/Regions/Groups, so that the tool would place the cells in the given location. Pre-Place the Critical Logic Cells & Guide the tool. Use magnet placement to pull the cells closer Routing layer promotion for critical nets ‘© Congestion Analysis ° 0000000000 Report the Global-Route based Congestion. ‘Check the Congestion numbers in the report. Visually check the Congestion Map. Visually check the Cell-Density Map. Visually check the Pin-Density Map. Check for wrong macro placement/orientation. Check for any blocked ports/pins. IF1/O ports of BUS are not grouped, can cause congestion. Dense PG Network. Check the Complex Cells ( ? ) ratio in the design. Check the Allowed Metal Layers for Routing, wrong set ig can cause congestion. © Congestion Fixes ° e00000 Perform Congestion-Aware Placement & perform Area-Recovery. ‘Add Partial Placement Blockage to control the cell density. ‘Add Soft Placement Blockages in Macro-Channels. ‘Add Cell Padding to the cells which is causing the congestion. Enable the Scan-Chain Re-Ordering. Understand & use all the congestion related switches in the tool.© Add Route-Guides to guide the routing. © Update global route after timing fixes - It could have reduced congestion too! © QoR/ Quality Check © Zero unplaced cells © No Cell Overlaps © Allthe cells should be legally placed ( on placement grid and row ) © Timing QoR * DRV( Max Tran, Max Cap & Max Fan-out ) "Setup "No Hold Check ( Clock is ideal & skew is 0, won't check hold when clock is ideal ) © Congestion should be under control + Congestion Report ( report_congestion } © Both H& V should be <0.5%. © Max overflow should be <4 ‘+ Check Congestion value for each layer if the design is congested. "Congestion Map ( Highlight & Visually Check ) = Cell-Density Map ( Highlight & Visually Check ) = Pin-Density Map ( Highlight & Visually Check } © Std Cell Utilization growth. = Growth should not be more than 5% to 7%. © Check the Vt % ( Make sure ULVT/LVT are used less ) * Placement Stage Commands # stages that constitute the default flow for the place_opt command © place_opt + Sstages © initial_place © initial_dre * initial_opto © final_place + final_opto. create_placement # To perform coarse/global placement only magnet_placement # To pull the cells closer, so that the timing will be met (© legalize_placement # To perform cell legalization refine_placement # Incremental Opt : refine the placement and minimize congestion report_utilization (To report the utilization ) check_legality -verbose # check the placement legality report_placement group_path -name critical_1 -from regA/CLK -to regB/D -weight 5 = create a group path most violated in the design create_keepout_margin -type hard -outer {0.152 0 0.152 0} [get_lib_cells */*OA*] create_bound -name x -coordinates {0.0 10 10 } [get_cells ~hier xyz] (Bound/Group) report_gor ( Timing & Area Summary ) report_global_timing ( Setup & Hold Summary) report_timing ( Detailed Timing Report ) report_constraint —all_violators ( DRV violations + Others like setup, hold etc ) report_congestion ( To report congestion ) ° e000 0000000cTs + Goal ° ° ° ° ° ‘+ Inputs ° ° ° ° ° ° ° + Flow Reduce the Insertion Delay Meet the Skew Target Reduce the clock cell count Reduce the clock-tree power Reduce the OCV variation Insertion Delay target Skew Target ( Global Skew ) Clock Cells {Like CKBUF or CKINV } Clock Routing Layer { Always Top 2 Metal Layers after PG Routing ) NDR ( Double-Width & Double-Spacing ) + Root-Level NDR + Leaf-Level NDR Clock-Transition ( 10% of clock period } = Root-Level Transition + Leaf-Level Transition Clock-tree exceptions ‘© Float-pin ( Custom Insertion delay setting for the sink) Exclude-Pin ( Exclude the sink pins from skew balancing ) Through-Pin ( Treat the sink pin as not an endpoint ) Stop-pin ( Treat combo cell pins as sink pin ) Inter-Clock Balancing if any. ; | cea ET “Areata cance \ rs foveacock Tea a vnc ee oath at Sema ee eee Types of Clock-tree ° Traditional Clock-Tree { Load Balancing ) ‘© High Insertion Delay due to more logic level in clock path & High Skew. H-Tree Moderate Insertion Delay & Less Skew. Clock-Mesh = Less Insertion Delay & Less Skew. Multi-Point CTSvy * _ Less insertion Delay & Moderate Skew © Fish-Bone Moderate insertion Delay & Moderate Skew = Checks Insertion Delay Skew Clock-cell count Clock-DRV Clock-cell area Std Cell Utilization Timing QoR Clock & Data DRV ( Max Tran, Setup & Hold (We should check for Hold since t ‘+ Min-Pulse Width Violations Congestion should be under control Congestion Report ( report_congestion ) Both H & V should be < 1%. Max overflow should be <5 h layer if the design Is congested. Check Congestion value for eac! light & Visually Check ) light & Visually Check ) & Visually Check } 2000000 : Max Cap & Max Fan-out ) he clock is propagated ) Congestion Map ( Hig! Cell-Density Map ( Hig! + Pin-Density Map ( Highlight Std Cell Utilization growth, Growth should not be more than 29% to 3%. ntial issues which can harm the CTS) opt ( Check if the Design is ready for CTS) vahich will be used while performing CTS) © Commands ‘check_clock_tree ( Check for pote! ‘skew & Clock Transition Targets ) ° ©. check_physical_design -stage pre_clock define_routing_rule ( Create NOR rule, tree options ( Apply Insertion Delay, (Clock Cell Settings } exclude pin ete } set_clock_ (Clock Tree Exceptions like float pin, ° © set clock_tree_references 6 set clock_tree_exceptions 0 clock_opt -only_cts ( Only CTS) o clock_opt ( CTS + Timing Opt) © clock opt -only_psyn ( DRV + Setup Optimization ) 0. set_fix_hold [all_clocks ] ( Enable Hold Fix for all the clock group ) > clock_opt -only_hold_time ( Hold Optimization } © report. clock. tree ( Reports the clock-tree statistics & summary } 5 report clack timing -type latency ~verbose ( Detailed Insertion delay path summary ~type skew verbose ( Detailed Skew report) ) report_clock_timing report_gor ( Timing QoR summary } report_timing report timing -delay_type min ( Reports Hold Timing ) ° ° ° ° Routing «Establishing the actual wiring ( or metal connections) using available metal layers © Pre_requirement © Allcells should be legally placed © No cell overlaps 10© Make sure CTS is done ‘© Timing ( DRV, Setup & Hold ) should be clean ‘© Congestion should be under control e ete ted layers for Routing ( Example : Min Layer ~142, thax Layer ~1A9 | © SI/Cross-talk settings © Order of routing © Special routing/pg routing © Clock routing © Regular Signal nets routing Timing Critical nets first = Rest others next. Types of routing © Global routing = Area is di ‘= Itidentifies the available tracks in each bin "Assign the tracks & layers for nets. "Won't add any Via’s. © Detail routing Add VIAs and completes the net connectivity without worrying ORC’s = Checks for Opens & Shorts, clears the same if found any + Searches for DRC violation and repairs using different routing topology like Detour the net + Change the Layer + Change the VIA type led into smaller bins (GRC) © Checks © Opens and Shorts ‘©. Physical DRC Violations © Timing QoR = Clock & Data DRV ( Max Tran, Max Cap & Max Fan-out ) = Setup & Hold = Min-Pulse Width Violations «Routing Related Commands co check_legality -verbose 0 check_physical_design -stage pre_route_opt ( Check if the Design is ready for Route ) ‘©. all_ideal_nets ( Check for ideal nets in the design ) ©. all-high_fanout -nets -threshold 100 ( Check for High Fanout Nets in the design ) © check 2rt_routability ( Check if there is any potential issues which will harm Routing ) ©. set_ignored_layers -max_routing_layer M8 -min_routing_layer M2 © set_route_zrt_common_options ( Common Routing Settings ) © set_si_options -route_xtalk_prevention true ( Cross-talk Related Settings ) ©. set_delay_calculation_options -routed_clock arnoldi ‘© report_route_zrt_common_options © route_zrt_group ( Route only selected Nets ) © route_zrt_global © route_zrt_track © route_zrt_detail -max_number_iterations 20 © route_zrt_auto ( Performs Global, Track & Detail Route, this is a super command ) © report_gor 11constraint -all_violators timing -delay_tvpe max Taelay_type min { check for ORC violations ) ‘Opens & Shorts ) Routing + Timing Opt ) report report_timing report_timing verify_art_route verify_Ivs ( Check for route_opt ( Performs STA 7 ‘= types of paths ; ae tak (External /Interface Timing } © R2R( Internal Timing ) 9 R20 (External / Interface Timing ) © 120 ( External / Interface Timing ) © Delay © Cell Delay = Depends on ‘© Input Transition Output Load ( Wire/Net Cap + Pin/Gate Capacitance ) © Net Delay ‘= TLU# file will have the R&C values per sq.micron for all layers. © Drive Strength © Multi-Vt Libraries o HVT ~ More Delay, Less Leakage SVI/RVT/NVT - Medium Delay, Medium Leakage ° o Wt ~ Less Delay, High Leakage © ULVT - Very less Delay, Very High Leakage + Example © INV_HVT_X2 (35ps) = INV_SVT_x2 (30ps) © INV_LVT_X2 ( 25ps) * INV_HVT_X4 ( 28ps ) © INV_SVT_X4 ( 24psps ) © INV_LVT_X4 ( 20ps ) «pvr © Process © Voltage © Temperature "Example © SS_OP9V_125C_HVT.lib © SS_OP9V_125¢_svr. © SS_OP9V_125¢_LVTLlib © SS_OP9V_Mm40C_HVT. *SS_OPSV_M40C_SVT.lib © SS_OP9V_M40C_LVT.lib © Clock Skew © Tskew = Tclk.arrival.Capture - Tclk.arrival.aunch © Positive Skew "Helps Setup 12© Setup Analysis: ° Negative Skew Helps Hold = Telkarrival.launch + Te-q + Teombo Data Arrival Time oat ed Time = Tekartval. Capture + Tek period ~Teetup fe-q + Teombo cew +Telk.period ~ Tsetup Data Arrival Tim Data Required Time = TSK Stack = Req Time — Arr Time = RT~AT Example Problem -1: © Teg =200p5 Teombo = 800ps Telk.period = 1ns Tsetup = 250ps Tskew =0, 150ps, 250ps, 300ps Calculate the setup slack. Example Problem -2: ©) Teg =250ps ‘* Teombo = 850ps * Tsetup = 250ps © Tskew = 100ps © Calculate the Clk freq, it shouldn't be violating the setup. © AT:250+850= 1100 RT : 100 + Telk ~ 250 = Telk - 150 Telk — 150 = 1100 => Telk = 1250ps © Cik Freq = 1/1250ps = 800MHz Hold Analysis ‘clk.arrival.Launch + Tc-q + Tcombo Data Arrival Tims Data Required Time = Tclk.arrival.Capture + Thold Data Arrival Time = Tc-q + Tcombo Data Required Time = Tskew + Thold Slack = Arr Time - Req Time =AT - RT Example Problem -1: © Te-q=200ps © Tcombo = 800ps © Takperiod = ans © Thold = 350ps © Tskew = 0, 150ps, 250ps, 300ps * Calculate the Hold slack. 13biel lnciealaea path is one in which data launched from one flop is ° ca ate more than one lock cel to reach to the capture flop. © False Path the actual functional operation of the design, it is possible that certain timing paths are not real or Practically the data never goes through that path, such paths are called False paths. ° 8 0 To removes the timing arc, it does not calculate path delay going through ae, ©. Case Analysis © set_case_analsis: Specifies constant value on @ pin of a cell, or on an input ports. © Clock Uncertainty ©The uncertainty can be used to model various factors that can reduce the effective clock period. These factors can be the clock ter and any other pessimism that one may want to include for timing analysis, © Clock Latency © Source Latency * the delay from the clock source to the clock definition point. © Network Latency . Piet latency is the delay from the clock definition point to the clock pin of a flip- jo © Clock Groups * commands © Report_timing -delay_type max--nosplit -slack_lesser_than 0 -verbose © Report_timing -delay_type min -nosplit -slack_lesser_than 0 -verbose © Report_global_timing © Report_annotated_parasitics © Size_cell instance_name ref_name o Insert_buffer © Report constraints -all_violators © Report_analysis_coverage © Report_bottleneck (© Fix_eco_dre -type max_transition © Fix_eco_timing -type setup -methods size_cell © Set_max_transition 0.3 [current_design] © Report_gor © Write_changes formarticctcl-output outputs/ecot.tcl 14