Advanced Computer Architecture (C5114)

1 Computer architecture is abstracted by its ___. b

a. Instruction
b. Instruction set
c. Organization
d. None of the above

2 Which of the following is a type of computer architecture? C

a) Microarchitecture
b) Harvard Architecture
c) Von-Neumann Architecture
d) All of the mentioned
3 Who developed the basic architecture of computer? C
a)Blaise Pascal
b)Charles Babbage
c)John Von Neumann
d)None of the above
4 Which of the architecture is power efficient? A
a) RISC
b) ISA
c) IANA
d) CISC
5 The IA-32 system follows which of the following design? D
a) CISC
b) SIMD
c) RISC
d) None of the mentioned
6 The VLIW architecture follows _____ approach to achieve parallelism. b
a) SISD
b) MIMD
c) MISD
d) SIMD
7 ________ are the different type/s of generating control signals. d
a) Hardwired
b) Micro-instruction
c) Micro-programmed
d) Both Micro-programmed and Hardwired
8 The small extremely fast, RAM’s all called as ________ d
a) Heaps
b) Accumulators
c) Stacks
d) Cache
9 The small extremely fast, RAM’s all called as ________
a) Heaps
b) Accumulators
c) Stacks
d) Cache
10 The difference in the address and data connection between DRAM’s and c
SDRAM’s is _______
 a) The requirement of more address lines in SDRAM’s
b) The usage of a buffer in SDRAM’s
c) The usage of more number of pins in SDRAM’s
d) None of the mentioned
11 An SIMD computer exploits ___ parallelism. a
a. Spatial
b. Temporal
c. Both a & b
d. None of the above

12 ___ architecture supports the pipelined flow of vectors operands directly from a
the memory to pipelines and then back to memory.
a. Memory to memory
b. Register to memory
c. Memory to register
d. Register to register

13 The term Computer Architecture was coined in ___ by the ‘Chief architects of a
the ___
a. 1974, 360 System
b. 1965, AT & T
c. 1964, IBM System
d. 1984, ENCI System
14 The micro operation that specifies binary operations for strings of bits stored in a
registers
are___________.
A. logic micro operation.
B. shift micro operation.
C. arithmetic micro operation.
D. register transfer micro operation.
15 Pipelining ___ the clock cycle time. a
a. Decreases
b. Increases
c. Stabilizes
d. None of the time

16 The ________ holds the number of words to be transferred to the memory.

A. word count register.
B. address register.
C. control register.
D. program register.
17 The last on the hierarchy scale of memory devices is ______. b
a. Main memory
b. Secondary memory
c. TLB
d. Flash drives
18 ___ hazards arises when an instruction depends on the results of a previous b
instruction in a way that is exposed by the overlapping of instructions in the
pipeline.
a. Structural
 b. Data
c. Control
d. None of the above
19 ___ classification shows the architectural evolution from sequential scalar
computers to vector processors and parallel computers.
a. Von-Neumann’s
b. Nyquist’s
c. Flynn’s
d. None of the above
20 The effectiveness of the cache memory is based on the property of ______ a
A. Locality of reference
B. Memory localization
C. Memory size
D. None of the above
21 PMS stands for
a. Processor-memory switch
b. Program-memory-switch
c. Processor-machine-switch
d. Program-memory-switch
22 ___ hazards arises when an instruction depends on the results of a previous b
instruction in a way that is exposed by the overlapping of instructions in the
pipeline.
a. Structural
b. Data
c. Control
d. None of the above
23 Pipelining yields a reduction in the ___ per instruction. c
a. Fetching Line
b. Executions tine
c. Average execution time
d. None of the above
24 ___ are fast registers for holding the intermediate results. a
a. Latches
b. J.K
c. RS
d. Master slave
25 The cost-performance ratio is a good indicator of ___ quality for small a
changes.
a. Relative
b. Absolute
c. Absolute relative
d. All of the above

26 The ratio which stays constant as performance and cost is increased by equal c
factors is called as-
a. Performance Ratio
b. Cost Ratio
c. Cost-Performance Ratio
d. All of the above
27 The study of architecture covers both ___ and ___. c
a. Evolutional, Revolution
b. IBM System, Revolution
c. Instruction-set architecture, Machine implementation organizations
d. Evolutional, IBM System
28 The number successful accesses to memory stated as a fraction is called as c
_____
a) Access rate
b) Success rate
c) Hit rate
d) Miss rate
29 The number of successful accesses to memory stated as a fraction is called as a
_____.
a. Hit rate
b. Miss rate
c. Success rate
d. Access rate
30 Associate memory can be used to build ___ associative processors. b
a. SISD
b. SIMD
c. MISD
d. MIMD

31 The ________ holds the number of words to be transferred to the memory. a

A. word count register.
B. address register.
C. control register.
D. program register.
32 The associatively mapped virtual memory makes use of _______ a
a. TLB
b. Page table
c. Frame table
d. None of the mentioned
33 The read and write operations usually start at ______ of the sector. d
a. Center
b. Middle
c. From the last used point
d. Boundaries
34 A hard disk with 20 surfaces will have _____ heads. b
a. 10
b. 5
c. 1
d. 20
35 The method used to reduce the maximum number of summands by half is b
_______
a. Fast multiplication
b. Bit-pair recording
c. Quick multiplication
d. None of the mentioned
36 Situations that prevent next instruction in instruction stream, from executing c
 during its designated clock cycle are known
a. Pipe stage
b. Previous stage
c. Hazards
d. Processor cycle
37 Delays arising from use of a load result 1 or 2 cycles after loads, refers as a
a. Data stall
b. Control stall
c. Branch stall
d. Lord Stall
38 Code containing redundant loads, stores, and other operations that might be d
eliminated by an optimizer, is
a. Optimized clock
b. Unoptimized clock
c. Optimized code
d. Unoptimized code
39 The digital information is stored on the hard disk by ____________ b
a. Applying a suitable electric pulse
b. Applying a suitable magnetic field
c. Applying a suitable nuclear field
d. By using optic waves
40 If an exception is raised and the succeeding instructions are executed b
completely, then the processor is said to have ______
a. Exception handling
b. Imprecise exceptions
c. Error correction
d. None of the mentioned
41 Process of letting an instruction move from instruction decode stage into B
execution stage of this pipeline is usually called
a. Canceling
b. Instruction issue
c. Nullifying
d. Branch prediction
42 Sum of contents of base register and sign-extended offset is used as a memory C
address, sum is known as
a. ALU instructions
b. Through put
c. Effective address
d. Load and store instructions
43 When compiler attempts to schedule instructions to avoid hazard; this C
approach is called
a. Compiler
b. Static scheduling
c. Dynamic scheduling
d. Both a and b
44 Exceptions that occur within instructions are usually A
a. Synchronous
b. Asynchronous
c. Pipelined
d. Blocked
45 Each of clock cycles from previous section of execution, becomes a a
a. Pipe stage
b. Previous stage
c. Stall
d. Processor cycle
46 Pipeline overhead arises from combination of pipeline register delay D
a. Hit rate
b. Clock cycle
c. Cycle rate
d. Clock skew
47 If event occurs at same place every time program is executed with same data B
and memory allocation, then event is known as
a. Stalled
b. Synchronous
c. Delayed
d. Asynchronous
48 Load instruction has a delay or latency that cannot be eliminated by A
forwarding, other technique used is
a. Pipeline interlock
b. Deadlock
c. Stall interlock
d. Stall deadlock
49 With separate adder and a branch decision made during ID, there is only a B
a. 1-clock-cycle stall on branches
b. 2-clock-cycles stall on branches
c. 4-clock-cycles stall on branches
d. 3-clock-cycles stall on branches
50 Splitting cache into separate instructions and data caches or by using a set of C
buffers, usually called
a. Cache buffer
b. Data buffer
c. Instruction buffer
d. None of above
51 Simplest scheme to handle branches is to A
a. Flush pipeline
b. Freezing pipeline
c. Depth of pipeline
d. Both a and b
52 Processor without structural hazard is A
a. Faster
b. Slower
c. Have longer clock cycle
d. Have larger clock rate
53 Which processor has a single instruction multiple data stream organization that B
manipulates the common instruction by means of multiple functional units?
a. Attached array processor
b. SIMD array processor
c. Both
d. None
54 Which is used to speed-up the processing: C
 a. Pipeline
b. Vector processing
c. Both
d. None
55 Which type of register holds a single vector containing at least two read ports D
and one write ports
a. Data system
b. Database
c. Memory
d. Vector register
56 Which are the types of array processor? C
a. Attached array processor
b. SIMD array processor
c. Both
d. None
57 Which is a method of decomposing a sequential process into sub operations? A
a. Pipelline
b. CISC
c. RISC
d. Database
58 MIMD stands for: c
a. Multiple input multiple data
b. Memory input multiple data
c. Multiple instruction multiple data
d. Memory instruction multiple data
59 SIMD stands for: D
a. System instruction multiple data
b. Scale instruction multiple data
c. Symmetric instruction multiple data
d. Single instruction multiple data
60 Which control refers to the track of the address of instructions C
a. Data control
b. Register control
c. Program control
d. None of these
61 Both the CISC and RISC architectures have been developed to reduce the C
______
a. Cost
b. Time delay
c. Semantic gap
d. All of the mentioned
62 The iconic feature of the RISC machine among the following is _______ A
a. Reduced number of addressing modes
b. Increased memory size
c. Having a branch delay slot
d. All of the mentioned
63 Which of the following is independent of the address bus? D
a. Secondary memory
b. Main memory
c. Onboard memory
 d. Cache memory
64 If a unit completes its task before the allotted time period, then a
a. It’ll perform some other task in the remaining time
cIts time gets reallocated to different task
b. It’ll remain idle for the remaining time
c. None of the mentioned
65 The fetch and execution cycles are interleaved with the help of ________. C
a. Modification in processor architecture
b. Special unit
c. Clock
d. Control unit
66 The signals that are provided to maintain proper data flow and synchronization A
between the data transmitter and receiver are
a. Handshaking signals
b. Control signals
c. Input signals
d. None of the above
67 ____ register is used for the purpose of controlling the status of each interrupt D
request in parallel priority interrupt
a. Mass
b. Mark
c. Make
d. Mask
68 ______ interrupt method uses register whose bits are set separately by interrupt C
signal for each device
a. Parallel priority interrupt
b. Daisy chaining
c. Serial priority interrupt
d. None of the above
69 For moving string instruction from the register to the memory, the command B
used is
a. MOV
b. MOVS
c. MOS
d. MVS

70 Which unit initiates bus requests on the bus? D

a. Slave
b. controller master
c. striping
d. bus master

71 ingle instruction single data stream (SISD) category is the A

a. uniprocessor category
b. dual processor category
c. quad core category
d. multiple processor

72 The goal of software techniques and hardware techniques is to exploit a

a. Parallelism
 b. Scalability
c. Supervision
d. compatibility

73 The address and data information is typically referred to as the a

a. request payload
b. data load
c. memory
d. message payload

74 Every time during execution time if the event occurs at the same place with the b
same data and memory allocation is known as
a. Asynchronous
b. Synchronous
c. Delayed
d. stalled

75 The duration between the read and the MFC signal is a

a. acess time
b. latency
c. delay
d. cycle time