oe INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR Ba Mid-Spring Semester Examination 2022-23 ion: Session: (FN/AN) ____ Duration: 2 irs. Full Marks: 60, Date of Examin Subject No.: EC: Subject: Basie Electronics Department/Center/Schoot: Electronics and Electrical Communication Engineering Specific charts, graph paper, log book ete., required: No Special Instructions (if any): Ifnot specified, you can assume the temperature to be room temperature (300K) and the thermal voltage Vz (kigT/q) to be 25.9mV Fill in the blanks, []Mark x 5] (a) If base current in a common-emitter npn BIT is 10/4 and the common emitter current gain B is 100, then the collector current is and the emitter current is (b) The common base current gain factor a for the BJT (as given in question I.a above) will be (©) Fora perfect (ideal) diode, the ideality factor (q) is (@) In a pn junction, as the magnitude of reverse bias voliage decreases, the junction capacitance (©) A bandpass filter is constructed by connecting a low pass filter and a high pass filter in series. In this case, the cut-off frequency of the high pass filter should be compared to the low pass filter. 2. (a) Why is there a necessity to dope intrinsic semiconductors? With suitable diagrams, describe the process of doping and explain on the choice of dopant materials. [5 Marks] (0) For a Silicon based pn junction device, working at 50 degrees Celsius, doped at Na = 10"5 cm? in the p region and Np = 10'S cm” in the n region, calculate the built-in potential, if the intrinsic carrier concentration of Silicon at 50 degree Celsius is approximately 5.86 x 10'° cm? [5 Marks} 3. (A) Plot the output waveform for the given cirenit in Fig. 1 and mention the state of individual diodes for one cycle of time period T. Identify the mistake in the circuit if itis to be used for AC to DC conversion, that is, as a rectifier. Draw the correct circuit, Assume silicon diodes (V, =0.7V). [3+2 Marks} (B) Design a de power supply to obtain 12V that may deliver a current of 120 mA to the load and produces an output with ripples not greater than 5%. Sketch various intermediate blocks including rectifier and filter circuit to achieve 12 V (unregulated power supply) and calculate the average (DC) value of the output voltage. Assume silicon diodes with cut-in voltage ¥, = 0.7V, as given in Fig. 1 (10 marks]actine vohage 220V (rms), 50H? Sinusoidal input waveform All diodes wee silicon diodes (V,=0.7 V) Figure | 4, (A) A Zener voltage regulator is to have # nominal output voltage of 10 V. The specified Zener diode has a rating of | W, has a 10 V drop at , = 25 mA, and has a Zener resistance of r, = SA. ‘The input power supply has a nominal value of Vps = 20V and can vary by £25%. The output toad current is to vary between f,, = 0 and 20 mA. (a) If the minimum Zener current is to be Iz, = 5 mA, determine the required Rj. (b) Determine the maximum variation in output voltage. (c) Determine the percent load and source regulation, [24244 Marks] (B) Sketch the steady-state output voltage v, versus time for each circuit in Fig. 2 with the input voltage given in the left hand side of Fig. 2. Assume ¥, = 0 and assume the RC time constant is large. [3+3 Marks} fo) tb) Figure 2 (C) Consider the circuits shown in Fig. 3. Each diode cut-in voltage is Vy = 0.7 V. Plot vg versus v; over the range ~10V < v; < +10V for both the circuits in Fig. 3 for(i) Vp = 5V and (ii) Vp = ~5V. [3+3 Marks] fa) (o) Figure 35. The circuit shown in Fig. 4is designed such that Icg = 0.8 mA and Vorg = 2V. Assume Ry = 1k and B=80, (0) Determine the values of Re and Ry [242 Marks] (b) IF is changed to 120, determine the percentage variation in Je and Veeg: [2+2 Marks} (c] With proper labelling, plot the loadiine and the variation in Q-point as fis changed from 80 to 120. {2 Marks} 45V Re Ry Figure 4