Roll No…………………..

Dr. B. R. Ambedkar National Institute of Technology, Jalandhar

B. Tech. (Electronics and Communication) - 3rd Semester
ECPC–203, Electronic Devices and Circuits
End Semester Examination, Dec 2021
Duration: 02 Hours Max. Marks: 40 Date: 09th Dec 2021

Marks Distribution & Mapping of Questions with Course Outcomes (COs)

Question 1(a) 2(a) 3(a) 4(a) 5(a) 6(a) 7(a) 8(a)
Number 1(b) 2(b) 3(b) 4(b) 5(b) 6(b) 7(b) 8(b)
Marks 5 5 5 5 5 5 5 5
CO No. 1 2 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4
Learning 2 2, 3 2, 3 2, 3 2, 3 2, 3 2 2
Level

Note:
1. Attempt all the questions.
2. Write the answers in hard copy (on A4 sheet) using blue/black pen with
your signature on top left and page number on top right corner of each
page of the answer booklet.
3. The time allowed for writing examination is 02 hours. Extra 15 minutes
are allowed for preparing the PDF file of Answer Booklet and
submitting it.
4. Follow the instructions regarding submission of answer booklet as
issued by the examination section.

Q 1(a). Given an intrinsic semiconductor specimen, state two physical (2)

processes for increasing its conductivity. Explain briefly.

Q 1(b). Radiation falls on a semiconductor specimen, which is (3)

uniformly illuminated, and a steady state is reached. At t=0, the
light is turned-off.
(i) Sketch the minority carrier concentration as a function of
time for t ≥ 0.
(ii) Define all symbols in the equation describing your sketch.

Q 2(a). Plot the hole current, the electron current, and the total current (2)
as a function of distance on both sides of a p-n junction.
Indicate the transition region.

Q 2(b). (i). The resistivities of the P-region and N-region of a p-n (3)
junction diode are 6 Ω-cm and 4 Ω-cm respectively. Calculate

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 the contact potential V0 and potential energy barrier E0.
(ii). If the doping densities of both P and N-regions are doubled,
determine V0 and E0. Given that q = 1.6×10-19, ni = 2.5×1013/cm3,
µp = 1800 cm2/V-s, µn = 3800 cm2/V-s, and VT = 0.026 V at
300ºK.

Q 3(a). Sketch vo for each network of Fig. 1 for the input shown. Would (3)
it be a good approximation to consider the diode to be ideal for
both configurations? Why?

Fig. 1

Q 3(b). Design a voltage regulator that will maintain an output voltage (2)
of 20 V across a 1-k load with an input that will vary between
30 and 50 V. That is, determine the proper value of Rs and the
maximum current IZM.

Q 4(a). What is Early effect or Base-width modulation? Explain with (2)

the help of a diagram.

Q 4(b). (i). Find the transistor currents in the circuit of Fig. 2(a). A Si-transistor (3)
with β = 100, and ICO = 20 nA is under consideration.
(ii). Repeat Part (i), if a 2K emitter resistor is added to the
circuit as shown in Fig. 2(b). Find the region of operation of the
transistor in both the cases.

Fig. 2

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Q 5(a). Draw the circuit of a CE transistor configuration, and give its h- (2)
parameter model.

Q 5(b). The transistor of Fig. 3 is connected as a common emitter amplifier, (3)

and the h-parameters are given in Table-1. If RL = 10K, and RS = 1K,
find the various gains and the input and output impedances.

Table-1

Fig. 3

Q 6(a). Why we DC bias the transistor? How many DC biasing (2)

techniques are there? Which one is the best DC biasing
technique and why?

Q 6(b). For the circuit as shown in Fig. 4, find the values of I C, VC, VE, and (3)
VCE.

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 Fig. 4

Q 7(a). Draw the characteristics of an n-channel JFET for VGS ≤ 0V, and show (2)
how the current IDS becomes 0 mA at |VGS| = |VP|.

Q 7(b). Draw and differentiate between the transfer characteristics of an n- (3)

channel depletion MOSFET and an enhancement MOSFET.

Q 8(a). Why the feedback is required in amplifiers? Draw the block (3)
diagrams of all the types of feedbacks used in amplifiers. What
is the effect of negative feedback on gain and bandwidth?

Q 8(b). Draw the circuit diagram of an RC-phase shift oscillator, and (2)
explain its working.