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K L Deemed to be University
Department of Computer Science and Engineering-Honors -- KLAZIZ
Course Handout
2023-2024, Even Sem
Course Title :DIGITAL DESIGN AND COMPUTER ARCHITECTURE
Course Code :23EC1202
L-T-P-S Structure : 3-0-2-0
Pre-requisite :
Credits :4
Course Coordinator :ABHISHEK KUMAR SHRIVASTAVA
Team of Instructors :
Teaching Associates :
Syllabus :CO 1: Combinational Digital Logic Circuits: Boolean Algebra, Digital Logic SOP/POS representation and
optimization techniques. Adders, Subtractors, Multiplexers, De-Multiplexers, Decoder, Encoder, Concept of
Reversible Gates. Programmable Logic Devices: PROM, PAL, and PLA design. Implementation of CPLD
(Macrocells) and FPGA (CLB/LUT) based digital logic modules and their applications. CO-2: Design of Sequential
and Memory Circuits: Latches and Flip-Flops, Modeling of memory ,registers and Shift registers, Timing and
sequence control modules using Asynchronous/Synchronous counters, Ring and Johnson counter as timing and
control units. Random Access Memory (RAM) and Memory decoding. CO-3: Basic Computer Architecture and
Instructions: Features of Micro Computer, Operands, Addressing modes, Instruction formats, Machine cycle,
Instruction sets, subroutine call and return mechanisms. Instruction set architectures - CISC and RISC architectures.
Hardwired realization vs micro-programmed realization, multi-cycle implementation, Instruction level parallelism,
instruction pipelining and pipeline hazards. CO-4: Memory Architecture and I/O Organization Storage systems,
introduction to memory hierarchy: importance of temporal and spatial locality; main memory organization, cache
memory: address mapping, block size, replacement, and store policies. Virtual Memory System: page table and TLB.
External storage; IO fundamentals: handshaking, buffering, programmed IO, interrupt driven IO.
Text Books :1. Computer System Architecture by M. Moris Mano, 3rd edition published by Pearson/PHI 2.
Fundamentals of Digital Logic with Verilog HDL by Stephen Brown and ZvonkoVranesic, 3rd edition, Published by
Mc Graw Hill
Reference Books :1. Computer Organization and Design by DA Patterson and JL Hennessy,4th edition published by
Morgan Kaufmann Publisher 2. Computer Organization and Architecture, by W. Stalling published by PHI.
Web Links :[1]. https://nptel.ac.in/courses/117106086 [2]. https://archive.nptel.ac.in/courses/106/105/106105163/
MOOCS :[1]. https://www.edx.org/learn/design/harvey-mudd-college-digital-design [2]. https://ocw.mit.edu/courses/
6-823-computer-system-architecture-fall-2005/ [3]. https://www.coursera.org/learn/digital-systems

COURSE OUTCOMES (COs):

Blooms
CO Taxonomy
Course Outcome (CO) PO/PSO
NO Level
(BTL)
Build the combinational and programmable digital logic circuits using
CO1 PSO1,PO1,PO2 3
logic gates and optimization methods
CO2 Construct the sequential and memory circuits using flip-flops PSO1,PO1,PO2 3
CO3 Able to organize computer architecture and instructions sequence PSO1,PO1,PO2 3
CO4 Model the Memory Architecture and I/O Organization modules PO2,PSO1,PO1 3

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Develop and analyze of computer architecture modules using basic

CO5 PSO1,PO1,PO3,PO5 4
combinational, sequential and memory logics

COURSE OUTCOME INDICATORS (COIs)::

Outcome Highest
COI-1 COI-2
No. BTL
Btl-2 Btl-3
This course provides a comprehensive Understanding this course delves into the realm
introduction to digital logic design and Boolean of Programmable Read-Only Memory (PROM),
algebra, covering fundamental concepts, Programmable Array Logic (PAL), and
CO1 3 representation techniques, and optimization Programmable Logic Array (PLA), exploring
strategies. Students will gain a deep their design principles and applications.
understanding of the building blocks of digital Students will gain a comprehensive
systems and learn how to design and optimize understanding of these devices and their role in
circuits for various applications. modern digital systems.
Btl-2 Btl-3
This course empowers the knowledge by The study of Ring and Johnson counters
Studying latches, flip-flops, memory modeling, provides insights into advanced sequential
and register design provides essential control mechanisms, improving students'
knowledge for creating digital circuits with understanding of precise timing in digital
CO2 3
effective data storage. Exploring timing controls systems. Exploring Random Access Memory
using asynchronous/synchronous counters (RAM) and Memory decoding enhances their
ensures accurate sequencing, while knowledge of efficient data storage and
understanding shift registers enables serial data retrieval, contributing to the optimization of
manipulation. digital circuits.
Btl-2 Btl-3
Understanding an in-depth exploration of This course explores Instruction Set
microcomputer architecture and programming, Architectures (ISAs), covering Complex
covering essential features, addressing modes, Instruction Set Computing (CISC) and Reduced
instruction formats, machine cycles, and Instruction Set Computing (RISC). Topics
CO3 3
subroutine call and return mechanisms. Students include hardwired versus micro-programmed
will gain a comprehensive understanding of the realization, multi-cycle implementations, and
fundamental components that constitute a advanced concepts like instruction-level
microcomputer system and the intricacies of parallelism, instruction pipelining, and pipeline
programming at the machine level. hazard mitigation.
Btl-3
The study of virtual memory system,
Btl-2 emphasizing page tables and TLBs for
Understanding the storage systems and memory streamlined virtual-to-physical memory
hierarchy, students delve into the hierarchical mapping. The course further covers external
organization of computer memory. Emphasizing storage and IO fundamentals, including
CO4 3
the significance of temporal and spatial locality, handshaking, buffering, programmed IO, and
this provides students with a thorough interrupt-driven IO. This provides a
understanding of the principles governing comprehensive grasp of organizational elements
efficient data retrieval in computer architecture. in virtual memory systems and principles
governing Input/Output operations in computer
architecture.
Btl-4
Students analyze practical applications in digital
CO5 4 electronics, including tasks like LED control,
car security system design, and participant
selection using multiplexers. They also analyze

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projects involving digital displays, random

number generators, and computational
processing systems. These hands-on activities
offer a valuable opportunity for students to
analyze and understand the diverse applications
of digital electronics in real-world scenarios.

PROGRAM OUTCOMES & PROGRAM SPECIFIC OUTCOMES (POs/PSOs)

Po
Program Outcome
No.
Engineering Knowledge:Apply the knowledge of mathematics, science, engineering fundamentals, and an
PO1
engineering specialization to the solution of complex engineering problems.
Problem Analysis: Identify, formulate, review research literature, and analyse complex engineering problems
PO2 reaching substantiated conclusions using first principles of mathematics, natural sciences and engineering
sciences
Design/Development of Solutions: Design solutions for complex engineering problems and design system
PO3 components or processes that meet the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations
Conduct Investigations of Complex Problems:Use research-based knowledge and research methods including
design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid
PO4
conclusions for complex problems that cannot be solved by straightforward application of knowledge, theories
and techniques applicable to the engineering discipline.
Modern Tool Usage:Create, select, and apply appropriate techniques, resources, and modern engineering and
PO5 IT tools including prediction and modelling to complex engineering activities with an understanding of the
limitations.
The Engineer and Society:Apply reasoning informed by the contextual knowledge to assess societal, health,
PO6 safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering
practice.
Environment and Sustainability:Understand the impact of the professional engineering solutions in societal and
PO7
environmental contexts, and demonstrate the knowledge of, and need for sustainable development
Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
PO8
engineering practice
Individual and Team Work: Function effectively as an individual, and as a member or leader in diverse teams,
PO9
and in multidisciplinary settings.
Communication:Communicate effectively on complex engineering activities with the engineering community
PO10 and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions
Project Management and Finance: Demonstrate knowledge and understanding of the engineering and
PO11 management principles and apply these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
Life-long Learning: Recognize the need for, and have the preparation and ability to engage in independent and
PO12
lifelong learning in the broadest context of technological change.
PSO1 An ability to design and develop software projects as well as Analyze and test user requirements.
PSO2 An Ability to gain working Knowledge on emerging software tools and technologies.

Lecture Course DELIVERY Plan:

Teaching-
Book No[CH
Sess.No. CO COI Topic Learning EvaluationComponents
No][Page No]
Methods

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Teaching-
Book No[CH
Sess.No. CO COI Topic Learning EvaluationComponents
No][Page No]
Methods
End Semester Exam,SEM-
1 CO1 COI-1 Course Handout NA Chalk,PPT,Talk
EXAM1,SEM-EXAM2

T BOOK [1],
End Semester
2 CO1 COI-1 Introduction, Boolean Algebra CH 2, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
1-24

Digital Logic SOP/POS T BOOK [1],

ALM,End Semester
3 CO1 COI-1 representation and optimization CH 2, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
techniques 25-37

T BOOK [1],
End Semester
4 CO1 COI-1 Adders, Subtractors CH 2, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
38-42

End Semester
T BOOK [1],
Exam,Home
5 CO1 COI-1 Multiplexers, De-Multiplexers CH 6, Page no Chalk,PPT,Talk
Assignment,SEM-
303-314
EXAM1

T BOOK [1],
End Semester
6 CO1 COI-1 Decoder, Encoder CH 2, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
314-317

T BOOK [1],
End Semester
7 CO1 COI-2 Introduction to PLD's, PROM CH 2, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
87-92

End Semester
T BOOK [1],
Exam,Home
8 CO1 COI-2 PAL and PLA design CH 2, Page no Chalk,PPT,Talk
Assignment,SEM-
47-49
EXAM1

Implementation of CPLD T BOOK [1],

ALM,End Semester
9 CO1 COI-2 (Macrocells) based digital logic CH 2, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
modules and their applications 92-101

FPGA (CLB/LUT) based digital T BOOK [1],

ALM,End Semester
10 CO1 COI-2 logic modules and their CH 2, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
applications 102-108

T BOOK [1],
End Semester
11 CO1 COI-2 Concept of Reversible Gates CH 2, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
62-63

T BOOK [1],
Introduction to sequential circuits, End Semester
12 CO2 COI-1 CH 2, Page no Chalk,PPT,Talk
Latches Exam,SEM-EXAM1
497-499

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Teaching-
Book No[CH
Sess.No. CO COI Topic Learning EvaluationComponents
No][Page No]
Methods

T BOOK [1],
End Semester
13 CO2 COI-1 Flip-Flops CH 2, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
499-502

T BOOK [1],
Modeling of memory and End Semester
14 CO2 COI-1 CH 2, Page no Chalk,PPT,Talk
registers Exam,SEM-EXAM1
68-71

T BOOK [1],
ALM,End Semester
15 CO2 COI-1 Shift registers CH 5, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
160 - 165

Timing and sequence control T BOOK [1],

End Semester
16 CO2 COI-2 modules using Asynchronous CH 5, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
counters 155

Timing and sequence control T BOOK [1],

End Semester
17 CO2 COI-2 modules using Synchronous CH 5, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
counters 156

End Semester
T BOOK [1],
Ring counter as timing and Exam,Home
18 CO2 COI-2 CH 5, Page no Chalk,PPT,Talk
control units Assignment,SEM-
157-158
EXAM1

T BOOK [1],
Johnson counter as timing and ALM,End Semester
19 CO2 COI-2 CH 5, Page no Chalk,PPT,Talk
control units Exam,SEM-EXAM1
159-161

End Semester
T BOOK [1],
Exam,Home
20 CO2 COI-2 Random Access Memory (RAM) CH 5, Page no Chalk,PPT,Talk
Assignment,SEM-
609 - 610
EXAM1

T BOOK [1],
End Semester
21 CO2 COI-2 Memory decoding CH 5, Page no Chalk,PPT,Talk
Exam,SEM-EXAM1
611

T BOOK [1],
Introduction, Features of Micro End Semester
22 CO3 COI-1 CH 5, Page no Chalk,PPT,Talk
Computer Exam,SEM-EXAM2
123 - 126

End Semester
T BOOK [1],
Operands, Addressing modes, Exam,Home
23 CO3 COI-1 CH 5, Page no Chalk,PPT,Talk
Instruction formats Assignment,SEM-
186 - 190
EXAM2

24 CO3 COI-1 Machine cycle, Instruction sets T BOOK [1], Chalk,PPT,Talk ALM,End Semester

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Teaching-
Book No[CH
Sess.No. CO COI Topic Learning EvaluationComponents
No][Page No]
Methods
CH 7, Page no
Exam,SEM-EXAM2
174-179

T BOOK [1],
subroutine call and return End Semester
25 CO3 COI-1 CH 7, Page no Chalk,PPT,Talk
mechanisms Exam,SEM-EXAM2
213-220

T BOOK [1],
Instruction set architectures - ALM,End Semester
26 CO3 COI-2 CH 7, Page no Chalk,PPT,Talk
CISC and RISC architectures Exam,SEM-EXAM2
262

T BOOK [1],
Hardwired realization vs micro- End Semester
27 CO3 COI-2 CH 7, Page no Chalk,PPT,Talk
programmed realization Exam,SEM-EXAM2
282-285

T BOOK [1],
End Semester
28 CO3 COI-2 Multi-cycle implementation CH 7, Page no Chalk,PPT,Talk
Exam,SEM-EXAM2
286-288

T BOOK [1],
End Semester
29 CO3 COI-2 Instruction level parallelism CH 9, Page no Chalk,PPT,Talk
Exam,SEM-EXAM2
310-315

End Semester
T BOOK [1],
Instruction pipelining and Exam,Home
30 CO3 COI-2 CH 9, Page no Chalk,PPT,Talk
pipeline Hazards Assignment,SEM-
316-320
EXAM2

T BOOK [1],
End Semester
31 CO4 COI-1 Introduction, Storage systems CH 12, Page Chalk,PPT,Talk
Exam,SEM-EXAM2
no 445

End Semester
Introduction to memory T BOOK [1],
Exam,Home
32 CO4 COI-1 hierarchy: Importance of temporal CH 12, Page Chalk,PPT,Talk
Assignment,SEM-
and spatial locality no 446-448
EXAM2

T BOOK [2],
ALM,End Semester
33 CO4 COI-1 Main memory organization CH 12, Page Chalk,PPT,Talk
Exam,SEM-EXAM2
no 448-452

T BOOK [2],
Cache memory: address mapping, End Semester
34 CO4 COI-1 CH 12, Page Chalk,PPT,Talk
Block size Exam,SEM-EXAM2
no 462-465

T BOOK [2],
End Semester
35 CO4 COI-1 Replacement, and Store policies CH 12, Page Chalk,PPT,Talk
Exam,SEM-EXAM2
no 466-469

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Teaching-
Book No[CH
Sess.No. CO COI Topic Learning EvaluationComponents
No][Page No]
Methods

End Semester
T BOOK [2],
Virtual memory system: page Exam,Home
36 CO4 COI-1 CH 12, Page Chalk,PPT,Talk
table and TLB Assignment,SEM-
no 469-476
EXAM2

T BOOK [2],
End Semester
37 CO4 COI-1 External storage CH 12, Page Chalk,PPT,Talk
Exam,SEM-EXAM2
no 478

T BOOK [2],
IO fundamentals: handshaking, ALM,End Semester
38 CO4 COI-2 CH 11, Page Chalk,PPT,Talk
buffering Exam,SEM-EXAM2
no 392-396

T BOOK [2],
Programmed IO, Interrupt driven End Semester
39 CO4 COI-2 CH 11, Page Chalk,PPT,Talk
IO Exam,SEM-EXAM2
no 402-407

Lecture Session wise Teaching – Learning Plan

SESSION NUMBER : 1

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
--- NOT
Discussion on Course Objectives, Course Outcomes and Course
20 2 PPT APPLICABLE
outcome Indicators.
---
--- NOT
20 Discussion on Evaluation Plan 2 PPT APPLICABLE
---
--- NOT
5 Summary & Conclusion 2 Talk APPLICABLE
---

SESSION NUMBER : 2

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 1 Talk APPLICABLE

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---
Sketching &
20 Introduction 2 PPT
Drawing
Sketching &
20 Boolean Algebra 2 PPT
Drawing
Sketching &
5 Summary & Conclusion 2 PPT
Drawing

SESSION NUMBER : 3

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
Sketching &
20 Digital Logic SOP/POS representation 2 PPT
Drawing
Sketching &
20 Optimization techniques 2 PPT
Drawing
Sketching &
5 Summary & Conclusion 2 PPT
Drawing

SESSION NUMBER : 4

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 PPT APPLICABLE
---
Sketching &
20 Half Adder, Full adder 2 PPT
Drawing
Sketching &
20 Half subtractor, Full subtractor 2 PPT
Drawing
Sketching &
5 Summary & Conclusion 2 PPT
Drawing

SESSION NUMBER : 5

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---

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Sketching &
20 Multiplexers 2 PPT
Drawing
Sketching &
20 De-Multiplexers 2 PPT
Drawing
Sketching &
5 Summary & Conclusion 2 PPT
Drawing

SESSION NUMBER : 6

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
Sketching &
20 Decoder 2 PPT
Drawing
Sketching &
20 Encoder 2 PPT
Drawing
Sketching &
5 Summary & Conclusion 2 PPT
Drawing

SESSION NUMBER : 7

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE
---
Sketching &
20 Introduction to PLD's 3 PPT
Drawing
Sketching &
20 PROM 3 PPT
Drawing
Sketching &
5 Summary & Conclusion 3 PPT
Drawing

SESSION NUMBER : 8

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE
---

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Sketching &
20 Programmable Array Logic (PAL) 3 PPT
Drawing
Sketching &
20 programmable logic array (PLA) 3 PPT
Drawing
Sketching &
5 Summary & Conclusion 3 PPT
Drawing

SESSION NUMBER : 9

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE
---
Sketching &
20 CPLD Structure 3 PPT
Drawing
Sketching &
20 Implementation of CPLD (Macrocells) 3 PPT
Drawing
Sketching &
5 Summary & Conclusion 3 PPT
Drawing

SESSION NUMBER : 10

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE
---
Sketching &
20 FPGA Structure 3 PPT
Drawing
Sketching &
20 Implementation of FPGA based digital logic modules 3 PPT
Drawing
Sketching &
5 Summary & Conclusion 3 PPT
Drawing

SESSION NUMBER : 11

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE
---

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Sketching &
20 Types of Reversible Gates 3 PPT
Drawing
Sketching &
20 Operation of Reversible Gates 3 PPT
Drawing
Sketching &
5 Summary & Conclusion 3 PPT
Drawing

SESSION NUMBER : 12

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 PPT APPLICABLE
---
Problem-Based
20 Sequential circuits - Introduction 2 PPT
Learning
Problem-Based
20 Concept of latches 2 PPT
Learning
Problem-Based
5 Summary & Conclusion 2 PPT
Learning

SESSION NUMBER : 13

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
Problem-Based
5 Attendance 2 PPT
Learning
Problem-Based
20 Concept of flip-flops 2 PPT
Learning
Problem-Based
20 Types of flip-flops 2 PPT
Learning
Problem-Based
5 Summary & Conclusion 2 PPT
Learning

SESSION NUMBER : 14

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
Problem-Based
20 Modeling of memory 2 PPT
Learning

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Problem-Based
20 Registers 2 PPT
Learning
Problem-Based
5 Summary & Conclusion 2 PPT
Learning

SESSION NUMBER : 15

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
Problem-Based
20 Types of Shift registers 2 PPT
Learning
Problem-Based
20 Operation of shift Registers 2 PPT
Learning
Problem-Based
5 Summary & Conclusion 2 PPT
Learning

SESSION NUMBER : 16

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE
---
Design
20 Asynchronous counters 3 PPT
Thinking
Design
20 Asynchronous counters - Timing and sequence control modules 3 PPT
Thinking
Design
5 Summary & Conclusion 3 PPT
Thinking

SESSION NUMBER : 17

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE
---
Design
20 Synchronous counters 3 PPT
Thinking

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Design
20 Synchronous counters - Timing and sequence control modules 3 PPT
Thinking
Design
5 Summary & Conclusion 3 PPT
Thinking

SESSION NUMBER : 18

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE
---
Design
20 Description - Ring counter 3 PPT
Thinking
Design
20 Operation of Ring counter 3 PPT
Thinking
Design
5 Summary & Conclusion 3 PPT
Thinking

SESSION NUMBER : 19

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE
---
Design
20 Introduction - Johnson counter 3 PPT
Thinking
Design
20 Operation - Johnson counter 3 PPT
Thinking
Design
5 Summary & Conclusion 3 PPT
Thinking

SESSION NUMBER : 20

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE
---
Design
20 Random Access Memory (RAM) - Introduction 3 PPT
Thinking

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Application of Random Access Memory (RAM) in computer Design

20 3 PPT
architecture Thinking
Design
5 Summary & Conclusion 3 PPT
Thinking

SESSION NUMBER : 21

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 PPT APPLICABLE
---
Design
20 Memory decoding introduction 2 PPT
Thinking
Design
20 Application of Memory decoding in computer architecture 2 PPT
Thinking
Design
5 Summary & Conclusion 2 PPT
Thinking

SESSION NUMBER : 22

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
One minute
20 Introduction of computer architecture 2 PPT
paper
One minute
20 Features of Micro Computer 2 PPT
paper
One minute
5 Summary & Conclusion 2 PPT
paper

SESSION NUMBER : 23

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 1 Talk APPLICABLE
---
One minute
10 Operands 2 PPT
paper

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One minute
20 Addressing modes 2 PPT
paper
One minute
10 Instruction formats 2 PPT
paper
One minute
5 Summary & Conclusion 2 PPT
paper

SESSION NUMBER : 24

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
One minute
20 Machine cycle 2 PPT
paper
One minute
20 Instruction sets 2 PPT
paper
One minute
5 Summary & Conclusion 2 PPT
paper

SESSION NUMBER : 25

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
One minute
20 Types of subroutines 2 PPT
paper
One minute
20 subroutine call and return mechanisms 2 PPT
paper
One minute
5 Summary & Conclusion 2 PPT
paper

SESSION NUMBER : 26

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
One minute
5 Attendance 3 PPT
paper
One-Minute
20 CISC architecture 3 PPT
Paper

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One-Minute
20 RISC architecture 3 PPT
Paper
One-Minute
5 Summary & Conclusion 3 PPT
Paper

SESSION NUMBER : 27

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE
---
One-Minute
20 Hardwired realization 3 PPT
Paper
One-Minute
20 micro-programmed realization 3 PPT
Paper
One-Minute
5 Summary & Conclusion 3 PPT
Paper

SESSION NUMBER : 28

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 PPT APPLICABLE
---
One-Minute
20 Concept of Multi-cycle implementation 3 PPT
Paper
One-Minute
20 Application of Multi-cycle implementation 3 PPT
Paper
One-Minute
5 Summary & Conclusion 3 PPT
Paper

SESSION NUMBER : 29

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE
---
One minute
20 Instruction level Pipelining 3 PPT
paper

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One minute
20 Instruction level parallelism 3 PPT
paper
One minute
5 Summary & Conclusion 3 PPT
paper

SESSION NUMBER : 30

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE
---
One minute
20 Instruction pipelining 3 PPT
paper
One minute
20 pipeline Hazards 3 PPT
paper
One minute
5 Summary & Conclusion 3 PPT
paper

SESSION NUMBER : 31

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
Think / Pair /
20 Introduction 2 PPT
Share
Think / Pair /
20 Storage systems 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 32

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 PPT APPLICABLE
---
Think / Pair /
20 Introduction to memory hierarchy 2 PPT
Share

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Think / Pair /
20 Importance of temporal and spatial locality 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 33

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
Think / Pair /
20 Introduction of Main memory organization 2 PPT
Share
Think / Pair /
20 Description - Main memory organization 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 34

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
Think / Pair /
20 Cache memory: address mapping 2 PPT
Share
Think / Pair /
20 Concept of Block size 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 35

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
Think / Pair /
20 Concept of Replacement in Memory 2 PPT
Share

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Think / Pair /
20 Concept of Store policies 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 36

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
Think / Pair /
20 Virtual memory system: page table 2 PPT
Share
Think / Pair /
20 Virtual memory system: TLB 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 37

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
Think / Pair /
20 External storage types 2 PPT
Share
Think / Pair /
20 External storage description 2 PPT
Share
Think / Pair /
5 Summary & Conclusion 2 PPT
Share

SESSION NUMBER : 38

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE
---
Think / Pair /
20 IO fundamentals: Handshaking 3 PPT
Share

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Think / Pair /
20 IO fundamentals: Buffering 3 PPT
Share
Think / Pair /
5 Summary & Conclusion 3 PPT
Share

SESSION NUMBER : 39

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 3 Talk APPLICABLE
---
Think / Pair /
20 Programmed IO 3 PPT
Share
Think / Pair /
20 Interrupt driven IO 3 PPT
Share
Think / Pair /
5 Summary & Conclusion 3 PPT
Share

Tutorial Course DELIVERY Plan: NO Delivery Plan Exists

Tutorial Session wise Teaching – Learning Plan

No Session Plans Exists

Practical Course DELIVERY Plan:

Tutorial
Session Topics CO-Mapping
no

1 Introduction session to laboratory CO5

2 Controlling LEDs with Universal Logic Gates CO5

3 Combinational Circuit Based Car Security System CO5

4 Participant selection in Competitions Using Multiplexer CO5

5 Digital Display of the Department Name using 7-segment decoder CO5

6 Random Number Generator for Gaming Using D-Flip- flop CO5

7 Digital Unlocking System using Shift Register CO5

8 Design of Computational Processing System for Arithmetic and Logical Operations CO5

9 Implementation of Information Transmission System CO5

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Tutorial
Session Topics CO-Mapping
no

10 Development of Instruction Processing System from Fetching to Execution CO5

11 Implementation of Cache Memory CO5

12 Choice Based Control of Vending Machine CO5

13 Implementation of 3-Stage Pipelining CO5

Practical Session wise Teaching – Learning Plan

SESSION NUMBER : 1

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE
---
--- NOT
40 Introduction to logisim 4 PPT APPLICABLE
---
--- NOT
40 Introduction to hardware components 4 PPT APPLICABLE
---
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE
---

SESSION NUMBER : 2

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE
---
--- NOT
20 Description - Controlling LEDs with Universal Logic Gates 4 PPT APPLICABLE
---
--- NOT
30 Implementation - Controlling LEDs with Universal Logic Gates 4 PPT APPLICABLE
---

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--- NOT
30 Results & Discussion 4 PPT APPLICABLE
---
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE
---

SESSION NUMBER : 3

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE
---
--- NOT
20 Description - Combinational Circuit Based Car Security System 4 PPT APPLICABLE
---
--- NOT
Implementation - Combinational Circuit Based Car Security
30 4 PPT APPLICABLE
System
---
--- NOT
30 Results & Discussion 4 PPT APPLICABLE
---
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE
---

SESSION NUMBER : 4

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE
---
--- NOT
Description - Participant selection in Competitions Using
20 4 PPT APPLICABLE
Multiplexer
---
--- NOT
Implementation - Participant selection in Competitions Using
30 4 PPT APPLICABLE
Multiplexer
---
--- NOT
30 Results & Discussion 4 PPT APPLICABLE
---
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE
---

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SESSION NUMBER : 5

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE
---
--- NOT
Description - Digital Display of the Department Name using 7-
20 4 PPT APPLICABLE
segment decoder
---
--- NOT
Implementation - Digital Display of the Department Name using
30 4 PPT APPLICABLE
7-segment decoder
---
--- NOT
30 Results & Discussion 4 PPT APPLICABLE
---
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE
---

SESSION NUMBER : 6

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE
---
--- NOT
Description - Random Number Generator for Gaming Using D-
20 4 PPT APPLICABLE
Flip- flop
---
--- NOT
Implementation - Random Number Generator for Gaming Using
30 4 PPT APPLICABLE
D-Flip- flop
---
--- NOT
30 Results & Discussion 4 PPT APPLICABLE
---
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE
---

SESSION NUMBER : 7

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods

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--- NOT
10 Attendance 4 PPT APPLICABLE
---
--- NOT
20 Description - Digital Unlocking System using Shift Register 4 PPT APPLICABLE
---
--- NOT
30 Implementation - Digital Unlocking System using Shift Register 4 PPT APPLICABLE
---
--- NOT
30 Results & Discussion 4 PPT APPLICABLE
---
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE
---

SESSION NUMBER : 8

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE
---
--- NOT
Description of Computational Processing System for Arithmetic
20 4 PPT APPLICABLE
and LogicalOperations
---
--- NOT
Implementation of Computational Processing System for
30 4 PPT APPLICABLE
Arithmetic andLogical Operations
---
--- NOT
30 Results & Evaluation 4 PPT APPLICABLE
---
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE
---

SESSION NUMBER : 9

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE
---
--- NOT
20 Description of Information Transmission System 4 PPT APPLICABLE
---

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--- NOT
30 Implementation of Information Transmission System 4 PPT APPLICABLE
---
--- NOT
30 Results & Evaluation 4 PPT APPLICABLE
---
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE
---

SESSION NUMBER : 10

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 3 PPT APPLICABLE
---
--- NOT
Description of Instruction Processing System from Fetching to
20 3 PPT APPLICABLE
Execution
---
--- NOT
Description of Instruction Processing System from Fetching to
30 3 PPT APPLICABLE
Execution
---
--- NOT
30 Results & Evaluation 3 PPT APPLICABLE
---
--- NOT
10 Summary & Conclusion 3 PPT APPLICABLE
---

SESSION NUMBER : 11

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 3 PPT APPLICABLE
---
--- NOT
20 Description of Cache Memory 3 PPT APPLICABLE
---
--- NOT
30 Implementation of Cache Memory 3 PPT APPLICABLE
---
--- NOT
30 Results & Evaluation 3 PPT APPLICABLE
---

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--- NOT
10 Summary & Conclusion 3 PPT APPLICABLE
---

SESSION NUMBER : 12

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 Attendance 4 PPT APPLICABLE
---
--- NOT
20 Description of Choice Based Control of Vending Machine 4 PPT APPLICABLE
---
--- NOT
30 Implementation of Choice Based Control of Vending Machine 4 PPT APPLICABLE
---
--- NOT
30 Results & Evaluation 4 PPT APPLICABLE
---
--- NOT
10 Choice Based Control of Vending Machine 4 PPT APPLICABLE
---

SESSION NUMBER : 13

No Session Outcomes are mapped

Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
10 ATTENDANCE 4 PPT APPLICABLE
---
--- NOT
30 Demonstration of 3-Stage Pipelining 4 PPT APPLICABLE
---
--- NOT
50 Implementation of 3-Stage Pipelining, Results & Evaluation 4 PPT APPLICABLE
---
--- NOT
10 Summary & Conclusion 4 PPT APPLICABLE
---

Skilling Course DELIVERY Plan: NO Delivery Plan Exists

Skilling Session wise Teaching – Learning Plan

No Session Plans Exists

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WEEKLY HOMEWORK ASSIGNMENTS/ PROBLEM SETS/OPEN ENDEDED PROBLEM-SOLVING EXERCISES etc:

Assignment Assignment
Week Topic Details co
Type No
Weekly 2. Design a random number
5 Homework 2 D - Flip flops generator for gaming using D- CO2
Assignments flipflops
Weekly
1. Design a Digital Unlocking
6 Homework 2 Shift Registers CO2
System using Shift Register
Assignments
1. Define operands in the
context of computer
instructions. What are the
different types of operands
commonly used in assembly
Weekly
language programming? 2.
7 Homework 3 ALP, Hazards CO3
Explain the concept of pipeline
Assignments
hazards. What are data hazards,
control hazards, and structural
hazards, and how do they
impact the smooth execution of
instructions in a pipeline?
1. Define a machine cycle and
break down the components,
including fetch, decode,
Weekly
execute, and store. 2. Explore
9 Homework 3 Instruction cycle & CISC, RISC CO3
and contrast the architectural
Assignments
features and design
philosophies of RISC and CISC
architectures.
1. Provide examples of real-
world scenarios where temporal
locality is exhibited. How does
the repeated use of certain data
within a short time frame
Weekly benefit from the concept of
10 Homework 4 Page Table temporal locality? 2. Describe CO4
Assignments the typical structure of a page
table. What information is
stored in the page table entries,
and how does the operating
system use this information
during address translation?
1. Draw and explain the
operation of 4:1 Mux and 1:4
Weekly demux. 2. How do AND gates
2 Homework 1 Multiplexer and Demultiplexer PLD's and OR gates contribute to the CO1
Assignments implementation of
combinational logic functions in
PAL and PLA devices?
Weekly 1. Compare and contrast the
11 Homework 4 Main memory & Handshaking characteristics and CO4
Assignments functionalities of main memory

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in a computer system. 2. How

does handshaking facilitate
communication between
devices in a computer system?
1. Optimize the following 3-
variable Boolean function:
Weekly
F(A,B,C)=Σ(1,2,4,6) using
3 Homework 1 K-Maps & FPGA, CPLD's CO1
Karnaugh Maps. 2. Sketch the
Assignments
digital logic modules of FPGA
and CPLD
1. Explore the applications of
Ring Counters in digital
systems. How are they utilized
in various scenarios, and what
advantages do they offer over
Weekly
other types of counters? 2.
4 Homework 2 Counters and Memories CO2
Differentiate between volatile
Assignments
and non-volatile memory. Why
is RAM considered volatile, and
how does this characteristic
influence its usage in a
computer system?

COURSE TIME TABLE:

Hour 1 2 3 4 5 6 7 8 9
Day Component
Theory --- H-S6 H-S6,H-S9 H-S1 H-S1 H-S2 -- -- ---
Tutorial --- -- -- -- -- -- -- -- ---
Mon H-S4,H- H-S4,H-
Lab --- -- -- -- -- -- ---
S4 S4
Skilling --- -- -- -- -- -- -- -- ---
Theory H-S8 H-S8 H-S9 --- --- -- -- --- ---
Tutorial -- -- -- --- --- -- -- --- ---
Tue H-S3,H- H-S3,H-
Lab -- -- -- --- --- --- ---
S3 S3
Skilling -- -- -- --- --- -- -- --- ---
H-S2,H-
Theory H-S1 H-S4 H-S3,H-S4 -- -- H-S2 -- ---
S8
Tutorial -- -- -- -- -- -- -- -- ---
Wed
H-S7,H- H-S7,H- H-S5,H- H-S5,H-
Lab -- -- -- -- ---
S7 S7 S5 S5
Skilling -- -- -- -- -- -- -- -- ---
Theory --- --- --- -- -- H-S6 -- -- ---
Tutorial --- --- --- -- -- -- -- -- ---
Thu H-S9,H- H-S9,H- H-S1,H- H-S1,H-
Lab --- --- --- -- ---
S9 S9 S1 S1
Skilling --- --- --- -- -- -- -- -- ---

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H-S4,H-S5,H-
Theory -- -- H-S3 H-S3 --- -- -- ---
S7
Tutorial -- -- -- -- -- --- -- -- ---
Fri
H-S8,H- H-S2,H- H-S2,H-
Lab H-S8 H-S8 -- -- --- ---
S8 S2 S2
Skilling -- -- -- -- -- --- -- -- ---
H-S5,H- H-S5,H-
Theory --- --- --- --- -- H-S9 ---
S7 S7
Tutorial -- -- --- --- --- --- -- -- ---
Sat
H-S6,H- H-S6,H-
Lab -- -- --- --- --- --- ---
S6 S6
Skilling -- -- --- --- --- --- -- -- ---
Theory -- -- -- -- -- -- -- -- --
Tutorial -- -- -- -- -- -- -- -- --
Sun
Lab -- -- -- -- -- -- -- -- --
Skilling -- -- -- -- -- -- -- -- --

REMEDIAL CLASSES:

Supplement course handout, which may perhaps include special lectures and discussions that would be planned, and
schedule notified according

SELF-LEARNING:

Assignments to promote self-learning, survey of contents from multiple sources.

S.no Topics CO ALM References/MOOCS

DELIVERY DETAILS OF CONTENT BEYOND SYLLABUS:

Content beyond syllabus covered (if any) should be delivered to all students that would be planned, and schedule
notified accordingly.
Advanced Topics, Additional Reading, Research
S.no CO ALM References/MOOCS
papers and any

EVALUATION PLAN:

Evaluation Evaluation Weightage/ Duration

Assessment Dates CO1 CO2 CO3 CO4 CO5
Type Component Marks (Hours)
End End Weightage 24 6 6 6 6
Semester Semester Max
100
07.05.2024 180
25 25 25 25
Summative Exam Marks
Evaluation Lab End Weightage 16 16
Total= 40 Semester Max 07.05.2024 120
% Exam 50 50
Marks
In Semester in Weightage 15 11.03.2024,12.03.2024,13.03.2024 90 7.5 7.5

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Exam-I Max
50 25 25
Marks
Semester Weightage 15 7.5 7.5
Summative Semester in
Max 29.04.2024,30.04.2024,01.05.2024 90
Evaluation Exam-II 50 25 25
Total= 38 Marks
% Lab In Weightage 8 8
Semester Max 01.04.2024 100
Exam 50 50
Marks
Weightage 8 2 2 2 2
ALM Max 22.01.2024,01.05.2024 50
20 5 5 5 5
In Marks
Semester Lab Weightage 7 7
Formative Weekly Max 22.01.2024,01.05.2024 100
Evaluation exercise 75 75
Marks
Total= 22
Home Weightage 7 1.75 1.75 1.75 1.75
%
Assignment
Max 22.01.2024,01.05.2024 50
and 28 7 7 7 7
Textbook Marks

ATTENDANCE POLICY:

Every student is expected to be responsible for regularity of his/her attendance in class rooms and laboratories, to
appear in scheduled tests and examinations and fulfill all other tasks assigned to him/her in every course
In every course, student has to maintain a minimum of 85% attendance to be eligible for appearing in Semester end
examination of the course, for cases of medical issues and other unavoidable circumstances the students will be
condoned if their attendance is between 75% to 85% in every course, subjected to submission of medical certificates,
medical case file and other needful documental proof to the concerned departments

DETENTION POLICY :

In any course, a student has to maintain a minimum of 85% attendance and In-Semester Examinations to be eligible for
appearing to the Semester End Examination, failing to fulfill these conditions will deem such student to have been
detained in that course.

PLAGIARISM POLICY :

Supplement course handout, which may perhaps include special lectures and discussions

COURSE TEAM MEMBERS, CHAMBER CONSULTATION HOURS AND CHAMBER VENUE DETAILS:

Supplement course handout, which may perhaps include special lectures and discussions
Chamber
Delivery Sections Chamber Chamber Signature of
Consultation
Name of Faculty Component of of Consultation Consultation Course
Timings for each
Faculty Faculty Day (s) Room No: faculty:
day
9-MA,4-
Thirupathaiah Kola L - - - -
MA
4-A,9-A,
Thirupathaiah Kola P - - - -
5-B
ABHISHEK 1-MA,7-
L - - - -
SHRIVASTAVA MA

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ABHISHEK 1-A,2-B,
P - - - -
SHRIVASTAVA 7-A
PRADEEP
1-B,6-B,
KUMAR GOUD P - - - -
7-B
NADIKUDA
Anil Kumar Budati L 2-MA - - - -
Anil Kumar Budati P 2-A - - - -
8-MA,3-
Badavath Rao L - - - -
MA
Badavath Rao P 8-A,3-A - - - -
Sachin Trankatwar L 5-MA - - - -
4-B,5-A,
Sachin Trankatwar P - - - -
9-B
AMIT
L 6-MA - - - -
SHRIVASTAVA
AMIT 8-B,6-A,
P - - - -
SHRIVASTAVA 3-B

GENERAL INSTRUCTIONS

Students should come prepared for classes and carry the text book(s) or material(s) as prescribed by the Course Faculty
to the class.

NOTICES

Most of the notices are available on the LMS platform.

All notices will be communicated through the institution email.

All notices concerning the course will be displayed on the respective Notice Boards.

Signature of COURSE COORDINATOR

(ABHISHEK KUMAR SHRIVASTAVA)

Signature of Department Prof. Incharge Academics & Vetting Team Member

Department Of CSE-Honors

HEAD OF DEPARTMENT:

Approval from: DEAN-ACADEMICS

(Sign with Office Seal) [object HTMLDivElement]

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