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DPCO Regulations

The document outlines the objectives and units of a course on digital principles and computer organization. The objectives are to analyze and design combinational and sequential circuits, understand computer fundamentals and architecture, and study processor design, memory, and I/O interfacing. The 5 units cover combinational logic, synchronous sequential logic, computer fundamentals, processor design, and memory and I/O.

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0% found this document useful (0 votes)
61 views6 pages

DPCO Regulations

The document outlines the objectives and units of a course on digital principles and computer organization. The objectives are to analyze and design combinational and sequential circuits, understand computer fundamentals and architecture, and study processor design, memory, and I/O interfacing. The 5 units cover combinational logic, synchronous sequential logic, computer fundamentals, processor design, and memory and I/O.

Uploaded by

Poovizhi Balan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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REGULATION 2021

CS3351 DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION LT PC


3024
COURSE OBJECTIVES:
 To analyze and design combinational circuits.
 To analyze and design sequential circuits
 To understand the basic structure and operation of a digital computer.
 To study the design of data path unit, control unit for processor and to familiarize with the
hazards.
 To understand the concept of various memories and I/O interfacing.
UNIT I COMBINATIONAL LOGIC 9
Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary Adder –
Subtractor – Decimal Adder - Magnitude Comparator – Decoder – Encoder – Multiplexers -
Demultiplexers
UNIT II SYNCHRONOUS SEQUENTIAL LOGIC 9
Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables, Triggering
of FF, Analysis and design of clocked sequential circuits – Design – Moore/Mealy models,
state minimization, state assignment, circuit implementation - Registers – Counters.
UNIT III COMPUTER FUNDAMENTALS 9
Functional Units of a Digital Computer: Von Neumann Architecture – Operation and
Operands of Computer Hardware Instruction – Instruction Set Architecture (ISA): Memory
Location, Address and Operation – Instruction and Instruction Sequencing – Addressing
Modes, Encoding of Machine Instruction – Interaction between Assembly and High Level
Language.
UNIT IV PROCESSOR 9
Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired
Control, Microprogrammed Control – Pipelining – Data Hazard – Control Hazards.
UNIT V MEMORY AND I/O 9
Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping and
Replacement Techniques – Virtual Memory – DMA – I/O – Accessing I/O: Parallel and Serial
Interface – Interrupt I/O – Interconnection Standards: USB, SATA
45 PERIODS
PRACTICAL EXERCISES: 30 PERIODS
1. Verification of Boolean theorems using logic gates.
2. Design and implementation of combinational circuits using gates for arbitrary functions.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture
COURSE OUTCOMES:
At the end of this course, the students will be able to:
CO1 : Design various combinational digital circuits using logic gates
CO2 : Design sequential circuits and analyze the design procedures
CO3 : State the fundamentals of computer systems and analyze the execution of an
instruction
CO4 : Analyze different types of control design and identify hazards
CO5 : Identify the characteristics of various memory systems and I/O communication
TOTAL: 75 PERIODS
TEXT BOOKS:
1. M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the Verilog
HDL, VHDL, and System Verilog”, Sixth Edition, Pearson Education, 2018.
2. David A. Patterson, John L. Hennessy, “Computer Organization and Design, The
Hardware/Software Interface”, Sixth Edition, Morgan Kaufmann/Elsevier, 2020.
REFERENCES:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer
Organization and Embedded Systems”, Sixth Edition, Tata McGraw-Hill, 2012.
2. William Stallings, “Computer Organization and Architecture – Designing for
Performance”, Tenth Edition, Pearson Education, 2016.
3. M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016.
REGULATION 2017
CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN LT PC
4004
OBJECTIVES:
• To design digital circuits using simplified Boolean functions
• To analyze and design combinational circuits
• To analyze and design synchronous and asynchronous sequential circuits
• To understand Programmable Logic Devices
• To write HDL code for combinational and sequential circuits
UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 12
Number Systems - Arithmetic Operations - Binary Codes- Boolean Algebra and Logic Gates
- Theorems and Properties of Boolean Algebra - Boolean Functions - Canonical and Standard
Forms - Simplification of Boolean Functions using Karnaugh Map - Logic Gates – NAND
and NOR Implementations.
UNIT II COMBINATIONAL LOGIC 12
Combinational Circuits – Analysis and Design Procedures - Binary Adder-Subtractor -
Decimal Adder - Binary Multiplier - Magnitude Comparator - Decoders – Encoders –
Multiplexers - Introduction to HDL – HDL Models of Combinational circuits.
UNIT III SYNCHRONOUS SEQUENTIAL LOGIC 12
Sequential Circuits - Storage Elements: Latches , Flip-Flops - Analysis of Clocked
Sequential Circuits - State Reduction and Assignment - Design Procedure - Registers and
Counters - HDL Models of Sequential Circuits.
UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC 12
Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow
Tables – Race-free State Assignment – Hazards.
UNIT V MEMORY AND PROGRAMMABLE LOGIC 12
RAM – Memory Decoding – Error Detection and Correction - ROM - Programmable Logic
Array – Programmable Array Logic – Sequential Programmable Devices.
TOTAL : 60 PERIODS
OUTCOMES:
On Completion of the course, the students should be able to:
 Simplify Boolean functions using KMap
 Design and Analyze Combinational and Sequential Circuits
 Implement designs using Programmable Logic Devices
 Write HDL code for combinational and Sequential Circuits
TEXT BOOK:
1. M. Morris R. Mano, Michael D. Ciletti, “Digital Design: With an Introduction to the
Verilog HDL, VHDL, and SystemVerilog”, 6th Edition, Pearson Education, 2017.
REFERENCES:
1. G. K. Kharate, Digital Electronics, Oxford University Press, 2010
2. John F. Wakerly, Digital Design Principles and Practices, Fifth Edition, Pearson
Education, 2017.
3. Charles H. Roth Jr, Larry L. Kinney, Fundamentals of Logic Design, Sixth Edition,
CENGAGE Learning, 2013
4. Donald D. Givone, Digital Principles and Designǁ, Tata Mc Graw Hill, 2003.

REGULATION 2013
CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN LT PC
3003
OBJECTIVES:
The student should be made to:
 Learn the various number systems.
 Learn Boolean Algebra
 Understand the various logic gates.
 Be familiar with various combinational circuits.
 Be familiar with designing synchronous and asynchronous sequential circuits.
 Be exposed to designing using PLD
UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 9
Review of Number Systems – Arithmetic Operations – Binary Codes – Boolean Algebra and
Theorems – Boolean Functions – Simplification of Boolean Functions using Karnaugh Map
and Tabulation Methods – Logic Gates – NAND and NOR Implementations.
UNIT II COMBINATIONAL LOGIC 9
Combinational Circuits – Analysis and Design Procedures – Circuits for Arithmetic
Operations, Code Conversion – Decoders and Encoders – Multiplexers and Demultiplexers –
Introduction to HDL – HDL Models of Combinational circuits.
UNIT III SYNCHRONOUS SEQUENTIAL LOGIC 12
Sequential Circuits - Storage Elements: Latches , Flip-Flops - Analysis of Clocked
Sequential Circuits - State Reduction and Assignment - Design Procedure - Registers and
Counters - HDL Models of Sequential Circuits.
UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC 12
Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow
Tables – Race-free State Assignment – Hazards.
UNIT V MEMORY AND PROGRAMMABLE LOGIC 12
RAM – Memory Decoding – Error Detection and Correction - ROM - Programmable Logic
Array – Programmable Array Logic – Sequential Programmable Devices.
TOTAL : 60 PERIODS
OUTCOMES:
On Completion of the course, the students should be able to:
 Simplify Boolean functions using KMap
 Design and Analyze Combinational and Sequential Circuits
 Implement designs using Programmable Logic Devices
 Write HDL code for combinational and Sequential Circuits
TEXT BOOK:
1. M. Morris R. Mano, Michael D. Ciletti, “Digital Design: With an Introduction to the
Verilog HDL, VHDL, and SystemVerilog”, 6th Edition, Pearson Education, 2017.
REFERENCES:
1. G. K. Kharate, Digital Electronics, Oxford University Press, 2010
2. John F. Wakerly, Digital Design Principles and Practices, Fifth Edition, Pearson
Education, 2017.
3. Charles H. Roth Jr, Larry L. Kinney, Fundamentals of Logic Design, Sixth Edition,
CENGAGE Learning, 2013
4. Donald D. Givone, Digital Principles and Designǁ, Tata Mc Graw Hill, 2003.

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