CAMBRIDGE INSTITUTE OF TECHNOLOGY

K.R. PURAM, BENGALURU-560036

Department of Computer Science & Engineering Department of CSE/ISE/AI&ML

DD & CO (BCS302) Preparatory exam Question Bank

1) State the duality principle of Boolean algebra with an example.

2) Write the basic theorems and postulates of Boolean algebra and prove them.

3) Simplify the following Boolean functions to a minimum number of literlas. F( x,y ) = x(x’+y),
F(A,B) = --------

4) Find the complement of the following functions: F1 = A’B+AC, F2 = ------- F3= ---------

5) Draw the Graphic symbols and truth table for digital logic gates.

6) Show that AND and OR functions are Commutative and Associative.

7) Show that NAND and NOR functions are Commutative and but not Associative.

8) a)Explain Positive and Negative logic with examples. b)Show the the following by means of truth
tables: i) Positive logic ------ gate is a negative logic ------- gate

9)Demonstrate the validity of the following identities/theorems by means of truth tables:

i)Reduce the following Boolean expressions to indicated number of literals. I

ii)Determine the complement of F(x,y,z) = ------------and show that F.F’ = 0 and F + F’ = 1.

10)What is K- map ? Explan two, three and four variable K-Maps with examples.

11) Explain the don’t care condition in K Map with an example.

12) Explain the NAND and NOR implementation of circuits with examples.

13)Show Boolean function F (A,B,C) = ---------- with i) AND, OR and inverter gates iii) NAND Gates ii)
NOR gates.

14)Solve the following Boolean functions using K – Map and write the circuit for simplified circuit
using NAND gates. F(A,B,C,D) = A’BC +AB’ + ACD’+ ---- +-----+-------

15)Solve the following Boolean functions using K – Map and write the circuit for simplified circuit
using NOR gates. i) F(A,B,C,D) = ∑ m( , , , , ) + d(, , , , ,)
 16)Solve the following Boolean functions using K – Map and write the circuit for simplified circuit
using NOR gates. F(A,B,C,D) = A’BC +AB’ + ACD’+ ---- +-----+-------

MODULE-2

17.What is a combinational circuit ? Explain the procedure to obtain the output of a combinational
circuit with an example.

18. Design Decimal to binary encoder.

19. Design a BCD-to-excess-3 code converter.

20. Design a Full adder circuit.

21. Explain a 4 bit binary adder circuit with an example.

22. Explain Four-bit adder–subtractor (with overflow detection)

23. Explain Logic diagram of carry lookahead generator.

24. Design a combinational circuit with three inputs and one output. (a) Write the Boolean functions for
the four outputs in terms of the input variables. (b)* If the circuit is described in a truth table, how many
rows and columns would there be in the table?

25. An ABCD-to-seven-segment decoder is a combinational circuit that converts a decimal digit in BCD to
an appropriate code for the selection of segments in an indicator used to display the decimal digit in a
familiar form. The seven outputs of the decoder (a, b, c, d, e, f, g) select the corresponding segments in
the display. The numeric display chosen to represent the decimal digit is shown . Using a truth table and
Karnaugh maps, design the BCD-to-seven-segment decoder using a minimum number of gates. The six
invalid combinations should result in a blank display.

26. Design the following combinational circuit : (a) converts a four-bit Gray code to a bit four-bit binary
number. (b) full-subtractor (c) Full Subtractor

27. Design verilog HDL to implement Two-to-Four-line decoder

28. Design veilog program to implement types of De-Multiplexers.

29. Explain the fallowing terms with examples

a)Predefined buffers and invertors

b) User defined buffers and invertors

30. Show the dataflow description of 4-bit magnitude comparator.

31. Build verilog HDL code for Four-bit-adder.

32. List and explain VHDL operators and predefined VHDL data types.

MODULE 4
33. Draw the arrangement of a single bus structure and explain memory mapped I/O and I/O mapped I/O
with examples.

34. What are the three MECHANISMS USED FOR INTERFACING I/O-DEVICES?

35.What is an interrupt? Explain the transfer of program control through the use of interrupts with an
example

36.Explain interrupt hardware. / Explain how interrupt requests from several IO devices can be
communicated to a processor through a single INTR line.

37.Explain the following terms w r. to interrupt i) Interrupt service routine(ISR) ii) Interrupt latency iii)
enabling and disabling of interrupts.

38.Explain in detail, the situations where a number of devices capable of initiating interrupts are
connected to the processor? How to resolve the problems? /Explain following methods of handling
interrupts from multiple devices. i) i)Interrupt nesting/priority structure ii) ii)Vectored interrupt iii)
iii)Simultaneous requests/Daisy chain technique.

39.Explain following w. r.to DMA i) DMA controllers in a computer system. ii) Registers in a DMA
interface.

40.What is bus arbitration? Explain different approaches to bus arbitration.

41.Explain Centralized bus arbitration with diagrams.

42.Explain Distributed bus arbitration with examples.

43.Draw the connection of memory to the processor and explain basic concepts.

44. Explain with diagram the memory hierarchy with respect to speed, size and cost.

45. What is cache memory. Explain the use and operation of cache memory with a diagram.

46. Explain direct mapping with an example.

47. Explain associative mapping with an example.

48. Explain set-associative mapping with an example.

49. A program is to be run on a computer that has an instruction cache organized in the direct mapped
manner and that has t Main Memory Size 64K words, Cache size 1K words and Block size 128 word.
Determine the following: i)Number of bits in the TAG, BLOCK and WORD fields in main memory
address. ii) Number of bits in the main memory address.

50. A program is to be run on a computer that has an instruction cache organized in the Associative
mapped manner and that has the Main Memory Size 64K words, Cache size 1K words and Block size 128
word. Determine the following: i)Number of bits in the TAG and WORD fields in main memory address.
ii) Number of bits in the main memory address.
51. A block -set -associative cache consists of a total of 64 blocks divided into 4 block sets. The main
memory contains 4096 blocks, each consisting of 128 word. Determine: i)Number of bits in the TAG,
SET and WORD fields in main memory address. ii) Number of bits in the main memory address.

52 A computer system has a main memory consisting of 1M 16 bit words. It also has a 4K word cache
organized in the block set associative manner, with 4 blocks per set and 64 word per block. Determine:
i)Number of bits in the TAG, SET and WORD fields in main memory address. ii) Number of bits in the
main memory address.

53. A computer system uses 16-bit memory addresses. It has a 2K-byte cache organized in a direct-
mapped manner with 64 bytes per cache block. Assume that the size of each memory word is 1 byte. i.
Calculate the number of bits in each of the Tag, Block, and Word fields of the memory address.

Module-5

54. Draw the Main hardware components of a processor and explain the steps needed to execute an
instruction.

55. Draw and explain the single-bus organization of the data path inside a processor.

56. Explain with an example, the register transfer in single bus organization/ Explain a sequence of steps
in which data are transferred from one register to another with an example.

57. Explain with an example, how a processor performs arithmetic or logic operations and store the result
in a processor register.

58. Explain the control signals of MDR and MAR.

59. Explain the sequence of steps in fetching a word from memory with an example.

60. List out the actions needed to execute the instruction ADD (R3), R1. Write and explain the sequence
of control steps for the execution of the same. 8. Write and explain the control sequence for execution of
an unconditional branch instruction.

61. Explain the basic idea of two stage instruction pipelining.

62. Explain the basic idea of four stage instruction pipelining.

63. Explain the role of cache memory in pipelining.

64. What is data hazard and instruction hazard in pipelining?