Digital Design & Computer Organization Dec.2023/Jan.

2024 Question
paper solution
1.a. Obtain a minimum product of sums with a Karnaugh Map.
F(w,x,y,z)=x’z’+wyz+w’y’z’+x’y

1.b. Find the minimum sum of products for each function using a Karnaugh Map.
i. F1(a,b,c)=M0+M2+M5+M6
ii. F2(d,e,f)=∑m(0,1,2,4)
iii. F3(r,s,t)=rt’+r’s’+r’s

Roopa.B, Asst. Prof., Dept. of CSE, ATMECE

2.a. Identify the prime implicants and essential prime implicants of the following
functions:
i. f(A,B,C,D)=∑(1,3,4,5,10,11,12,13,14,15)
ii. f(W,X,Y,Z)=∑(0,1,2,5,7,8,10,15)

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2.b. Write the verilog code for the given expression using dataflow and behavioral model
where, Y=(AB’+A’B)(CB+AD)(AB’C+AC)

Roopa.B, Asst. Prof., Dept. of CSE, ATMECE

2.c. Write the Verilog code and time diagram for the given circuit with propagation delay
where the AND, OR gate has a delay of 30ns and 10ns.

3.a. What is Latch? With the neat diagram, explain S-R Latch using NOR gate. Derive
characteristics equation.
name latches are used for a sequential device that checks all its inputs continuously and changes
its outputs accordingly at any time independent of a clocking signal.
Set-Reset Latch
S stands for set and R stands for reset. There are two inputs S is used for set and R is used for
reset. The output of SR depends on current as well as previous state. And its state changes as
soon as input change.
The SR latch can either be designed either using NOR gate or using NAND gates. The graphical
representation of SR latch is shown below:

Working of SR Latch: The two useful states are as follows:

• If output Q = 1 and Q’= 0 then latch is in set state.
• If output Q = 0 and Q’= 1 then latch is in reset state.

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If the circuit is designed using NOR gate then for both S =R=0 then Q and Q’ will retains the
previous state represented as Q0 which is said to be No change and S=R=1, then the output
states are said to be invalid or undefined.
If circuit is designed using NAND gate, then for both S =R=1 and S=R=0, then the output states
will be reverse of the NOR gate.

S R Q State
0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
1 1 - Invalid

S R Qn Q(n+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X

Characteristic equation: Q(n+1) = S + R’Qn

3.b. What is priority encoder? Design 4:2 priority encoder with necessary diagrams.
A priority encoder is an encoder circuit that includes the priority function. The operation of the
priority encoder is such that if two or more inputs are equal to 1 at the same time, the input
having the highest priority will take precedence.
The truth table of a four-input priority encoder is given in Table below. In addition to the two
outputs x and y, the circuit has a third output designated by V; this is a valid bit indicator that

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is set to 1 when one or more inputs are equal to 1. If all inputs are 0, there is no valid input and
V is equal to 0.

The other two outputs are not inspected when V equals 0 and are specified as don’t-care
conditions. Note that whereas X ’s in output columns represent don’t-care conditions, the X ’s
in the input columns are useful for representing a truth table in condensed form.
Instead of listing all 16 minterms of four variables, the truth table uses an X to represent either
1 or 0. For example, X100 represents the two minterms 0100 and 1100.
According to truth Table, the higher the subscript number, the higher the priority of the input.
Input D3 has the highest priority, so, regardless of the values of the other inputs, when this
input is 1, the output for xy is 11 (binary 3). D2 has the next priority level. The output is 10 if
D2 = 1, provided that D3 = 0, regardless of the values of the other two lower priority inputs.
The output for D1 is generated only if higher priority inputs are 0, and so on down the priority
levels.
The minterms for the two functions are derived from map method. Although the table has only
five rows, when each X in a row is replaced first by 0 and then by 1, we obtain all 16 possible
input combinations. For example, the fourth row in the table, with inputs XX10, represents the
four minterms 0010, 0110, 1010, and 1110. The simplified Boolean expressions for the priority
encoder are obtained from the maps. The condition for output V is an OR function of all the
input variables.

The priority encoder is implemented in Fig. according to the following Boolean functions:

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 Four input priority encoder
4.a. Design and explain four-bit adder with carry look ahead.
There are several techniques for reducing the carry propagation time in a parallel adder. The
most widely used technique employs the principle of carry lookahead logic.

Consider the circuit of the full adder shown in above Fig. If we define two new binary variables

the output sum and carry can respectively be expressed as

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Gi is called a carry generate, and it produces a carry of 1 when both Ai and Bi are 1, regardless
of the input carry Ci. Pi is called a carry propagate, because it determines whether a carry into
stage i will propagate into stage i + 1.
Now write the Boolean functions for the carry outputs of each stage and substitute the value of
each Ci from the previous equations:

Since the Boolean function for each output carry is expressed in sum-of-products form, each
function can be implemented with one level of AND gates followed by an OR gate.
The three Boolean functions for C1, C2, and C3 are implemented in the carry lookahead
generator shown in Fig. below. Note that this circuit can add in less time because C3 does not
have to wait for C2 and C1 to propagate; in fact, C3 is propagated at the same time as C1 and
C2. This gain in speed of operation is achieved at the expense of additional complexity
(hardware).

Logic diagram of carry lookahead generator

The construction of a four-bit adder with a carry lookahead scheme is shown in Fig below.
Each sum output requires two exclusive-OR gates. The output of the first exclusive-OR gate
generates the Pi variable, and the AND gate generates the Gi variable. The carries are
propagated through the carry lookahead generator and applied as inputs to the second
exclusive-OR gate. All output carries are generated after a delay through two levels of gates.

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Thus, outputs S1 through S3 have equal propagation delay times. The two-level circuit for the
output carry C4 is not shown.

4.b. What is multiplexer? Design 9:1 mux using 2:1 mux.

A multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of a particular input line is controlled
by a set of selection lines. Normally, there are 2n input lines and n selection lines whose bit
combinations determine which input is selected.

Roopa.B, Asst. Prof., Dept. of CSE, ATMECE

5.a. Explain four types of operation performed by computer with an example.
A computer must have instructions capable of performing four types of operations.
1. Data transfers between the memory and the registers (MOV, PUSH, POP, XCHG).
2. Arithmetic and logic operations on data (ADD, SUB, MUL, DIV, AND, OR, NOT).
3. Program sequencing and control (CALL, RET, LOOP, INT).
4. I/0 transfers (IN, OUT).
Register transfer notation
Transfer of information occurs from one location in the computer to another. Possible locations
that may be involved in such transfers are,
• memory locations,
• processor registers, or
• registers in the I/O subsystem.
Most of the time, we identify a location by a symbolic name standing for its hardware binary
address.

This type of notation is known as Register Transfer Notation (RTN). Note that the right-hand
side of an RTN expression always denotes a value, and the left- hand side is the name of a
location where the value is to be places, overwriting the old contents of that location.

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Assembly language notation

To represent machine instructions and programs, assembly language format is used. The
contents of LOC are unchanged by the execution of this instruction, but the old contents of
register R1 are overwritten.
5.b. Show how below expression will be executed in one address, two address, zero address
and three address processor in an accumulator organization X=(A*B)+(C*D).

For Zero address: No instruction

6.a. What is addressing mode? Explain different types of addressing mode with an
example.
The different ways in which the location of an operand is specified in an instruction are referred
to as addressing modes.

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Register mode - The operand is the contents of a processor register; the name (address)of the
register is given in the instruction.
Example: Move R1, R2 ; Copy content of register R1 into register R2
Absolute mode - The operand is in a memory location; the address of this location is given
explicitly in the instruction. (In some assembly languages, this mode is called Direct).
Example: Move LOC, R2 ; Copy content of memory-location LOC into register R2.
Immediate mode - The operand is given explicitly in the instruction.
Example: Move 200immediate, R0 ; Place the value 200 in register R0.
The Immediate mode is only used to specify the value of a source operand. Using a subscript
to denote the Immediate mode is not appropriate in assembly languages. A common convention
is to use the sharp sign (#) in front of the value to indicate that this value is to be used as an
immediate operand. Hence, write the instruction above in the form,
Move #200, R0 ; Place the value 200 in register R0.
Indirect mode - The effective address of the operand is the contents of a register or memory
location whose address appears in the instruction.

To execute the Add instruction in fig (a), the processor uses the value, which is in register R1,
as the effective address of the operand. It requests a read operation from the memory R1 to

Roopa.B, Asst. Prof., Dept. of CSE, ATMECE

read the contents of location B. the value read is the desired operand, which the processor adds
to the contents of register R0.
Indirect addressing through a memory location is also possible as shown in fig (b). In this case,
the processor first reads the contents of memory location A, then requests a second read
operation using the value B as an address to obtain the operand.
Index mode - the effective address of the operand is generated by adding a constant value to
the contents of a register. The register use may be either a special register provided for this
purpose, or, more commonly, it may be any one of a set of general-purpose registers in the
processor. In either case, it is referred to as index register.
Indicate the Index mode symbolically as: X (Ri), Where X denotes the constant value contained
in the instruction and Ri is the name of the register involved.

Relative mode – The effective address is determined by the Index mode using the program
counter in place of the general-purpose register Ri. This mode can be used to access data
operands. But, its most common use is to specify the target address in branch instructions. An
instruction such as
Branch > 0 LOOP
Causes program execution to go to the branch target location identified by the name LOOP if
the branch condition is satisfied. This location can be computed by specifying it as an offset
from the current value of the program counter. Since the branch target may be either before or
after the branch instruction, the offset is given as a signed number.
Autoincrement mode – the effective address of the operand is the contents of a register
specified in the instruction. After accessing the operand, the contents of this register are
automatically to point to the next item in a list. (Ri)+.
Autodecrement mode – the contents of a register specified in the instruction are first
automatically decremented and are then used as the effective address of the operand. -(Ri)
6.b. With a neat diagram, explain basic operational concepts of a computer.
To perform a given task an appropriate program consisting of a list of instructions is stored in
the memory. Individual instructions are brought from the memory into the processor, which
executes the specified operations. Data to be stored are also stored in the memory.
Example: Add LOCA, R0
This instruction adds the operand at memory location LOCA, to operand in register R0 &
places the sum into register R0. This instruction requires the performance of several steps,

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1. First the instruction is fetched from the memory into the processor.
2. The operand at LOCA is fetched and added to the contents of R0
3. Finally, the resulting sum is stored in the register R0
The preceding add instruction combines a memory access operation with an ALU Operations.
In some other type of computers, these two types of operations are performed by separate
instructions for performance reasons.
Load LOCA, R1
Add R1, R0
Transfers between the memory and the processor are started by sending the address of the
memory location to be accessed to the memory unit and issuing the appropriate control signals.
The data are then transferred to or from the memory. The shows how memory & the processor
can be connected.
In addition to the ALU & the control circuitry, the processor contains several registers used for
several different purposes.
The instruction register (IR): Holds the instructions that is currently being executed. Its output
is available for the control circuits which generates the timing signals that control the various
processing elements in one execution of instruction.
The program counter (PC): This is another specialized register that keeps track of execution of
a program. It contains the memory address of the next instruction to be fetched and executed.
Besides IR and PC, there are n-general purpose registers R0 through Rn-1.
The other two registers which facilitate communication with memory are:
1. MAR – (Memory Address Register): It holds the address of the location to be accessed.
2. MDR – (Memory Data Register): It contains the data to be written into or read out of the
address location.

Connections between processor and memory

Roopa.B, Asst. Prof., Dept. of CSE, ATMECE

7.a. Explain the following with respect to interrupts with diagram.
i. Vector interrupt
• A device requesting an interrupt identifies itself by sending a special code to processor
over bus. Then, the processor starts executing the ISR.
• The special-code indicates starting-address of ISR. The staring address to ISR is called
the interrupt vector. The special-code length ranges from 4 to 8 bits.
• This arrangement implies that the interrupt service routine for a given device must
always start at the same location. The programmer can gain some flexibility by storing
in this location and instruction that causes a branch to appropriate routine. In many
computers, this is done automatically by the interrupt handling mechanism.
• The location pointed to by the interrupting-device is used to store the staring address to
ISR. The processor reads this address, called interrupt vector and loads it into the PC.
• When a device sends an interrupt request, the processor may not be ready to receive the
interrupt vector code immediately. The interrupting device must wait to put data on the
bus only when the processor is ready to receive it. When processor is ready to receive
interrupt-vector code, it activates INTA line. Then, I/O-device responds by sending its
interrupt-vector code & turning off the INTR signal.
ii. Interrupt nesting
Interrupts should be disabled during the execution of an interrupt-service routine, to ensure that
a request from one device will not cause more than one interruption. The same arrangement is
often used when several devices are involved, in which case execution of a given interrupt-
service routine, once started, always continues to completion before the processor accepts an
interrupt request from a second device. Interrupt-service routines are typically short, and the
delay they may cause is acceptable for most simple devices.
• A multiple-priority scheme is implemented by using separate INTR & INTA lines for
each device. Each INTR line is assigned a different priority-level.
• Priority-level of processor is the priority of program that is currently being executed.
• Processor accepts interrupts only from devices that have higher priority than its own.
At the time of execution of ISR for some device, priority of processor is raised to that
of the device. Thus, interrupts from devices at the same level of priority or lower are
disabled.
iii. Simultaneous request
The processor must have some mechanisms to decide which request to service when
simultaneous requests arrive. A widely used scheme is to connect the devices to form a daisy
chain, as shown in fig.
• INTR line is common to all devices
• The interrupt-acknowledge line, INTA, is connected in a daisy-chain fashion, such that
the INTA signal propagates serially through the devices. INTA signal propagates
serially through devices.
• When several devices raise an interrupt-request, INTR line is activated. Processor
responds by setting INTA line to 1. This signal is received by device1.
• Device-1 passes signal on to device 2 only if it does not require any service.
If device-1 has a pending-request for interrupt, the device-1

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→ blocks INTA signal &
→ proceeds to put its identifying-code on data-lines.
• Device that is electrically closest to processor has highest priority.
• Advantage: It requires fewer wires than the individual connections.

Daisy chain
7.b. Explain Direct Memory Access with a neat diagram.
The transfer of a block of data directly between an external device & main memory without
continuous involvement by processor is called DMA.
DMA controller
→ is a control circuit that performs DMA transfers
→ is a part of the I/O device interface.
→ performs the functions that would normally be carried out by processor.
While a DMA transfer is taking place, the processor can be used to execute another program.

Use of DMA controller in a computer system.

DMA interface has three registers:
1) First register is used for storing starting address.
2) Second register is used for storing word-count.
3) Third register contains status- &control-flags.
The R/W bit determines direction of transfer.
If R/W=1, controller performs a read-operation (i.e. it transfers data from memory to I/O),
Otherwise, controller performs a write-operation (i.e. it transfers data from I/O to memory).
If Done=1, the controller
→ has completed transferring a block of data and
→ is ready to receive another command. (IE Interrupt Enable).
If IE=1, controller raises an interrupt after it has completed transferring a block of data.
If IRQ=1, controller requests an interrupt.

Roopa.B, Asst. Prof., Dept. of CSE, ATMECE

Requests by DMA devices for using the bus are always given higher priority than processor
requests.
There are 2 ways in which the DMA operation can be carried out:
1) Processor originates most memory-access cycles. DMA controller is said to "steal" memory
cycles from processor. Hence, this technique is usually called Cycle Stealing.
2) DMA controller is given exclusive access to main memory to transfer a block of data without
any interruption. This is known as Block Mode (or burst mode).

Typical registers in DMA Controller

8.a. What is bus arbitration? Explain different types of bus arbitration
Bus Arbitration is the process by which
→ next device to become the bus-master is selected &
→ bus-mastership is transferred to that device.
The two approaches are:
1) Centralized Arbitration: A single bus-arbiter performs the required arbitration.
2) Distributed Arbitration: All devices participate in selection of next bus-master.
Centralized Arbitration
• A single bus-arbiter performs the required arbitration. Normally, processor is the bus-
master. Processor may grant bus-mastership to one of the DMA controllers.
• A DMA controller indicates that it needs to become bus-master by activating BR line.
The signal on the BR line is the logical OR of bus-requests from all devices connected
to it.
• Then, processor activates BG1 signal indicating to DMA controllers to use bus when it
becomes free. BG1 signal is connected to all DMA controllers using a daisy-chain
arrangement.
• If DMA controller-1 is requesting the bus, then, DMA controller-1 blocks propagation
of grant-signal to other devices. Otherwise, DMA controller-1 passes the grant
downstream by asserting BG2.
• Current bus-master indicates to all devices that it is using bus by activating BBSY line.
(BR Bus-Request, BG Bus-Grant, BBSY Bus Busy).

Roopa.B, Asst. Prof., Dept. of CSE, ATMECE

Distributed Arbitration
• All devices participate in the selection of next bus-master (Figure 4.13). Each device
on bus is assigned a 4-bit identification number (ID).
When 1 or more devices request bus, they
→ assert Start-Arbitration signal &
→ place their 4-bit ID numbers on four open-collector lines ARB0 through ARB 3.
• A winner is selected as a result of interaction among signals transmitted over these lines.
• Net-outcome is that the code on 4 lines represents request that has the highest ID
number.
Advantage: This approach offers higher reliability since operation of bus is not dependent on
single device.

For E.g.: Assume 2 devices A & B have their ID 5 (0101), 6 (0110), their logical OR code is
0111.
• Each device compares the pattern on the arbitration line to its own ID starting from
MSB. If the device detects a difference at any bit position, it disables the drivers at that
bit position. Driver is disabled by placing ”0” at the input of the driver.
In e.g. “A” detects a difference in line ARB1, hence it disables the drivers on lines ARB1 &
ARB0. This causes pattern on arbitration-line to change to 0110. This means that “B” has won
contention.

8.b. Discuss different types of mapping functions caches.

Technique using which the contents of main memory are brought into the cache memory or
correspondence between cache and main memory is specified by a mapping function. The main
memory block is copied simply to the cache during the process of cache mapping, and this
block isn’t brought at all from the main memory.

Roopa.B, Asst. Prof., Dept. of CSE, ATMECE

Direct mapping
• Simple technique but not flexible
• Since more than one memory block is mapped onto a given cache block position,
congestion/dispute may arise for that position even when the cache is not full.
• Congestion is resolved by allowing the new block to overwrite the currently resident
block. So, no replacement algorithm is required.
Placement of cache is determined from the memory address called Physical address. It can be
divided into 3 fields: Tag, block/index, word/offset.

Associative Mapping
• Much more flexible method, but expensive.
• Main memory blocks can be placed into any cache block position. Hence there is no
need to identify a specific empty block in cache when a new block arrives. So, tag bits
of an address received from the processor are compared with the tag bits of each of
cache to see if the desired block is present.
• A new block brought into the cache has to replace an existing cache block, only if the
cache is full. Hence replacement algorithm is required. The replacement algorithm
suggests a block that is to be replaced whenever all the cache lines happen to be
occupied. So, replacement algorithms such as LRU (Least recently used) Algorithm,
FCFS Algorithm, etc., are employed.

Roopa.B, Asst. Prof., Dept. of CSE, ATMECE

Set Associative mapping
• By combining the simplicity of direct mapping and flexibility of associative mapping a
new method called set-associative mapping is developed. Here, blocks of cache are
grouped into sets, and the mapping allows a block of main memory to reside in any
block of a specific set.
• Ex: cache with 2 blocks per set – two way set associative. Any memory block can
occupy either of the 2 cache block positions within the set. The ‘Set’ field of address
determines which set of cache might contain the desired block. Tag field is then
compared to the tags of the two blocks of set to check if the desired block is present.
• Compared to associative search size, time is reduced, thus reducing the design cost.

Roopa.B, Asst. Prof., Dept. of CSE, ATMECE

9.a Draw and explain the single bus organization of the data path inside a processor.
A computer system has one functional unit which executes machine instructions. This unit
communicates with and coordinates the activities of other subsystems within the computer.
This unit is called CPU. ALU and all the registers are interconnected via a Single Common
Bus, which is internal to the processor.
• Data & address lines of the external memory-bus is connected to the internal processor-bus
via MDR & MAR respectively. (MDR- Memory Data Register, MAR - Memory Address
Register).
• MDR has 2 inputs and 2 outputs. Data may be loaded,
→ into MDR either from memory-bus (external) or
→ from processor-bus (internal).
Data stored in MDR may be placed on either bus.
• MAR’ s input is connected to internal bus; MAR’s output is connected to external bus.
• Instruction Decoder & Control Unit is responsible for
→ issuing the control-signals to all the units inside the processor.
→ interacting with memory bus.
• Register R0 through R(n-1) are the Processor Registers. The programmer can access these
registers for general-purpose use.
• Only processor can access 3 registers Y, Z & Temp for temporary storage during program-
execution. The programmer cannot access these 3 registers.
• In ALU,
1) ‘A’ input gets the operand from the output of the multiplexer (MUX).
2) ‘B’ input gets the operand directly from the internal processor-bus.
• There are 2 options provided for ‘A’ input of the ALU. MUX is used to select one of the 2
inputs. MUX selects either,
→ output of Y (using selectY) or
→ constant-value 4 (which is used to increment PC content- using select 4).
As instruction execution progresses, data are transferred from one register to another, often
passing through ALU to perform some arithmetic or logic operation. The registers, the ALU,
and the interconnecting bus are collectively referred to as the data path.

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9.b. List out the actions needed to execute the instruction ADD (R3),R1 write and explain
the sequence of control steps for the execution of the same.
Answer is same as 10.a
10.a. Analyse how does execution of a complete instruction carry out.
Consider the instruction Add (R3), R1 which adds the contents of a memory-location pointed
by R3 to register R1. Executing this instruction requires the following actions:
1) Fetch the instruction.
2) Fetch the first operand from memory
3) Perform the addition &
4) Store the result in R1.

Instruction execution proceeds as follows:

Step1: The instruction-fetch operation is initiated by
→ loading contents of PC into MAR &
→ sending a Read request to memory.
The Select signal is set to Select4, which causes the Mux to select constant 4. This value is
added to operand at input B (PC’s content), and the result is stored in Z.
Step2: Updated value in Z is moved to PC. This completes the PC increment operation and PC
will now point to next instruction.
Step3: Fetched instruction is moved into MDR and then to IR.
The step 1 through 3 constitutes the Fetch Phase.
At the beginning of step 4, the instruction decoder interprets the contents of the IR. This enables
the control circuitry to activate the control-signals for steps 4 through 7. The step 4 through 7
constitutes the Execution Phase.
Step4: Contents of R3 are loaded into MAR & a memory read signal is issued.
Step5: Contents of R1 are transferred to Y to prepare for addition.
Step6: When Read operation is completed, memory-operand is available in MDR, and the
addition is performed.
Step7: Sum is stored in Z, then transferred to R1. The End signal causes a new instruction fetch
cycle to begin by returning to step1.
10.b. What is pipeline? Explain the performance of pipeline with an example.

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The overlapped execution mechanism which improves the throughput of the system is referred
to as pipelining.
The problems that occur in the pipeline which affect the performance are called hazards.
Pipeline hazards are classified as: data hazards, control or instruction hazards, structural
hazards
Data Hazard
• A data hazard is a situation in which the pipeline is stalled because the operands are not
available at the time expected in the pipeline and hence some operation is delayed.
• Consider below figure, here the stage E2 of instruction I2 takes 3 clock cycles to
complete. Thus, for clock cycle 5 and 6, instructions I3 and I4 cannot go to the execute
stage, Since I2 has not yet completed the operation in that stage. So, all the next
instructions are delayed. The pipelined operation in fig is said to have been stalled for
2 clock cycles.

• Another cause for data hazard is data dependency.

• Example: B←A*4
C←B+3
Let A=10 initially. If sequence is followed, value of C will be 43. But if they are executed
concurrently, the result will be different, since the second operation would have started before
the completion of the first operation. Here the second operation depends on the result of the
first operation and hence must wait for the completion of the first instruction causing the
pipeline to stall.
Solution: hardware design or in the software by using NOP instructions, to introduce the delay
needed.
Control Hazard
• The pipeline may also be stalled because of a delay in the availability of instructions.
• For example, as shown in figure below the fetch operation for instruction I2 results in
a cache miss and is delayed till clock cycle 5. Hence the next instructions will also be
delayed.

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 • Figure b illustrates the operation in each clock cycle, by each stage. Each stage is idle
for more than one clock cycle. Such idle periods are called bubbles in the pipeline.

Structural hazard
• The third type of hazard that may be encountered in pipelined operation is known as a
structural hazard. This is the situation when two instructions require the use of a given
hardware resource at the same time.
• The most common case in which this hazard may arise is in access to memory. One
instruction may need to access memory as part of the execute while another instruction
is being fetched.
• If the instructions and data reside in the same cache unit, only one instruction can
proceed, and the other instruction is delayed.
• Many processors use separate instruction and data caches to avoid this delay.
Example: Load X(R1), R2
The memory address, X+[R1], is computed in step E2 in cycle 4, then memory access takes
place in cycle 5. The operand read from memory is written into register R2 in cycle 6. This
means that execution step of this instruction takes 2 clock cycles (4 & 5). It causes the pipeline
to stall for one cycle, because both the instructions I2 and I3 require access to the register file
in cycle 6.

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Solution: The structural hazards are avoided by providing sufficient hardware resources on the
processor chip

Roopa.B, Asst. Prof., Dept. of CSE, ATMECE