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FSM Questions

The document contains 7 problems involving designing finite state machines (FSMs) with various specifications: 1) An FSM with 1 input and 1 output that outputs 1 when 2 0s and 2 1s have occurred as input. 2) An FSM that indicates if a binary number is divisible by 3. 3) The maximum number of bits needed for the state register if an FSM is connected to another FSM. 4) An FSM that outputs 1 when the number of As is even and Bs is odd. 5) An FSM to detect the input sequence "abca". 6) An FSM for a modulo-3 or modulo-4 counter. 7) A logic that mimics an infinite width register and outputs high when the held value

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Sumit Kumar
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154 views1 page

FSM Questions

The document contains 7 problems involving designing finite state machines (FSMs) with various specifications: 1) An FSM with 1 input and 1 output that outputs 1 when 2 0s and 2 1s have occurred as input. 2) An FSM that indicates if a binary number is divisible by 3. 3) The maximum number of bits needed for the state register if an FSM is connected to another FSM. 4) An FSM that outputs 1 when the number of As is even and Bs is odd. 5) An FSM to detect the input sequence "abca". 6) An FSM for a modulo-3 or modulo-4 counter. 7) A logic that mimics an infinite width register and outputs high when the held value

Uploaded by

Sumit Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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1. Design an FSM that has 1 i/p and 1 o/p.

The o/p becomes 1 and remains 1 when


at least two 0's and two 1's have occurred as i/p's.

2.Design a "%3" FSM that accepts one bit at a time, most significant bit first,
and indicates if the number is divisible by 3.

3. If an FSM is redesigned using a state register with minimum number of bits after
connecting the output of a 3-state FSM to the inputs of an 9-state FSM, what is
the maximum number of bits needed?

4. Design a state-machine to give an output ’1’ when the number of A’s are even
and number of B’s are odd. The input is in the form of a serial-stream
(one-bit per clock cycle). The input s could be of t he type A, B or C. At any
given clock cycle, the output is a ’1’, provided the number of A’s are even and
number of B’s are odd. At any given clock cycle, the out put is a ’0’, if the
above condition is not satisfied.

5. Design a FSM to detect the sequence ‘abca’ when the inputs can be ‘abcd’.

6. Design a finite state machine for a modulo-3 counter when x=0, and
modulo-4 counter when x=1.

7. Design a logic which mimics a infinite width register. It takes input


serially 1 bit at a time. Output is asserted high when this register holds
a value which is divisible by 5.

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