Scribd
Upload
6 views5 pages

QB 4

The document outlines various topics related to digital logic design, including Boolean algebra, combinational circuits, sequential circuits, and programmable logic devices. It includes definitions, design tasks, and simplification techniques for various digital components such as adders, multiplexers, and flip-flops. Additionally, it covers hazards in asynchronous circuits and provides exercises for implementing functions using different methods.

Uploaded by

senthil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
6 views5 pages

QB 4

The document outlines various topics related to digital logic design, including Boolean algebra, combinational circuits, sequential circuits, and programmable logic devices. It includes definitions, design tasks, and simplification techniques for various digital components such as adders, multiplexers, and flip-flops. Additionally, it covers hazards in asynchronous circuits and provides exercises for implementing functions using different methods.

Uploaded by

senthil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

UNIT – I

1. State De-Morgan’s Theorem.


2. Convert Y= A+BC'+AB+A'BC into canonical form
3. Express x  yz as the sum of min terms.
4. What is prime implicant?
5. What is meant by ‘essential prime-implicant’?
6. Show that A+A’B=A+B using the theorems of Boolean algebra.
7. Convert (101101.1101)2 to decimal and hexadecimal form.
8. Convert (153.513)10 to octal.
9. Perform (147-89) using 2’s complement binary arithmetic.
10. Convert binary number 1011100010 to its gray code
11.

1. State and prove demorgan’s law with three variables.

2. Simplify the given switching function using tabular minimization procedure f(x1, x2, x3, x4)
= ∑m(0,5,7,8,9,10,11,14,15)

3. Simplify the function F = ∑m(1,3,7,11,15) + ∑d(0,2,5) using k-map.

4. Reduce F = ∑m(1,4,6,7,8,9,10,11,15) using Quine Mcclusky method.

5. Simplify using Quine Mcclusky method.and verify your result using k-map

F = ∑m(0,1,2,5,7,8,9,10,13,15).

UNIT – II

1. Define half adder and full adder.


2. Define half subtractor and full subtractor
3. List the advantage of look ahead carry? When should it be used?
4. Distinguish between Decoder and Demultiplexer
5. What are the applications of magnitude comparator?
6. Draw the block diagram of n-bit parallel adder
7. Draw a logic diagram of 1 to 4 data distributor
8. Write the function table and logic diagram of a 4:1 data selector.
9. Implement the following function using suitable multiplexer F=∑m
(0,2,5,7)
10. Relate carry generate, carry propagate, sum and carry-out of a carry
look ahead adder.
11. Design a single bit magnitude comparator to compare two
words A and B.
12. What is combinational circuit? Give examples.
13. What is priority Encoder?
14. List few applications of multiplexer.
15. Construct a two-4-bit parallel adder/subtractor using Full Adders and XOR gates.

1. Design a 4-bit magnitude comparator with three outputs : A>B , A=B , A<B .

2. Implement the following Boolean function using 8×1 MUX

F(A,B,C,D) = ∑m(1,3,4,11,12,13,14,15)

3. Design and explain 1 to 8 demultiplexer.

4. Draw the logic diagram and truth table and explain the operation of 3 to 8 line decoder.

5. What is decoder? Explain the circuit of a BCD to decimal decoder.

6. What is a demultiplexer? Draw the logic circuit of 1 to 8 demultiplexer.

7. Design a full adder using two half adder .

UNIT – III

1. How do you eliminate the race around condition in a JK flip-flop?


2. Draw the state table and excitation table of T flip-flop.
3. Write the flip-flop excitation tables for JK and T FF.
4. Mention any two differences between the edge triggering and level triggering.
5. State the differences between Moore and mealy state machine.
6. Compare the logics of synchronous counter and ripple counter.
7. Define latches.
8.

1. Design a 3-bit synchronous counter using D-Flip-flop.

2. Draw and explain the 4-bit S1S0, S1P0, P1S0 & P1P0 shift register with its waveforms.

3. Explain the operation of JK flip-flop with neat diagram.

4. Design a counter with the following repeated binary sequence

0, 1, 3,7,6,4 using T flip-flop.

5. Design a 3-bit synchronous counter using JK Flip Flops

6. With the necessary diagram explain the operation of modulo 8 up counter using T flip flops.

7. Design a synchronous up/down counter

8. Discuss the working of a 4-bit Johnson counter with circuit diagram.

UNIT – IV

1. What is difference between PAL and PLA?


2. Compare Dynamic RAM with Static RAM.
3. Mention few applications of PLA and PAL.
4. What are the different types of programmable logic devices?
5. Draw the structure of a static RAM cell.
6. How the memories are classified?
7. Draw the logic diagram of a static RAM cell and Bipolar cell.
8.

1. Implement the following function using PLA,


F1(x,y,z)= ∑m(1,2,4,6)

F2(x,y,z)= ∑m(0,1,6,7)

F3(x,y,z)= ∑m(2,6)

2. Write a short note on FPGA.

3. Differentiate static and dynamic RAM. Draw the circuit of one cell of each and explain its
working principle.

4. Write short notes on EAPROM and static RAM cell using MOSFET.

5. Use PLA with 3 inputs and 4 AND gates and two outputs to implement the following
Boolean functions.

F1(A,B,C)= ∑m(3,5,6,7) F2(A,B,C)= ∑m(1,2,3,4)

UNIT – V

1. What are hazard free digital circuits?


2. What is state table?
3. What are the two types of asynchronous sequential circuits?
4. Differentiate fundamental mode and pulse mode asynchronous sequential circuits.
5. Define flow table and primitive flow table.
6. What is the cause for essential Hazard?
7.

1. What is a hazard in asynchronous sequential circuits? Define static, dynamic and essential
hazard.

2. Explain the terms critical race, non critical race, stable state and cycles in asynchronous
sequential circuits with examples.

3. Design a negative triggered T Flip Flop for the circuit which has two inputs, T(toggle) and C
(clock) and one output Q. The output state is complemented if T=1 and the clock C changes
from 1 to 0. Otherwise under any other input condition the output Q remains unchanged. Obtain
its primitive flow table, transition table and logic diagram.

4. An asynchronous sequential circuit has two internal states and one output. The excitation and
output functions describing the circuit as follows.
Y1=x1x2+x1y2’+x2y1

Y2=x2+x1y1’y2+x1y1

Z=x2+y1

Draw the logic diagram of the circuit. Derive the transition table and output map. Also obtain the
flow table for the circuit.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy