Programming Manual: Programmable Controller
Programming Manual: Programmable Controller
PROGRAMMING MANUAL
1. MAKING SEQUENCE CIRCUITS 1
2. EXECUTION OF PROGRAM 2
3. PARAMETER 3
5. INSTRUCTION WORDS 5
For safety use of this product, read carefully this manual and other related individual operation
manuals altogether. Further, keep these manuals in file at an easily accessible place so that
persons concerned can read them anytime as necessary.
The distributor or dealer of this product is requested to hand over the said manuals to the end
user without fail.
The specification and other relevant information included in this Manual are subject to change
due to better improvement without prior notice.
Any product applicable to the strategic goods (or services) stipulated in the Foreign Exchange
and Foreign Trade Control Act is subject to export license of the Japanese Government, where
exported to overseas.
Should this product result in trouble during the guarantee period due to somewhat cause
attributed to our responsibility, necessary device(s) or parts(s) shall be repaired or replaced at
our discretion. For any other trouble or accident out of our responsibility, our company shall
be released from the responsibility for injury which may arise from such a trouble or accident.
i
FOR SAFETY OPERATION
Before installing, operating, maintaining and checking, read carefully this Manual without fail for
proper and safety operation and work. Any operator and any maintenance man who relate to
this product (Programmable Controller) are requested to acquire the knowledge on devices,
safety information and cautions before being engaged in the operation and maintenance. This
Manual classifies the safety caution level into "WARNING" and "CAUTION" using alert symbols
as follows.
Don't overhaul the module and don't touch the module internals,
with the power switch kept ON.
Failure to observe this instruction could result in electric shock.
Don't touch the terminals with the power switch kept ON.
Failure to observe this instruction could result in electric shock.
Execute write during PC run (write during run) only when cyclic
operation of main equipment/machine is in shutdown.
Failure to observe this instruction could result in breakdown of its
device(s) and bodily injury from mis-operation, if any.
In handling the lithium battery, read and observe " Lithium Battery
Handling Cautions " given in this Manual. Improper handling
would cause liquid leak, overheat, sparking, and fracture, which
could then result in breakdown of units and devices and bodily
injury.
ii
Use this product under an environment which meets the
environmental general specification specified in this Manual.
Don't attach/detach each module to/from its base, with the power
switch kept ON.
iii
REVISION HISTORY OF OPERATION MANUAL
Operation manual revision No. is added as a part of Manual No. described on the cover sheet of
the manual.
Operation Manual No.
T – 361 # E
N: Japanese E: English
Series No.
Revision symbol
PCk05-specific functions------------------PCk05
PCk06-specific functions------------------PCk06
iv
Contents
FOREWORD
FOR SAFETY OPERATION
REVISION HISTORY OF OPERATION MANUAL
Composition of Related Operation Manuals
The equipment is provided with limit switches (LS) which provide information on the location of
machine components and with pushbutton switches (PB) which give instructions to the machine.
The devices defining the conditions of action, generically called I/O devices, should be connected
to the input module on the TOYOPUC.
The equipment is also provide with solenoid valves (SOL) which drive and control, by hydraulic
medium, the cylinders used as actuator and with magnetic switches (MS) which turn on or off the
motors. These devices, generically called output devices, should be connected to the output
module on the TOYOPUC.
First specify a terminal to which an input or output device is to be connected. Each terminal has its
proper number and this is called I/O address. In a sequence program, the I/O address specifies
the I/O device.
The I/O address is shown by three figure digits of the hexadecimal number, and the number of
I/O with built-in CPU that starts from Y400 is an output from input X000. The number of the
option I/O module that starts from Y440 is an output from input X040.
Example 1 PCk05
Note) An intelligent module such as kDLNK doesn't occupy the I/O address.
1-1
Example 2 PCk06
Option slot 1 2 3 4
Input terminal
C0 X001 X003 X004 X006 C2 X009 X00B X00C X00E C4 X011 X013 N.C.
X000 X002 C1 X005 X007 X008 X00A C3 X00D X00F X010 X012 N.C.
Input 20 points X000 ~ X013
Example 2
Slot no Option module Mounting point Input address Output address
1 kDLNK It is not Unused Unused
2 OUT-k12 Output 16 points Unused Y440 ~ Y44F
3 IN-k93 Input 10 points X040 ~ X049 Unused
4 IN-k14 Input 16 points X050 ~ X05F Unused
Example 3
Slot no Option module Mounting point Input address Output address
1 kDLNK It is not Unused Unused
2 IN-k14 Input 16 points X040 ~ X04F Unused
3 OUT-k12 Output 16 points Unused Y440 ~ Y44F
4 OUT-k12 Output 16 points Unused Y450 ~ Y45F
1-2
1.2. Circuit diagram configuration
Usually, a circuit diagram representing sequence circuit including TOYOPUC is drawn in a form of
relay circuit (ladder diagram). The figures below show recommendable expression of circuit
configuration which make the design and maintenance of control board easier.
Circuits and components of the same function in a machine should be represented in a respective
block, such as input, logic and output section on a machine basis.
Devices to which TOYOPUC sends input signals (such as pushbutton switch and limit switch) are
written in the input section.
Example of circuit
1-3
1.3.2. Output section
Example of circuit
1-4
1.4. Logic section
Internal relay (dummy output) for temporary storage which does not drive external devices such as
solenoid-operated valve or magnetic switch is written in logic section.
Example of circuit
Advance memorized
Internal
M M000
relay
1-5
1.4.2. Timer
The timers used are divided into the following categories and are to be expressed in the logic
section.
Function Mnemonic
Unit in 10ms TMRH
Direct setup
Unit in 100ms TMR
Timer
Indirect Unit in 10ms TMRH
setup Unit in 100ms TMR
Unit in 10ms TMRSH
Direct setup
Integrating Unit in 100ms TMRS
timer Indirect Unit in 10ms TMRSH
setup Unit in 100ms TMRS
Example of circuit
Timer T T012
T012
1-6
1.4.3. Counter
The counters used are divided into the following categories and are to be expressed in the logic
section.
Function Mnemonic
Direct setup CNT
Up counter
Indirect setup CNT
Direct setup CNTH
Up/Down counter
Indirect setup CNTH
Example of circuit
1-7
1.4.4. Keep relay
Example of circuit
Keep
K K00A
relay
1-8
1.4.5. Edge detection
Turns on for a period equal to one scan of sequence when conditions are met( )or not
met ( ). This part should be expressed in logic section.
Example of circuit
Edge
P P001
detection
It is not possible to use it on other conditions. Moreover, the device that can be
used in a point of contact instruction at this time is only input (X), output (Y),
internal relay (M PCk05:M000-0FF,PCk06:M000-M1FF), Keep relay (K),
timer (T), counter (C), and link (L) relays.
1-9
1.4.6. Special relay
Special relays are internal relays whose application and function are predetermined by the TOYOPUC, the
primary applications being to indicate operation status of this machine and result of arithmetic operation
made through application instruction.
Example of circuit
The number to which the name is provided might be an empty column in other TOYOPUC while
having a look at the special relay shown since next page. Please note that it is not used by the
difference of the function of the main body of CPU in the usage about them.
Please use only a special relay of the number explained in the table of the list.
Because all are the reservation areas, the user cannot use it for the address that doesn't exist in
the list.
1-10
Address Name Outline Description
V00
0: No ERR0 On when a critical error such as I/O
V01 MAJOR ERROR
1: ERR0 in occurring communication loss has occured.
0: No ERR1
V02 MINOR ERROR On when a non critical error has occured.
1: ERR1 in occurring
V03
V06 1ST SCAN Only the first scanning is ON. ON by resetting and OFF by END processing.
V07
V08
V09
V0A
V0B
V0C
V0D
V0E
V0F
V10
V11
0:not TERMINAL RUN On when the mode switch is in the TERM position
V12 TERMINAL RUN
1:TERMINAL RUN and the CPU is in the run mode.
0:not TEST RUN
V13 TEST RUN On when the CPU is in the test run mode.
1:TEST RUN
V14
0:not TEST STOP
V15 TEST STOP On when the CPU is in the test stop mode.
1:TEST STOP
0:not TERMINAL STOP On when the mode switch is in the TERM position
V16 TERMINAL PGM
1:TERMINAL STOP and the CPU is in program mode.
V17
0:Excluding while stopping
V18 FORCED STOP On when the STOP instruction is executed.
1:Stopping
V19
INTERRUPT 0:Inhibit On when interrupts have been enabled using the
V1A
ENABLED 1:Enable EI instruction.
V1B
V1C
V1D
V1E
V1F
1-11
Address Name Outline Description
V20
V21
V22
V23
V24
V25
0:Excluding while stopping
V26 FORCED STOP On when the mode switch is in the STOP position.
1:Stopping
0:Excluding while running On when the mode switch is in the RUN position
V27 FORCED RUN
1:running and the CPU is running.
V28
V29
V2A
V2B
V2C
V2D
V2E
V2F
V30
V31
V32
V33
V34
V35
V36
V37
V38
V39
V3A
V3B
V3C
V3D
V3E
V3F
1-12
Address Name Outline Description
V40
V41
V42
V43
V44
V45
V46
V47
V48
V49
V4A
V4B
COMMUNICATION 0: No error On when RX,WX,instuctions are executed with
V4C
ERROR 1: Error the wrong parameters.
V4D
V4E
V4F
0: No error
V50 SOLVE LOGIC ERROR On if CPU cannot solve the logic.
1: Error
1-13
Address Name Outline Description
CPU PORT BUSY 0: No busy On when port2 is the master and sending
V60
PORT2 1: Busy data.
COMMUNICATIONS 0: No error On when port2 is the master and has s
V61
ERROR PORT2 1: Error communication error.
V62
V63
V64
V65
V66
V67
V68
V69
V6A
V6B
V6C
V6D
V6E
V6F
Repetition of 50msecOFF
V70 0.1 SEC CLOCK Clock of cycle 0.1 sec and duty 50%
and 50msecON
V71
V73
1-14
Address Name Outline Description
V80
V81
V82
V83
V84
V85
V86
V87
V88
V89
V8A
V8B
V8C
V8D
V8E
V8F
V90
V91
V92
V93
V94
V95
V96
V97
V98
V99
V9A
V9B
V9C
V9D
V9E
V9F
1-15
Address Name Outline Description
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
VA8
VA9
VAA
VAB
VAC
VAD
VAE
VAF
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7
VB8
VB9
VBA
VBB
VBC
VBD
VBE
VBF
1-16
Address Name Outline Description
0: No error
VC0 CPU ERROR ON upon detection of CPU module error.
1: Error
VC1
0: No error On when a memory error such as a memory parity
VC2 MEMORY DATA ERROR
1: Error error has occurred.
VC3
VC4
VC5
VC6
I/O MODULE ERROR( Fuse 0: No error On when an I/O error such as a blown fuse
VC7
blown, etc.) 1: Error occurs.
VC8
0: No error On if a grammatical error has occurred either
VC9 USER PROGRAM ERROR while the CPU is running of if the syntax
1: Error check is run.
VCA
VCB
VCC
VCD
VCE
VCF
VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VD8
VD9
VDA
VDB
VDC
VDD
VDE
VDF
1-17
Address Name Outline Description
VE0
0: No error ON upon detection of SCAN TIME OVER .OFF after
VE1 SCAN TIME-OVER
1: Error reset or power on.
VE2
VE3
VE4
VE5
VE6
VE7
VE8
VE9
VEA
VEB
VEC
VED
VEE
VEF
On when the CPU battery voltage is low.
0: No error
It detects it with PCk06 only at a battery
VF0 LOW BATTERY ERROR
circuit effective bit ON
1: Error
(special register S05B bit 12).
VF1
VF2
VF3
VF4
VF5
VF6
VF7
VF8
VF9
VFA
VFB
VFC
VFD
VFE
VFF
1-18
1.4.7. Link relay
Link relays are internal relays used foe data linking between PLCs and communication between
remote I/Os.
These relays can also be used for applications basically made for the general purpose internal
relay (M***), when they are not used as communication relays.
Example of circuit
1-19
1.5. Application instruction
TOYOPUC can store data and process numerical data through arithmetic operations, in addition to
operation of sequential processing. To enable the controller to handle this numerical data, special
instructions called application instructions (or function instructions) are available.
Application instructions are roughly classified as follows:
Used to transfer data, process arithmetic and logical operations and to handle other data
process oriented functions. The instruction will be executed when the previous operation
resulted in ON. (The instruction will be executed every scan as long as the operation result
is ON. To execute only once at the start, use .)
Stores the current value of a timer or counter. The current contents of a this register from an
application instruction.
1-20
1.5.4. Special register
The special registers listed in the table below are available for special applications such as CPU
status, built-in clock, link modules, etc. These special registers are in Basic area and extended
area.
It is all reservation area for the address that doesn't exist in the list. Therefore, the user cannot use
its address.
S016
S017
Location contains a 10mS counter (0-99). This location increments
S018 10ms COUNTER
once every 10mS.
S019
S01A
S01B
S01C
S01D FATAL ERROR CODE Error code - stores the fatal error code.
S01E MAJOR ERROR CODE Error code - stores the major error code.
S01F MINOR ERROR CODE Error code - stores the minor error code.
As for the content of the error code, it is 1.5.5. Refer to the CPU error code table.
1-21
Address Name Description
S020
S021
S022
S023
S024
S025
S026
S027
S028
S029
S02A
S02B
S02C
S02D
S02E
S02F
S030
S031
S032
S033
S034
S035
S036
S037
S038
S039
S03A
S03B
S03C
S03D
S03E
S03F
1-22
Address Name Description
S040
S041
S042
S043
S044
S045
S046
S047
S048 kDLNK MODULE PARAMETER kDLNK MODULE PARAMETER AREA
S049 kDLNK MODULE PARAMETER kDLNK MODULE PARAMETER AREA
S04A kDLNK MODULE PARAMETER kDLNK MODULE PARAMETER AREA
S04B kDLNK MODULE PARAMETER kDLNK MODULE PARAMETER AREA
S04C kDLNK MODULE PARAMETER kDLNK MODULE PARAMETER AREA
S04D kDLNK MODULE PARAMETER kDLNK MODULE PARAMETER AREA
S04E kDLNK MODULE PARAMETER kDLNK MODULE PARAMETER AREA
S04F kDLNK MODULE PARAMETER kDLNK MODULE PARAMETER AREA
S050
S051
S052
S053
S054
S055
S056
S057
S058 PCk05/PCk06 INPUT PARAMETER
S059 PCk05/PCk06 INPUT PARAMETER
S05A PCk05/PCk06 INPUT PARAMETER
S05B PCk05/PCk06 INPUT PARAMETER Sets the desired function code for X0 ~ X3.
X0 Setup Register for High-Speed I/O functions.
S05C PCk05/PCk06 INPUTPARAMETER
Default:1006
X1 Setup Register for High-Speed I/O functions.
S05D PCk05/PCk06 INPUT PARAMETER
Default:1006
X2 Setup Register for High-Speed I/O functions.
S05E PCk05/PCk06 INPUT PARAMETER
Default:1006
X3 Setup Register for High-Speed I/O functions.
S05F PCk05/PCk06 INPUT PARAMETER
Default:1006
As for the content of the PCk05/PCk06 Input parameter, it is 1.5.6. Refer to the PCk05/PCk06
Input parameter setting table.
1-23
Address Name Description
S060
S061
S062
S063
S064
S065
S066
S067
S068
S069
S06A
S06B
S06C
S06D CPU PORT2 PROTOCOL Setup for the protocol, time-out, and the response delay time.
S06E CPU PORT2 CONDITION Setup for the station number, baud rate, STOP bit, and parity.
Setup completion code used to notify the completion of the parameter
S06F CPU PORT2 COMPLETION
setup.
S070
S071
S072
S073
S074
S075
S076
S077
S078
S079
S07A
S07B
S07C
S07D
S07E
S07F
As for the content of CPU PORT2, it is 1.5.8. Refer to the CPU PORT2 setting table.
S080 ~
S0BF
S0C0 ~
S0FF
S100 ~
S3FF
1-24
1.5.5. CPU error code table
1-25
Error code PCk05 PCk06 Description
The checksum error occurred in system RAM.
VC2 is turned on, and the error code is
preserved in S01D. This problem has the
possibility of originating in the decrease, the
E155
○ noise, and the CPU RAM breakdown in the
RAM FAILURE
voltage of the battery. Please do the writing
operation of the program again. Please confirm
the earth. Please exchange CPU when the error
relapses.
E200
○ The I/O module broke down.
I/O MODULE FAILURE
1-26
Error code PCk05 PCk06 Description
Please give the last execution instruction of the
ladder program to me as END. Please insert the
E401
○ ○ END instruction in the position where the ladder
MISSING END STATEMENT
program is correct. VC9 is turned on, and the
error code is preserved in S01D.
1-27
1.5.6. PCk05/PCk06 input parameter setting table
1-28
1.5.7. PCk05/PCk06 input parameter setting program example
1-29
1.5.8. CPU PORT2 setting table
Special
register Name Description
address
bit02,bit01,bit00 RTS off delay. Waiting time until RTS signal is off
after data is transmitted.
000: 0 ms
001: 2 ms
010: 5 ms
011: 10 ms
100: 20 ms
101: 50 ms
110: 100 ms
111: 500 ms
1-30
Special
register Name Description
address
At protocol DirectNet
bit06-bit00 Communication station number(1-90)
bit07 Communication data format Hex(0) ASCII(1)
At protocol MODBUS
bit07-bit00 Communication station number(1-247)
PORT2 is selected and (1) is selected in case of MODBUS
(master). The range that can be set as MODBUS slave is
up to (1-247).
bit10,bit09,bit08 Communication baud rate
000: 300 bps
001: 600 bps
010: 1200 bps
011: 2400 bps
Communication 100: 4800 bps
S06E
setting 101: 9600 bps
110: 19200 bps
111: 38400 bps
bit12 Undefined(0)
1-31
1.5.9. CPU PORT2 setting program example
1-32
1.6. Network slave operation
1.6.1. Network slave
This section describes how other devices on a network can communicate with a CPU PORT2 that you
have configured as a DirectNET slave or MODBUS slave (PCk05/PCk06). A MODBUS host must use
the MODBUS RTU protocol to communicate with the PCk05/PCk06 as a slave. The host software must
send a MODBUS function code and MODBUS address to specify a PLC memory location the
PCk05/PCk06 comprehends. The DirectNET host uses normal I/O addresses to access applicable
PCk05/PCk06 CPU and system. No CPU ladder logic is required to support either MODBUS slave or
DirectNet slave operation.
MODBUS Function
Function Data Types Available
Code
01 Read a group of coils Y,M,K,T,C,L
02 Read a group of inputs X,L
05 Set / Reset a single coil Y,M,K,T,C,L
15 Set / Reset a group of coils Y, Y,M,K,T,C,L
03,04 Read a value from one or more registers D,N
06 Write a value into a single register D,N
16 Write a value into a group of registers D,N
(1) If Your Host Software Requires the Data Type and Address
Many host software packages allow you to specify the MODBUS data type and the MODBUS address
that corresponds to the PLC memory location. This is the easiest method, but not all packages allow
you to do it this way.
The actual equation used to calculate the address depends on the type of PLC data you are using.
The PLC memory types are split into two categories for this purpose.
・ Discrete – X,Y,M,K,T,C,L (contacts)
・ Word – D,N
In either case, you basically convert the PLC octal address to decimal and add the appropriate
MODBUS address (if required). The table below shows the exact equation used for each group of
data.
1-33
For PCk05
MODBUS
PLC MODBUS Data
PCk05 Memory Type QTY(Dec.) Address
Range(Hex) Type
Range(Dec.)
Convert PLC Addr. To Dec. + Start of Range + Data Type
Link Relays (L) 1024 L000 - L3FF 0 - 1023 Input
Inputs (X) 256 X000 - X0FF 2048 - 2303 Input
Link Relays (L) 1024 L400 - L7FF 0 - 1023 Coil
Outputs (Y) 256 Y400 - Y4FF 2048 - 2303 Coil
Internal Relays (M) 256 M000 - M0FF 3072 - 3327 Coil
Keep-Relays (K) 256 K000 - K0FF 3328 - 3583 Coil
Timer Contacts (T) 128 T000 - T07F 6144 - 6271 Coil
Counter Contacts (C) 128 C000 - C07F 6400 - 6527 Coil
Timer Current Values (N) 128 N000 - N07F 0 - 127 Input Register
Counter Current Values (N) 128 N100 - N17F 512 - 639 Input Register
Data Registers (D) 3200 D0000 - D0C7F 640 - 3839 Holding Register
Non-volatile Registers (D) 128 D0C80 - D0CFF 3840 - 3967 Holding Register
For PCk06
MODBUS
PLC MODBUS Data
PCk06 Memory Type QTY(Dec.) Address
Range(Hex) Type
Range(Dec.)
Convert PLC Addr. To Dec. + Start of Range + Data Type
Link Relays (L) 1024 L000 - L3FF 0 - 1023 Input
Inputs (X) 512 X000 - X1FF 2048 - 2559 Input
Link Relays (L) 1024 L400 - L7FF 0 - 1023 Coil
Outputs (Y) 512 Y400 - Y5FF 2048 - 2559 Coil
Internal Relays (M) 512 M000 - M1FF 3072 - 3583 Coil
Keep-Relays (K) 512 K000 - K1FF 3584 - 4095 Coil
Timer Contacts (T) 256 T000 - T0FF 6144 - 6399 Coil
Counter Contacts (C) 128 C000 - C07F 6400 - 6527 Coil
Timer Current Values (N) 256 N000 - N0FF 0 - 255 Input Register
Counter Current Values (N) 128 N100 - N17F 512 - 639 Input Register
3200 D0000 - D0C7F 640 - 3839 Holding Register
Data Registers (D)
4096 D1000 - D1FFF 4096 - 8191 Holding Register
Non-volatile Registers (D) 128 D0C80 - D0CFF 3840 - 3967 Holding Register
The following examples show how to generate the MODBUS address and data type for hosts which
require this format.
Example 1: D0440
Find the MODBUS address for Data Register D0440.
1. Find Data Registers in the table.
2. Convert D0440 into decimal (1088).
3. Add the starting address for the range (640) 1088 + 640 = 1728
4. Use the MODBUS data type from the table.
1-34
Example 2: Y410
Find the MODBUS address for output Y410.
1. Find Y outputs in the table.
2. Subtract the starting address for the range (400) 410 – 400 = 10h
3. Convert 10h into decimal (16).
4. Add the starting address for the range (2048). 16 + 2048 = 2064
5. Use the MODBUS data type from the table.
Coil 2064
Input Register 8
Example 4: M02C
Find the MODBUS address for Internal Relay M02C
1. Find Internal Relays in the table.
2. Convert M02C into decimal (44).
3. Add the starting address for the range (3072). 44 + 3072 = 3116
4. Use the MODBUS data type from the table.
Coil 3116
1-35
For PCk05
MODBUS Address Address
PCk05 Memory PLC MODBUS
QTY(Dec.) Address (484 (584/984
Type Range(Hex) Data Type
Range(Dec.) Mode) Mode)
Convert PLC Addr. To Dec. + Start of Range + Data Type
Link Relays (L) 1024 L000 - L3FF 0 - 1023 1001 100001 Input
Inputs (X) 256 X000 - X0FF 2048 - 2303 1001 100001 Input
Link Relays (L) 1024 L400 - L7FF 0 - 1023 1 1 Coil
Outputs (Y) 256 Y400 - Y4FF 2048 - 2303 1 1 Coil
Internal Relays M000 -
256 3072 - 3327 1 1 Coil
(M) M0FF
Keep-Relays (K) 256 K000 - K0FF 3328 - 3583 1 1 Coil
Timer Contacts
128 T000 - T07F 6144 - 6271 1 1 Coil
(T)
Counter Contacts
128 C000 - C07F 6400 - 6527 1 1 Coil
(C)
Timer Current Input
128 N000 - N07F 0 - 127 3001 30001
Values (N) Register
Counter Current Input
128 N100 - N17F 512 - 639 3001 30001
Values (N) Register
D0000 - Holding
Data Registers (D) 3200 640 - 3839 4001 40001
D0C7F Register
Non-volatile D0C80 - Holding
128 3840 - 3967 4001 40001
Registers (D) D0CFF Register
For PCk06
MODBUS Address Address
PCk06 Memory PLC MODBUS
QTY(Dec.) Address (484 (584/984
Type Range(Hex) Data Type
Range(Dec.) Mode) Mode)
Convert PLC Addr. To Dec. + Start of Range + Data Type
Link Relays (L) 1024 L000 - L3FF 0 - 1023 1001 100001 Input
Inputs (X) 512 X000 - X1FF 2048 - 2559 1001 100001 Input
Link Relays (L) 1024 L400 - L7FF 0 - 1023 1 1 Coil
Outputs (Y) 512 Y400 - Y5FF 2048 - 2559 1 1 Coil
Internal Relays M000 -
512 3072 - 3583 1 1 Coil
(M) M1FF
Keep-Relays (K) 512 K000 - K1FF 3584 - 4095 1 1 Coil
Timer Contacts
256 T000 - T0FF 6144 - 6399 1 1 Coil
(T)
Counter Contacts
128 C000 - C07F 6400 - 6527 1 1 Coil
(C)
Timer Current N000 - Input
256 0 - 255 3001 30001
Values (N) N0FF Register
Counter Current Input
128 N100 - N17F 512 - 639 3001 30001
Values (N) Register
D0000 - Holding
3200 640 - 3839
D0C7F Register
Data Registers (D) 4001 40001
D1000 - Holding
4096 4096 - 8191
D1FFF Register
Non-volatile D0C80 - Holding
128 3840 - 3967 4001 40001
Registers (D) D0CFF Register
1-36
The following examples show how to generate the MODBUS address and data type for hosts which
require this format.
1-37
2. EXECUTION OF PROGRAM
2.1. Processing operation
Sequential program starts at the first location in the sequential program area and stops on an
END instruction followed by internal post-processings such as updating of external I/O data and
self diagnosis. And then the program returns back to the step in which START instruction resides
and repeats steps through the END instruction. The portion of whole program starting from the
beginning of the program to START instruction is called the initial sequential program (initial
program) and a program from START to END instructions is called main sequential program (main
program). A START instruction can be stored at the beginning of whole program to have the main
program only. It becomes a composition only of the main program in PCk05/PCk06.
The processing for external I/O data starts by reading the external I/O data onto the image
memory before the initial sequence program. Then, the initial sequence program and main
sequence program are executed for the data on the image memory.
After executing the END instruction, the data on the image memory is output to the external output
module. That is the end of one scan.
After that, the current external I/O data is read onto the image memory before the START
instruction and the processing shown above is executed as(2), (3), and so on.
2-1
2.2. Subroutine
A part of program which is repeatedly used in different parts of the program is called subroutine
and stored in an area together with other subroutines. When a CALL instruction in a program is
encountered, a subroutine having the label in which the subroutine number denoted by the CALL
instruction is executed. A RET instruction causes the program to return to the step where
processing was made before issuing of the CALL.
Processing order
START (1)
CALL S***
(3) Followed by repetition of
steps (1) to (5)
CALL S***
(5)
END
LABEL S***
(2) (4)
Subroutine
RET
Available number of subroutines are (PCk05:64,S000 to S063) and (PCk06:128, S000 to Sl27).
These subroutines can be nested as shown below.
Processing order
START (1)
CALL S***
Followed by repetition of
(5) steps (1) to (5)
END
LABEL S***
(2)
CALL S###
(4)
RET
LABEL S###
(3)
RET
2-2
2.3. Interrupt program
(1) Interrupt program can be enabled and prohibited by application instructions EI and DI,
respectively.
(2) Default setting upon power-up and reset start is an interrupt program prohibited state(DI
state).EI instruction must be executed beforehand to execute the interrupt program.
(3) When an interruption occurs during execution of basic or application instruction, the interrupt
program is started upon completion of the current execution. This means that an interruption
during execution of an application program requiring a long processing period such as the
block transfer will have a long interrupt latency.
The timer interval between the start of the program and the execution of START instruction, i.e. the
execution period of initial program is called the scan time of initial program; and the interval
between the end of execution of START instruction and the starting of the next execution of START
instruction, i.e. the cycle time of main program, is the scan time of main program.
These scan times are continuously compared with the contents of the scan timer set by parameter
and cause a scan timer over error when one or both of them exceed the preset value. For
obtaining correct comparison result, these parameters should be set to match the scan time of
corresponding program.
The scan time value of program being executed is stored in special register, S001-S003, and can
be read out on the I/O monitor or by an appropriate application instruction.
Address Contents
S001 Maximum scan time in the sequence program (Binary : ms)
S002 Minimum scan time in the sequence program (Binary : ms)
S003 Current scan time in the sequence program (Binary : ms)
2-3
3. PARAMETER
Some functions of the TOYOPUC, such as processing upon occurrence of error are user settable
and are called parameters.
Set the time length of scan timer for initial program and main program in unit of milliseconds.
The time length should be within 2 to 9998 ms. If the scan exceeds the time set by this
parameter, the scan time over error will occur.
Store the program name as a parameter, and the contents of program are easily recognizable.
Setting with PCwin-PCk (For other peripheral devices, refer to their instruction manuals).
Double-click the
item to be set
3-1
(2) CPU operation mode
Scan Time Value of overall Program of the System Scan Time value of Main Program are
set. At the time of Program execution, if set scan time is executed, CPU error will occur.
Program name can be respectively set in the system. Input Range is maximum 8 half size
characters.
Program Name set here will be displayed in the Program Folder of the Project
Screen.
3-2
4. USER MEMORY STRUCTURE
4.1. Program memory structure
The program memory is divided two areas in the program area and the parameter area, and
when each area is blacked out, too maintains the content by the flash memory.
Parameter
1536 bytes
area
Some of the CPU functions such as processing upon occurrence of error and intervals
Periodic interrupts are user settable.
These setting values area called parameters and stored in this area.
Note) All the comments are kept with the file of PCwin-PCk because there is no comment data
area.
4-1
4.2. Data memory structure
4.2.1.1. Data memory address
PCk05 PCk06 Data
holding area
No. Identifier Name at power cut
Word Word
Bit address Points Bit address Points off
address address
X000 X00W X000 X00W
1 X Input 256 512 -
∼0FF ∼0FW ∼1FF ∼1FW
Y400 Y40W Y400 Y40W
2 Y Output 256 512 -
∼4FF ∼4FW ∼5FF ∼5FW
Internal M000 M00W M000 M00W
3 M 256 512 -
relay ∼0FF ∼0FW ∼1FF ∼1FW
K000 K00W K000 K00W
4 K keep-relay 256 512 O
∼0FF ∼0FW ∼1FF ∼1FW
Special V000 V00W V000 V00W
5 V 256 256 -
relay ∼0FF ∼0FW ∼0FF ∼0FW
Extend
M400 M40W M400 M40W
6 M special 256 256 -
relay ∼4FF ∼4FW ∼4FF ∼4FW
T000 T00W T000 T00W
7 T Timer 128 256 -
∼07F ∼07W ∼0FF ∼0FW
C100 C10W C100 C10W
8 C Counter 128 128 -
∼17F ∼17W ∼17F ∼17W
Link relay L000 L00W L000 L00W
9 L 1024 1024 -
input ∼3FF ∼3FW ∼3FF ∼3FW
Link relay L400 L40W L400 L40W
10 L 1024 1024 -
output ∼7FF ∼7FW ∼7FF ∼7FW
Edge P000 P000
11 P - 512 - 512 -
detection ∼1FF ∼1FF
D0000 D0000 3200
∼0C7F ∼0C7F
Data
12 D - 3200 - O
register D1000 4096
∼1FFF
Data
D0C80 D0C80
13 D register - 128 - 128 -
EEPROM ∼0CFF ∼0CFF
Timer N0000 N0000
14 N present - 128 - 256 -
value ∼007F ∼00FF
Counter N0100 N0100
15 N present - 128 - 128 O
value ∼017F ∼017F
S0000 S0000 128
∼007F ∼007F
S0080 64
∼00BF
Special
16 S - 128 - O
register
S00C0 64
∼00FF
S0100 768
∼03FF
4-2
(1) Bit devices area external I/O, internal relay, etc. which are usually set or reset by 1 bit and
designated by the bit address.
Word devices are devices such as the data register handled by a unit of 16 bits and are
designated by the word address.
(2) A bit device can be handled by a unit of 16 bits as if it is a word device. This can be done by
using an application instruction and replacing the lowest bit of a bit address with the
character W (as it implies).
(Note) When handling the data in a unit of 16 bits or 2 bits, use word address. Designation
cannot be made using bit or byte address (refer to the following). Therefore, for
example, 16-point data from X108 to X117 or from D0H to D1L cannot be handled as
1-word data.
(3) When data is divided into two 8 bits, it should be distinguished from the other in addressing
by suffixing H (upper byte) and L (lower byte). For bit devices, W in a word address is
replaced by H or L.
(Note) When handling the data in a unit of 16bits (word) or 32bits, designation starting with
the upper byte of the register cannot be made.
Example: H L
D0 D0H and D1L cannot be designated as one word.
D1
4-3
(EX.)
Bit address Word address Byte address
X000 (LSB) (LSB)
X001
X002
X003
X00L Lower byte
X004
X005
Bit X006
address X007 (MSB)
X00W
area X008 (LSB)
X009
X00A
X00B
X00H Upper byte
X00C
X00D
X00E
X00F (MSB) (MSB)
D0000-0 (LSB) (LSB)
D0000-1
D0000-2
D0000-3
D0000L Lower byte
D0000-4
D0000-5
Word D0000-6
address D0000-7 (MSB)
D0000
area D0000-8 (LSB)
(Example) D0000-9
D0000-A
D0000-B
D000H Upper byte
D0000-C
D0000-D
D0000-E
D0000-F (MSB) (MSB)
0 0
1 0
2 1
3 0
34h
4 1
5 1
6 0
7 0
8 1234h
9 0
A 1
B 0
0
C 12h
D 1
E 0
F 0
0
4-4
5. INSTRUCTION WORDS
5.1. Basic instructions
Processing time μs
Step
No. Symbol Language number Function
PCk05 PCk06
Computing start
1 STR 1 2.0 0.67
(normally ON)
Computing start
2 STR NOT 1 2.3 0.67
(normally OFF)
Series connection
3 AND 1 1.4 0.42
(normally ON)
AND Series connection
4 1 1.6 0.51
NOT (normally OFF)
Parallel connection
5 OR 1 1.6 0.51
(normally ON)
Parallel connection
6 OR NOT 1 1.9 0.55
(normally OFF)
Logic block series
7 AND STR 1 1.3 0.37
connection
Logic block parallel
8 OR STR 1 1.3 0.37
connection
5-1
1. STR, STR NOT
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
STR
STR NOT
(4) Function
STR is the instruction to start operation at normally ON and STR NOT at normally OFF, each
storing ON/OFF information of the designated device in the accumulator as the operation
result.
(5) Example
5-2
2. AND, AND NOT
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
AND
AND NOT
(4) Function
AND is the instruction to make serial connection at normally ON and AND NOT instruction at
normally OFF. AND operation(logical product) is carried out between ON/OFF information of
the specified device and the operation result stored in the accumulator. The logical product is
stored into the accumulator, replacing the current content.
5-3
3. OR, OR NOT
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
OR
OR NOT
(4) Function
OR is the instruction to make parallel connection at normally ON and OR NOT instruction at
normally OFF. OR operation(logical sum) is carried out between ON/OFF information of the
specified device and the operation result stored in the accumulator. The logical sum is stored
in the accumulator, replacing the current content.
5-4
4. AND STR
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1
(3) Symbol
(4) Function
Carries out AND operation between two logical blocks and makes the logical product as the
new operation result.
(6) Notes
Available instructions are up to 8 when using AND STR consecutively. Use of more than 8
instructions will have unexpected result.
5-5
5. OR STR
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1
(3) Symbol
(4) Function
Carries out OR operation between two logical blocks and makes the logical sum as the new
operation result.
(6) Notes
Available instructions are up to 8 when using OR STR consecutively. Use of more than 8
instructions will have unexpected result.
5-6
6. OUT
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○
(3) Symbol
(4) Function
Outputs the operation result stored in the accumulator to the specified device.
5-7
7. SET
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○
(3) Symbol
(4) Function
Turns on specified keep relay if the operation result before SET instruction is ON("1").
5-8
8. RST
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○
(3) Symbol
(4) Function
Turns off the specified keep relay if the operation result before RST instruction is ON("1").
5-9
9. PTS, NTS
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○
(3) Symbol
(4) Function
PTS turns on("1")the previous operation result for 1 scan period when the previous result
changes from OFF to ON.
NTS turns on("1")the previous operation result for 1 scan period when the previous result
changes from ON to OFF.
Time chart
(6) Notes
The address of device "P" available for instructions PTS and NTS is 512 points. Use only one
address for one device and avoid address overlapping.
Refer to the following page restrictions upon use.
5-10
Notes on use in a subroutine or interrupt
When used in a subroutine or interrupt, the PTS or NTS instruction may not be detected in
some cases.
Example
As shown in the time chart, if X20 is ON when X10 turns OFF from ON, Y100 does not turn
ON for one scan even when X10 and X20 turn ON next.
If X20 turns OFF when X10 is ON, Y100 functions normally (that is, when X20 functions as
shown by the dotted line, Y100 and P000 function as shown by the dotted line, as well)
Program example
Time chart
5-11
5.2. Timer and counter instructions
(1) Timer and counter commands
Processing time μs
Classifi
Function Mnemonic
Step
Symbol (example) Content of
cation number computation PCk05 PCk06
T000 10ms timer of 99.99
Direct-desig
sec at setup value
nated 10ms TMRH 3 59.5 48.4
TMRH K=99.99
timer
T001 10ms timer on which
Indirect-desi
D0100 content is set up
gnated TMRH 2 64.8 51.4
TMRH S=D0100 (as a setup value)
10ms timer
Timer
T002 100ms timer of 999.9
Direct-desig
sec at setup value
nated TMR 3 58.1 20.0
TMR K=999.9
100ms timer
T003 100ms timer on which
Indirect-desi
D0101 content is set up
gnated TMR 2 64.0 26.8
TMR S=D0101 (as a setup value)
100ms timer
5-12
(Note) PCk05 becomes (T000-T07F) in the address that can be used for the timer.
PCk05 becomes (T000-T0FF) in the address that can be used for the timer.
The address that can be used for the counter becomes it in case of both
(C100-C17F) PCk05 and PCk06.
The value becomes BCD set now a set value of the timer and the counter of PCk05/PCk06.
Do not set the binary.
(1) When “1” is set (0.1S for 100ms timer and 0.01S for 10ms timer),the timer may expire
instantaneously. Timer accuracy is 0 to -1 or –(scan time). Thus, when the increment of the
timer (100ms or 10ms) is smaller than the scan time, the timer may expire instantaneously
with a setting other than “1”.
When the timer instruction is used in a subroutine or interrupt, it may turn ON immediately in
some cases.
If X20 is OFF when X10 turns ON and the timer instruction is executed when X10 and X20
turns ON next, the timer adds the time lapsed in the section indicated by the arrow in the time
chart and thus, does not function normally.
If the subroutine is such that it is executed every scan, use of the timer in the subroutine
causes no problem.
Program example
Time chart
Since the instruction is executed during the period indicated by T, the timer
cannot determine when X20 has turned ON. Therefore, the timer assumes that the condition
has been satisfied (X20=ON) immediately after the previous instruction was executed and
thus adds the lapsed time T to the current value. Therefore, when the timer set value is less
than or equal to T, the timer turns ON immediately after the timer instruction is executed.
5-13
(3) Present value register (N****)
Each timer counter is stored in the present value register(N****) by the BCD4 digit now. It is
also possible to monitor each present value, and to change the value directly by the
application instruction now.
The value becomes BCD set now a set value of the timer and the counter of PCk05/PCk06.
Do not set the binary.
5-14
1.TMRH (Direct mode 10ms timer)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○
(3) Symbol
(4) Function
The count value of this timer is directly set by a constant in 10ms units. If the operation done
before the issue of TMRH instruction has resulted in ON, the timer counting the time end when
the terminal time is reached, turns on the specified device
(PCk05:T000-T07F,PCk06:T000-T0FF).
5-15
2.TMRH (Indirect mode 10ms timer)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
The timer loads the count value(BCD 1-9999)stored in the specified register. If the operation
before the issue of TMRH instruction has resulted in ON, the timer counts out time in 10 ms
units and when the terminal count is reached, turns on the specified device
(PCk05:T000-T07F,PCk06:T000-T0FF).
5-16
3.TMR (Direct mode 100ms timer)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○
(3) Symbol
(4) Function
The count value of this timer is directly set by a constant in 100ms units. If the operation done
before the issue of THR instruction has resulted in ON, the timer counting the timer end when
the terminal time is reached, turns on the specified device
(PCk05:T000-T07F,PCk06:T000-T0FF).
5-17
4.TMR (Indirect mode 100ms timer)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
The timer loads the count value(BCD 1-9999)stored in the specified register. If the operation
before the issue of TMR instruction has resulted in ON, the timer counts out time in 100 ms
units and when the terminal count is reached, turns on the specified device
(PCk05:T000-T07F,PCk06:T000-T0FF).
5-18
5.TMRSH (Direct mode 10ms integrating timer)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○
(3) Symbol
(4) Function
The count value of this integrating timer is directly set by a constant in 10ms units. If the
operation done on the T input has resulted in ON, the timer starts counting the time and when
the terminal time is reached, turns on the specified device
(PCk05:T000-T07F,PCk06:T000-T0FF).
The contents(current value)is kept unclear until the next R input becomes ON.
The passage value stores specified device number T(n) in both registers of value register
N(n) and N(n+1) by the BCD8 digit now. Therefore, it is noted not to be able to use T(n+1).
For instance, when the timer of T010 is used, T011 cannot be used.
5-19
6.TMRSH (Indirect mode 10ms integrating timer)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
The integrating timer loads the count value(1-65535)stored in the specified register. If the
operation done on T input has resulted in ON, the timer counts out time in 10 ms units and
when the terminal count is reached, turns on the specified device
(PCk05:T000-T07F,PCk06:T000-T0FF).
The contents(current value)is kept unclear until the next R input becomes ON.
A set value is set to both registers of specified register number (n) and (n+1) by BCD8 digit
(1~65535).
Example) For set value D102.
D102 setting value subordinate position BCD4 digit.
D103 setting value high rank BCD4 digit.
The passage value is stored in both registers of value register N(n) and N(n+1) by the BCD8
digit about specified device number T(n) now. Therefore, it is noted not to be able to use
T(n+1).
For instance, when the timer of T010 is used, T011 cannot be used.
Example) Four T010→N010 passage value subordinate position digits.
Four high rank of T011→N011 passage value digits.
5-20
7.TMRS (Direct mode 100 ms integrating timer)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○
(3) Symbol
(4) Function
The count value of this integrating timer is directly set by a constant in 100 ms units. If the
operation done on the T input has resulted in ON, the timer starts counting the time and when
the terminal time is reached, turns on the specified device
(PCk05:T000-T07F,PCk06:T000-T0FF).
The contents(current value)is kept unclear until the next R input becomes ON.
The passage value is stored in both registers of value register N(n) and N(n+1) by the BCD8
digit about specified device number T(n) now. Therefore, it is noted not to be able to use
T(n+1).
For instance, when the timer of T010 is used, T011 cannot be used.
Example) Four T010→N010 passage value subordinate position digits.
Four high rank of T011→N011 passage value digits.
5-21
8.TMRS (Indirect mode 100 ms integrating timer)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
The integrating timer loads the count value(1-65535)stored in the specified register. If the
operation done on T input has resulted in ON, the timer counts out time in 100 ms units and
when the terminal count is reached, turns on the specified device
(PCk05:T000-T07F,PCk06:T000-T0FF).
The contents(current value)is kept unclear until the next R input becomes ON.
A set value is set to both registers of specified register number (n) and (n+1) by BCD8 digit
(1~65535).
Example) For set value D104.
D104 setting value subordinate position BCD4 digit.
D105 setting value high rank BCD4 digit.
The passage value is stored in both registers of value register N(n) and N(n+1) by the BCD8
digit about specified device number T(n) now. Therefore, it is noted not to be able to use
T(n+1).
For instance, when the timer of T010 is used, T011 cannot be used.
Example) Four T010→N010 passage value subordinate position digits.
Four high rank of T011→N011 passage value digits.
5-22
9.CNT (Direct mode up counter)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○
(3) Symbol
(4) Function
An up counter whose quantity is directly set with a constant. If the R input is OFF, the counter
increments the current value by 1 upon turning on of the CK input and turns on the specified
device (C100-C17F)when the terminal count is reached. The counter clears the current value
upon ON of R input, turning off the specified device.
The count value (present value) is stored in value register N(n) by the BCD4 digit about
specified device number C(n) now. Therefore, the upper bound of the count value becomes
9999.
5-23
10.CNT (Indirect mode up counter)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
The up counter loads the count value(BCD 1-9999)stored in the specified register. If the R
input is OFF, the counter increments the current value by 1 upon turning on of the CK input
and turns on the specified device(C100-C17F)when the terminal count is reached. The
counter clears the current value upon ON of R input, turning off the specified device.
The count value (present value) is stored in value register N(n) by the BCD4 digit about
specified device number C(n) now. Therefore, the upper bound of the count value becomes
9999.
5-24
11. CNTH (Direct mode up/down counter)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○
(3) Symbol
(4) Function
It is ups and downs counter that specifies a set value directly by the constant.
Whenever the UP input is turned on when R input is turned off, +1 does the count value
(present value). And, whenever the DOWN input is turned on, -1 does the count value
(present value).
Specified device (C000~C17F) is turned on when the value is corresponding to a set value
now. It assumes it any more as turning on. Moreover, when R input is turned on, the count
value (present value) becomes 0.
When the UP input and the DOWN input simultaneous are input, it doesn't count. Moreover,
the DOWN input when the count value (present value) is 0 is 0. After the value of the count
(present value), the limit becomes 99999999 of the BCD 8 digits though the upper bound of a
set value is 65535.
The count value (present value) stores specified device number C(n) in both registers of value
register N(n) and N(n+1) by the BCD8 digit now. Therefore, it is noted not to be able to use
C(n+1).
For instance, when the counter of C110 is used, C111 cannot be used.
Example) Four C110→N110 passage value subordinate position digits.
Four high rank of C111→N111 passage value digits.
5-25
(5) Example of program
Time chart
5-26
12.CNTH (Indirect up/down counter)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
Device ○
Setting value ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
It is a set value and a done ups and downs counter as for the content of the specified
register (..digit.. 1~65535-BCD8).
Whenever the UP input is turned on when R input is turned off, +1 does the count value
(present value). And, whenever the DOWN input is turned on, -1 does the count value
(present value).
Specified device (C000~C17F) is turned on when the value is corresponding to a set value
now. It assumes it any more as turning on. Moreover, when R input is turned on, the count
value (present value) becomes 0.
When the UP input and the DOWN input simultaneous are input, it doesn't count. Moreover,
the DOWN input when the count value (present value) is 0 is 0. After the value of the count
(present value), the limit becomes 99999999 of the BCD 8 digits though the upper bound of a
set value is 65535.
The count value (present value) stores specified device number C(n) in both registers of value
register N(n) and N(n+1) by the BCD8 digit now. Therefore, it is noted not to be able to use
C(n+1).
For instance, when the counter of C110 is used, C111 cannot be used.
Example) Four C110→N110 passage value subordinate position digits.
Four high rank of C111→N111 passage value digits.
5-27
(5) Example of program
Time chart
5-28
5.3. Contact type application instructions
These are applied instructions and function as contact, i. e. they compare the values of two data,
and when the result meets the predetermined condition, turn ON. The instructions are roughly
classified into STR, AND OR, as appropriate to use in the sequence circuit.
This type of instruction is used at the beginning of an operation as the basic STR instruction is.
The result of the comparison or operation is stored in the accumulator as ON/OFF information.
Used for serial connection as the basic AND instruction is. The result of the previous
operation and the one obtained from the comparison done by this instruction are ANDed and
the logical product is stored in the accumulator.
(3) OR format
5-29
Contact type applied commands
5-30
1. W=H 4-digit hexadecimal constant comparison (=)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Compares a 16-bit data from the register with hexadecimal 4-digit constant. If they are equal,
provides ON state.
2) Turns on Y40F if the data register D0200 is FFFF in hexadecimal number and X000 is ON.
3) Turns on Y40F if the data register D0200 is AAAA in hexadecimal number or if X000 is ON.
5-31
2. W=N Word data comparison (=)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Compares two 16-bit data and provides ON state if they are equal.
1) Turns on Y423 if the current count of C100(contents of the current value register N100)and
that of C101(current value counter N101)are equal.
2) Turns on Y423 if the contents of Y410-Y41F and D0100are equal and X000 is ON.
3) Turns on Y423 if the contents of the data registers D0200 and D0201 are equal or if X000 is
ON.
5-32
3. W<>H 4-digit hexadecimal constant comparison (<>)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Compares a 16-bit data from the register with 4-digit hexadecimal constant. If they are not
equal, provides ON state.
2) Turns on Y40F if the data register D0200 is not FFFF in hexadecimal number and X000 is ON.
3) Turns on Y40F if the data register D0200 is not AAAA in hexadecimal number or if X000 is
ON.
5-33
4. W<>N Word data comparison (<>)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Compares two 16-bit data and provides ON state if they are not equal.
1) Turns on Y423 if the current count of C100(contents of the current value register N100)and
that of C101(current value counter N101)are not equal.
2) Turns on Y423 if the contents of Y410-Y41F and D0100 are not equal and X000 is ON.
3) Turns on Y423 if the contents of the data registers D0200 and D0201 are not equal or if X000
is ON.
5-34
5. W>=H 4-digit hexadecimal constant comparison (>=)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Compares a 16-bit data from the register with 4-digithexadecimal constant, and if the register
data is larger than or equal to the constant, provides ON state.
1) Turns on Y40F if the data in X000-X00F is larger than or equal to 1234 in BCD number.
2) Turns on Y40F if the data register D0100 is larger than or equal to 5555 in hexadecimal
number and X000 is ON.
3) Turns on Y40F if the data register D0200 is larger than or equal to AAAA in hexadecimal
number or if X000 is ON.
5-35
6. W>=N Word data comparison (>=)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Compares two 16-bit data and if the first data is larger than or equal to the second, provides
ON state.
1) Turns on Y423 if the current count of C100(contents of the current value register N100)is
larger than or equal to that of C101(current value counter N101).
2) Turns on Y423 if the value represented by Y410-Y41F is larger than or equal to the contents
of D0100 and X000 is ON.
3) Turns on Y423 if the contents of the data register D0200 is larger than or equal to that of
D0201 or if X000 is ON.
5-36
7. W<H 4-digit hexadecimal constant comparison (<)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Compares a 16-bit data from the register with 4-digit hexadecimal constant, and if the register
data is smaller than the constant, provides ON state.
1) Turns on Y40F if the data in X000-X00F is smaller than 1234 in BCD number.
2) Turns on Y40F if the data register D0100 is smaller than 5555 in hexadecimal number and
X000 is ON.
3) Turns on Y40F if the data register D0200 is smaller than AAAA in hexadecimal number or if
X000 is ON.
5-37
8. W<N Word data comparison (<)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Compares two 16-bit data and if the first data is smaller than the second, provides ON state.
1) Turns on Y423 if the current count of C100(contents of the current value register N100)is
smaller than that of C101 (current value counter N101).
2) Turns on Y423 if the value represented by Y410-Y41F is smaller than the contents of D0100
and X000 is ON.
3) Turns on Y423 if the contents of the data register D0200 is smaller than that of D0201 or if
X000 is ON.
5-38
5.4. Output type application instructions
Output type application instructions are used to process numeric data and are executed if the previous
operation resulted in ON.
The output type application instructions are classified as follows :
Transfer
Arithmetic operation
Logical operation
Increment/decrement
Search
Data exchange
Comparison
Bit operation
Shift
Rotate
Programmed branch
Master control
Sequential interrupt
Label
Special unit data transfer
Others
5-39
Note1 : Some output type application instructions alter the resulting flag prepared in the special relay
in accordance with the result of operation made by these instructions. The altered flag can
be used as one of the conditions for the next operation. The table below shows the
available resulting flags.
5-40
(4) Output-type application instructions
WMOVE S D
transfer
Direct
16bits 0 WMOVE DMOVE S data transferred to 60.3 7.4 21.1 2.0
transfer
- - - - - - - - - -
D
WBMOV S D K
Block
↔
transfer
16bits 119 WBMOV are transferred to the
- - - - - - - - - 148.4+16xK 10.7 78.2+9.5xK 2.9
area which of head
Transfer
address is D.
WXCH D1 D2
16bits 2 WXCH For 16bit change, the 161.7 17.5 50.6 5.0
Data change DXCH contents of D1 and D2 - - - - - - - - - -
are changed.
↔
Block change 16bits 135 WBXCH D2 addresses and - - - - - - - - - 102.1 3.0
which are shown with
constant K are
changed.
WFIL H S K H is transferred to an
area wherein head
↔
Data fill 16bits 129 WFIL address is S and the
- - - - - - - - - 44.2+8.0xK 3.0
number of data is K.
S,D : register H : hexadecimal constant K : Decimal constant
5-41
Flag Execution time (µs)
Classification No. Command
Symbol Function V5E V58 V57 V56 V55 V54 V53 V52 V51 V50 PCk05 PCk06
word
Not Not
(DER) (CY) (BO) (HCY) (HBO) (Z) (>) (=) (<) (ER) Execution Execution
execution execution
↔
stored in D. Data are all handled
- - - - - - -
169 D+ as binary number. 43.8 2.5
32bits
Add
↔
stored in D. The data are all
- - - - - -
178 D+P handled as BCD. 8 1.25 43.8 2.5
8digits
↔
D- - - - - - - -
in D. The data are all handled as
171 D- binary number. 43.8 2.5
32bits
Deduct
↔
in D. The data are all handled as
- - - - - -
5-42
↔
16bits 94 W* stored in D. The data are all
- - - - - - - - -
handled as binary number. 8 1.25 43.8 2.5
Multiply
↔
stored in D. The data are all
- - - - - - - -
183 D*P handled as BCD. 8 1.25 43.8 2.5
8digits
↔
16bits 175 W/ in D and the remainder stored in - - - - - - - -
D+1. The data are all handled as
binary number. 8 1.25 43.8 2.5
Divide
↔
in D and the remainder stored in - - - - - - -
D+1. The data are all handled as
8digits 186 D/P BCD. 8 1.25 43.8 2.5
↔
- - - - - - -
Constant addition
↔
- - - - - -
S content and constant K are added and
D+HP S K
8 digits 328 D+HP the result is stored in the address next to 58∼64 0.4 58∼64 0.4
S. The data are all handled as BCD.
After S content and constant H were
W-H S H D 3.2 0.4 3.2 0.4
16bit 330 W-H deducted, the result is stored in D. The
Binary
↔
Constant deduction
- - - - - - -
S content and constant H are deducted
D-H S H
32bit 331 D-H and the result is stored in D. The data 4.52 0.4
are all handled as binary number.
W-HP After S content and constant K were
S K D
4 digits 333 W-HP deducted, the result is stored in D. The 22.76 0.4 22.76 0.4
data are all handled as BCD.
BCD
↔
- - - - - -
S content and constant K are deducted and the
8 digits 334 D-HP D+HP S K result is stored in the address next to S. The 55∼67 0.4 55∼67 0.4
Arithmetic computation
W*H S H D
↔
336 W*H 4.6 0.4 4.6 0.4
multiplication
↔
4 digits 339 W*HP multiplied, the result is stored in D. The - - - - - - - - 0.4 0.4
data are all handled as BCD.
W/H
Binary
↔
16bit 342 W/H - - - - - - - - 0.4 0.4
remainder stored in next address. The
data are all handled as binary value.
After S content and constant K were
W/HP
BCD
↔
4 digits 345 W/HP - - - - - - - 56.92 0.4 56.92 0.4
remainder stored in next address. The
data are all handled as BCD.
↔
16bit 63 WINC - - - - - - - 4.6 0.4 4.6 0.4
Increment
↔
4 digits 200 WINCP compared with the content of S1. The - - - - - - 0.4 0.4
data are handled as BCD.
-1 is deducted from the content of D.
WDEC D
28∼30 28∼30
↔
0.4 0.4
Decrement
↔
4 digits 203 WDECP - - - - - - - - 56.92 0.4 56.92 0.4
The data are all handled as BCD.
Logical 16bits 187 WAND WAND S1 S2 D Logical product(AND) of S1 content 83.8 11.3 29.0 3.0
DAND
↔
product and S2 content is determined. The - - - - - - - - -
(AND) result is stored in D.
32bits 188 DAND 88.5 11.2 31.3 3.0
16bits 189 WOR Logical sum (OR) of S1 content and 84.2 11.1 29.2 3.0
Logical sum WOR S1 S2 D
↔
(OR) DOR S2 content is determined. The result - - - - - - - - -
is stored in D.
32bits 190 DOR 89.0 11.3 31.4 3.0
↔
(NOT)
each bit is 1 and to 1 if it is 0.). The - - - - - - - - -
result is stored in D.
32bits 192 DNOT 71.4 9.8 24.9 3.0
Exclusive 16bits 193 WXOR Exclusive logical sum (XOR) of S1 83.8 11.3 29.1 3.0
WXOR S1 S2 D
↔
logical sum DXOR content and S2 content is determined. - - - - - - - - -
(XOR) The result is stored in D.
11.2 3.0
Logic calculation
ANDH S H D
16bits 348 WANDH and constant H was computed, the 79.3 11.3 26.8 3.0
Constant result is stored in D.
↔
logic - - - - - - -
- -
product After logic product(AND) of S content
32bits 349 DANDH DANDH H
and constant H was computed, the 84.2 11.4 28.1 3.0
S result is stored in address next to S.
↔
logic - - - -
- - - - -
sum After logic sum (OR) of S content and
32bits 352 DORH DORH S H constant H was computed, the result is 84.6 11.2 28.2 3.0
stored in address next to S.
↔
logic After exclusive logic sum (XOR) of S - - - - - - - - -
sum content and constant H was
32bits 355 DXORH DXORH S H
computed, the result is stored in
84.2 11.4 27.8 3.0
address next to S.
↔
Data search 2 16bits 213 WSRH2 with K from the address of S2, - - - - - - - - -
CARRY FLAG is turned and the
position data is stored in S1+1 and the
matched data stored in S2
respectively.
4 digits ->
136.1 9.7 121.3 2.9
↔
16bits 3 WBIN WBIN S D - - - - - - - -
BCD -> BCD data stored in S is converted to
Conversion to DBIN
binary data and, thereafter, stored in D.
binary data 8 digits ->
141 9.8 122.6 2.9
↔
32bits 153 DBIN - - - - - - - -
16bits -> 4
220.2 9.6 116.3 2.9
↔
digits 4 WBCD WBCD S D - - - - - - - - -
Binary ->
DBCD Binary data stored in S is converted to
Conversion to BCD data and, thereafter, stored in D.
BCD data 32bits -> 8
225.1 9.7 117.6 2.9
↔
digits 155 DBCD - - - - - - - - -
↔
156 JBIN JBIN S D K - - - - - - - - -
5-45
↔
157 BJIS hexadecimal number and the stored in - - - - - - - - -
JIS
the area having D as its head address, K
after converted to JIS code.
DECO S D The content of S is stored in D, after its
4 ->16 DECODER 50 DECO lower 4bit was decoded to - - - - - - - - - - 99.6 13.6 32.5 4.0
hexadecimal data.
ON bit position, of 16 bits in the S
content, is converted to binary data
176.1 24.7 89.9 6.9
↔
16 ->4 DECODER 51 ENCO ENCO S D
(two or more ON bits; Priority is given - - - - - - - - -
to the lower bit.) and the converted
data is stored in lower 4 bits of D.
↔
Comparison
↔
32bits 211 DCP - - - - - - -
Bit operation
↔
16bits 209 WSUM - - - - - - - - -
WSUM S D The sum of bits under ON, of bits in S
On bit counter DSUM content, is counted and the result is
stored in D.
82.9 9.7 28.2 3.0
↔
32bits 210 DSUM - - - - - - - - -
↔
shift
WUP The least significant data is 0. - - - - - - - - -
16bits 253 WUP DUP 153.4 3.0
↔
shift DDOWN are shifted to lower significant direction.
- - - - - - - - -
16bits 257 WDOWN Most significant data is 0. 153.3 3.0
DRR S K
Rotate to right S content is rotated to the right, by the bit
32bits 244 DRR - - - - - - - - - - 35.3 3.0
without carry number designated with K.
Rotate
JMP Ln
Jump 272 JMP Jumped into label No. Ln. - - - - - - - - - - 5.1 4.8
START
Program start 448 START Indicating start-up of sequence program. - - - - - - - - - -
END
Program end 452 END Indicating end of main sequence program. - - - - - - - - - -
Label
DI
Interrupt inhibit 276 DI Inhibits sequence interrupt - - - - - - - - - - 9.4 2.3 9.4 2.3
Sequential interrupt
EI
Interrupt enable 277 EI Permits sequence interrupt - - - - - - - - - - 24.2 2.7 24.2 2.7
Return from
interrupt RETI
468 RETI Indicating end of the interrupt program - - - - - - - - - - 6.6 - 6.6 -
processing
routine
STOP
Program stop 287 STOP Run of sequence program is stopped. - - - - - - - - - - 10 1.1 10 1.1
Others
WDR
Scan time reset 46 WDR The scan time monitor timer is reset. - - - - - - - - - - 5.9 2.2 5.9 2.2
Transfer instruction is used to store numeric data into register or to transfer data between registers.
Transfer instructions are classified as follows.
5-49
1. WMOV 4-digit Hex constant transfer (FUN101)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Stores a hexadecimal constant into the register. The available constants are 0 to FFFF for
WMOV.
(5) Flag
No change
5-50
2. DMOV 8-digit Hex constant transfer (FUN102)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FE 400 - 4FE
OP1 ○
OP2 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FE 400 - 4FE
OP1 ○
OP2 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Stores a hexadecimal constant into the register. The available constants are 0 to FFFFFFFF
for DMOV.
(5) Flag
No change
Transfers "FEDCBA98" (hex) to data register D0003 and D0002 when K000 is ON.
5-51
3. WMOVT 4-digit Hex constant transfer to two places (FUN 110)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FE 400 - 4FE
OP1 ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FE 400 - 4FE
OP1 ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Stores the same Hex constant into two registers, the available constants are 0 to FFFF for
WOVT instruction.
(5) Flag
No change
5-52
4. WMOVE 2-byte data direct transfer (FUN0)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FF 400 - 4FF
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Transfers data from OP1 register to OP2register, leaving OP1 register data intact.
(5) Flag
No change
5-53
5. DMOVE 4-byte data direct transfer (FUN111)
M
X Y K V T C L P D N S Constant
PCk05 000 - 0FE 400 - 4FE
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
PCk06 000 - 1FE 400 - 4FE
OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Transfers data from OP1 register to OP2register, leaving OP1 register data intact.
(5) Flag
No change
5-54
6. WBMOV Word data block transfer (FUN119)
M
X Y K V T C L P D N S Constant
000 - 0FF 400 - 4FF
PCk05 OP1 ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○
M
X Y K V T C L P D N S Constant
000 - 1FF 400 - 4FF
PCk06 OP1 ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○
(3) Symbol
(4) Function
Transfers data in OP1 and subsequent registers to locations covered by OP2 and subsequent
registers with the number of data being specified by OP3. The maximum transferred data is
1024 words for WBMOV.
(5) Flag
V50 Error flag(ER): Is set when the transfer source and destination are outside of the data
memory area or when the transferred data exceeds the specified value.
5-55
7. WXCH 16-bit data exchange(FUN2)
M
X Y K V T C L P D N S Constant
000 - 0FF 400 - 4FF
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
000 - 1FF 400 - 4FF
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Swaps the contents of OP1 register and those in OP2.
(5) Flag
No change
5-56
8. DXCH 32-bit data exchange(FUN133)
M
X Y K V T C L P D N S Constant
000 - 0FE 400 - 4FE
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
000 - 1FE 400 - 4FE
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Swaps the contents of OP1 register and those in OP2.
(5) Flag
No change
5-57
9. WBXCH Word data block exchange (FUN 135) PCk06
M
X Y K V T C L P D N S Constant
000 - 1FF 400 - 4FF
PCk06 OP1 ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○
(3) Symbol
(4) Function
Swaps data stored in the locations starting at OP1 address with the data in the locations
starting at OP2 address. The number of piece of data to be swapped is up to 256 each and
specified by OP3.
(5) Flag
V50 Error flag(ER) : Is set if the locations to be exchanged are outside of the data memory
area.
5-58
10. WFIL Word data fill (FUN 129) PCk06
M
X Y K V T C L P D N S Constant
000 - 1FF 400 - 4FF
PCk06 OP1 ○
OP2 ○ ○
OP3 ○
(3) Symbol
(4) Function
Stores the Hex constant to the location starting at the address specified by content of OP2
and has the number of data specified by OP3.
The length of the location is 1024 data at maximum.
(5) Flag
V50 Error flag(ER) : Is set when the transfer destination is outside of the data memory.
5-59
5.4.2. Arithmetic operations
Instructions which carry out arithmetic operation on contents of registers are divided into the
following four.
Addition................Adds data of register to another register and stores the result into another
register.
Subtraction...........Subtracts data of register from another register and stores the result into
another register.
Multiplication........Multiplies data of register with another register and stores the result into
another register.
Division................Divides data of register by data of another register and stores the register
into another register.
5-60
11. W+ Word data binary addition (FUN 92)
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Adds the content of OP1 register to that of OP2 and stores the result to OP3 register. All data
is processed as unsigned binary numbers.
(5) Flag
V58 Carry flag(CY) : Is set when carrying is generated from bit 31 as a result of addition.
V56 Half carry flag(HCY) : Is set when carrying is generated from bit 15 aiming at bit 16 as a
result of addition.
V54 Zero flag(Z) : Is set when add operation results in 0.
5-61
12. D+ 32-bit data binary addition (FUN 169) PCk06
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
D+
(4) Function
Adds the content of OP1 register to that of OP2 and stores the result to OP3 register. All data
is processed as unsigned binary numbers.
(5) Flag
V58 Carry flag(CY) : Is set when carrying is generated from bit 31 as a result of addition.
V56 Half carry flag(HCY) : Is set when carrying is generated from bit 15 aiming at bit 16 as a
result of addition.
V54 Zero flag(Z) : Is set when add operation results in 0.
5-62
13. W+P 4-digit BCD addition (FUN 10)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Adds the content of OP1 register to that of OP2 register, both as BCD codes, and stores the
resultant BCD codes into OP3 register.
(5) Flag
V58 Carry flag(CY) : Is set when carrying is generated from bit 31 as a result of addition.
V56 Half carry flag(HCY) : Is set when carrying is generated from bit 15 aiming at bit 16 as a
result of addition.
V54 Zero flag(Z) : Is set when add operation results in 0.
V5E Data error flag(DER) : Is set if content of OP1 register or OP2 register is not in BCD
format
5-63
14. D+P 8-digit BCD addition (FUN 178)
M
X Y K V T C L P D N S Constant
0W – 0EW 40W – 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1EW 40W - 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Adds the content of OP1 register to that of OP2 register, both as BCD codes, and stores the
resultant BCD codes into OP3 register.
(5) Flag
V58 Carry flag(CY) : Is set when carrying is generated from bit 31 as a result of addition.
V56 Half carry flag(HCY) : Is set when carrying is generated from bit 15 aiming at bit 16 as a
result of addition.
V54 Zero flag(Z) : Is set when add operation results in 0.
V5E Data error flag(DER) : Is set if content of OP1 register or OP2 register is not in BCD
format
5-64
15. W- Word data binary subtraction (FUN 93)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Subtracts the content of OP2 register from that of OP1 register and stores the result into OP3
register. All data in unsigned binary format.
(5) Flag
5-65
16. D- 32-bit data binary subtraction (FUN 171) PCk06
M
X Y K V T C L P D N S Constant
0W - 1EW 40W - 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Subtracts the content of OP2 register from that of OP1 register and stores the result into OP3
register. All data in binary format.
(5) Flag
5-66
17. W-P 4-digit BCD subtraction (FUN 11)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Subtracts the content(BCD code)of OP2register from that(BCD code)of OP1 register and
stores the result into OP3register in BCD code.
(5) Flag
5-67
18. D-P 8-digit BCD subtraction (FUN 180)
M
X Y K V T C L P D N S Constant
0W – 0EW 40W - 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1EW 40W - 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Subtracts the content(BCD code)of OP2register from that(BCD code)of OP1 register and
stores the result into OP3register in BCD code.
(5) Flag
5-68
19. W* Word data binary multiplication (FUN 94)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0W -0EW
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 1EW
(3) Symbol
(4) Function
Multiplies contents of OP1 and OP2 registers and stores the result into OP3 register. All data
handled as unsigned binary numbers.
(5) Flag
5-69
20. W*P 4-digit BCD multiplication (FUN 182)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 0EW
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 1EW
(3) Symbol
(4) Function
Multiplies the contents of OP1 and OP2 registers as BCD code and stores the resultant BCD
code into OP3 register.
(5) Flag
5-70
21. D*P 8-digit BCD multiplication (FUN 183)
M
X Y K V T C L P D N S Constant
0W - 0EW 40W - 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 0CW
M
X Y K V T C L P D N S Constant
0W - 1EW 40W - 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0 W- 1CW
(3) Symbol
(4) Function
Multiplies the contents of OP1 and OP2 registers as BCD code and stores the resultant BCD
code into OP3 register.
(5) Flag
When M000 turns ON from OFF, multiplies BCD 8-digit data stored in D0149 and D0148 with
that in D014B and D014A and stores the result into D014D and D014C, and D014F and
D014E.
5-71
22. W/ Word data binary division 2 (FUN 175)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0W -0EW
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 1EW
(3) Symbol
(4) Function
Divides the content of OP1 register by that of OP2 register and stores the quotient into OP3
register and the remainder into the register at the address following that of OP3.
(5) Flag
5-72
23. W/P 4-digit BCD division (FUN 185)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 0EW
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 1EW
(3) Symbol
(4) Function
Divides the content of OP1 register(BCD code) by the content of OP2 register (BCD code) and
stores the quotient into OP3 register and the remainder into the register at the address
following that of OP3.
(5) Flag
5-73
24. D/P 8-digit BCD division (FUN 186)
M
X Y K V T C L P D N S Constant
0W - 0EW 40W - 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 0CW
M
X Y K V T C L P D N S Constant
0W - 1EW 40W - 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
○
OP3 ○ ○ ○ ○ ○ ○
0 W- 1CW
(3) Symbol
(4) Function
Divides the content of OP1 register(BCD code) by the content of OP2 register (BCD code) and
stores the quotient into OP3 register and the remainder into the register at the address
following that of OP3.
(5) Flag
5-74
25. W+H Addition of hexadecimal 4-digit constant (FUN 324)
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Adds the register content of OP1 and hexadecimal number and stores the result in the register
of OP3. The range of constants is 0 ~ FFFF.
(5) Flag
V58 Carry flag(CY) : Is set when carrying is generated from bit 31 as a result of addition.
V56 Half carry flag(HCY) : Is set when carrying is generated from bit 15 aiming at bit 16 as a result
of addition.
V54 Zero flag(Z) : Is set when add operation results in 0.
5-75
26. D+H Addition of hexadecimal 8-digit constant (FUN 325) PCk06
M
X Y K V T C L P D N S Constant
0W – 1CW 40W – 4CW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Adds the register content of OP1 and hexadecimal number and stores the result in the register
of address wherein 2 is added to the address of OP1. The range of constants is 0 ~
FFFFFFFF.
(5) Flag
V58 Carry flag(CY) : Is set when carrying is generated from bit 31 as a result of addition.
V56 Half carry flag(HCY) : Is set when carrying is generated from bit 15 aiming at bit 16 as a result
of addition.
V54 Zero flag(Z) : Is set when add operation results in 0.
5-76
27. W+HP Addition of BCD 4-digit constant (FUN 327)
(1) Usable devices
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Deeming register content of OP1 as BCD code, adds it together with BCD constant and stores
the result in the register of OP3. The range of constants is 0 ~ 9999.
(5) Flag
V58 Carry flag(CY) : Is set when carrying is generated from bit 31 as a result of addition.
V56 Half carry flag(HCY) : Is set when carrying is generated from bit 15 aiming at bit 16 as a result
of addition.
V54 Zero flag(Z) : Is set when add operation results in 0.
V5E Data error flag(DER) : Is set if content of OP1 register is not in BCD format.
5-77
28. D+HP Addition of BCD 8-digit constant (FUN 328)
M
X Y K V T C L P D N S Constant
0W – 0EW 40W – 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
0W - 1EW 40W - 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Deeming register content of OP1 as BCD code, adds it together with BCD constant and stores
the result in the register of address wherein 2 is added to the address of OP1. The range of
constants is 0 ~ 99999999.
(5) Flag
V58 Carry flag(CY) : Is set when carrying is generated from bit 31 as a result of addition.
V56 Half carry flag(HCY) : Is set when carrying is generated from bit 15 aiming at bit 16 as a result
of addition.
V54 Zero flag(Z) : Is set when add operation results in 0.
V5E Data error flag(DER) : Is set if content of OP1 register is not in BCD format.
5-78
29. W-H Subtraction of hexadecimal 4-digit constant (FUN 330)
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Subtracts hexadecimal 4-digit constant from the register content of OP1 and stores the result in
OP3 register. The range of constants is 0 ~ FFFF.
(5) Flag
5-79
30. D-H Subtraction of hexadecimal 8-digit constant (FUN 331) PCk06
M
X Y K V T C L P D N S Constant
0W – 1CW 40W – 4CW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Subtracts hexadecimal 8-digit constant from the register content of OP1 and stores the result in
the register of address wherein 2 was added to the address of OP1. The range of constants is
0 ~ FFFFFFFF.
(5) Flag
5-80
31. W-HP Subtraction of BCD 4-digit constant (FUN 333)
(1) Usable devices
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Deeming register content of OP1 as BCD code, subtracts it together with BCD constant and
stores the result in the register of OP3. The range of constants is 0 ~ 9999.
(5) Flag
V57 Borrow flag(BO) : Is set when the digit lowering to bit 31 is generated as a result of the
subtraction.
V55 Half borrow flag(HBO) : Is set when the digit lowering is generated from bit 16 aiming at bit 15
as a result of the subtraction.
V54 Zero flag(Z) : Is set when subtract operation results in 0.
V5E Data error flag(DER) : Is set if content of OP1 register or OP2 register is not in BCD format.
5-81
32. D-HP Addition of BCD 8-digit constant (FUN 334)
M
X Y K V T C L P D N S Constant
0W – 0EW 40W – 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
0W - 1EW 40W - 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Deeming the register content of OP1 as BCD code, subtracts BCD constant and stores the
result in the register of address wherein 2 was added to the address of OP1. The range of
constants is 0 ~ 99999999.
(5) Flag
5-82
33. W*H Multiplication of hexadecimal 4-digit constant (FUN 336)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
○
OP3 ○ ○ ○ ○ ○ ○
0W -0EW
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 1EW
(3) Symbol
(4) Function
Multiplies the register content of OP1 by hexadecimal constant and stores the result in OP3.
The range of constants is 0 ~ FFFF.
(5) Flag
5-83
34. W*HP Multiplication of BCD 4-digit constant (FUN 339)
(1) Usable devices
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 0EW
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 1EW
(3) Symbol
(4) Function
Deeming the register content of OP1 as BCD code, multiplies BCD constant and stores the
result in the register of OP3. The range of constants is 0 ~ 9999.
(5) Flag
5-84
35. W/H Divide of hexadecimal 4-digit constant (FUN 342)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
○
OP3 ○ ○ ○ ○ ○ ○
0W -0EW
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 1EW
(3) Symbol
(4) Function
Divides the register content of OP1 by hexadecimal constant and stores the quotient in OP3
register and remainder in the register of address next to OP3. The range of constants is 0 ~
FFFF.
(5) Flag
5-85
36. W/HP Divide of BCD 4-digit constant (FUN 345)
(1) Usable devices
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 0EW
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
○
OP3 ○ ○ ○ ○ ○ ○
0W - 1EW
(3) Symbol
(4) Function
Deeming the register content of OP1 as BCD code, divides it by BCD constant and stores the
quotient in OP3 register and the remainder in the register of address next to OP3. The range
of constants is 0 ~ 9999.
(5) Flag
V54 Zero flag(Z) : Is set when divide operation results in 0.
V50 Error flag(ER) : Is set when the content of OP2 register is 0.
V5E Data error flag(DER) : Is set when the content of OP1 register or OP2 register is not in
BCD format.
5-86
5.4.3. Logical operation instructions
Instructions carrying out logical operations on contents of registers are classified as follows.
Logical product (AND)…….Carries out AND operation between data in registers and stores
the result into another register.
Logical sum (OR)…………..Carries out OR operation between data in registers and stores the
result into another register.
Inversion (NOT)…………....Inverts register data and stores the result into another register.
Exclusive logical sum ……..Carries out exclusive OR between register (XOR) data and stores
the result into another register.
5-87
37. WAND Word data logical product(AND) (FUN 187)
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Carries out AND operation between contents of OP1 and OP2 registers and stores the result
into OP3 register.
(5) Flag
5-88
38. DAND 32-bit data logical product(AND) (FUN 188)
M
X Y K V T C L P D N S 定数
0W – 0EW 40 W- 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S 定数
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Carries out AND operation between contents of OP1 and OP2 registers and stores the result
into OP3 register.
(5) Flag
5-89
39. WOR Word data logical sum(OR) (FUN 189)
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Carries out OR operation between contents of OP1 and OP2 registers and stores the result
into OP3register.
(5) Flag
5-90
40. DOR 32-bit data logical sum(OR) (FUN 190)
M
X Y K V T C L P D N S Constant
0W – 0EW 40 W- 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Carries out OR operation between contents of OP1 and OP2 registers and stores the result
into OP3register.
(5) Flag
5-91
41. WNOT Word data inversion (FUN 191)
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Inverts the contents of OP1 register ("1"bit to "0" and "0" bit to "1") and stores them into OP2
register.
(5) Flag
5-92
42. DNOT 32-bit data inversion (FUN 192)
M
X Y K V T C L P D N S Constant
0W – 0EW 40 W- 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Inverts the contents of OP1 register ("1"bit to "0" and "0" bit to "1") and stores them into OP2
register.
(5) Flag
5-93
43. WXOR Word data exclusive logical sum(XOR) (FUN 193)
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Carries out exclusive OR (XOR) between contents of OP1 and OP2 registers and stores the
result into OP3 register.
(5) Flag
5-94
44. DXOR 32-bit data exclusive logical sum(XOR) (FUN 194)
M
X Y K V T C L P D N S Constant
0W – 0EW 40 W- 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Carries out exclusive OR (XOR) between contents of OP1 and OP2 registers and stores the
result into OP3 register.
(5) Flag
5-95
45. WANDH Logical product (AND) of hexadecimal 4-digit constant (FUN 348)
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Determines logical product (AND) of the register content of OP1 by hexadecimal constant and
stores the result in OP3 register. The range of constants is 0 ~ FFFF.
(5) Flag
V54 Zero Flag (Z) : Turns ON when the calculated result is 0.
5-96
46. DANDH Logical product (AND) of hexadecimal 8-digit constant (FUN 349)
M
X Y K V T C L P D N S Constant
0W – 0CW 40 W- 4CW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
0W – 1CW 40W – 4CW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Determines logical product (AND) of the register content of OP1 by hexadecimal constant and
stores the result in the register of address wherein 2 was added to the address of OP1. The
range of constants is 0 ~ FFFFFFFF.
(5) Flag
5-97
47. WORH Logical sum (OR) of hexadecimal 4-digit constant (FUN 351)
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Determines logical sum (OR) of the register content of OP1 and hexadecimal constant and
stores the result in OP3 register. The range of constants is 0 ~ FFFF.
(5) Flag
5-98
48. DORH Logical sum (OR) of hexadecimal 8-digit constant (FUN 352)
M
X Y K V T C L P D N S Constant
0W – 0CW 40 W- 4CW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
0W – 1CW 40W – 4CW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Determines logical sum (OR) of the register content of OP1 and hexadecimal constant and
stores the result in the register of address wherein 2 was added to the address of OP1. The
range of constants is 0 ~ FFFFFFFF.
(5) Flag
5-99
49. WXORH Exclusive logical sum (XOR) of hexadecimal 4-digit constant (FUN 354)
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Determines exclusive logical sum (XOR) of the register content of OP1 and hexadecimal
constant and stores the result in OP3 register. The range of constants is 0 ~ FFFF.
(5) Flag
5-100
50. DXORH Exclusive logical sum (XOR) of hexadecimal 8-digit constant (FUN 355)
M
X Y K V T C L P D N S Constant
0W – 0CW 40 W- 4CW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
0W – 1CW 40W – 4CW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Determines exclusive logical sum (XOR) of the register content of OP1 and hexadecimal
constant and stores the result in the register of address wherein 2 was added to the address of
OP1. The range of constants is 0 ~ FFFFFFFF.
(5) Flag
5-101
5.4.4. Increment and decrement
5-102
51. WINC Word data binary increment (FUN 63)
M
X Y K V T C L P D N S Constant
0W - 0FW 40 W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Increments the content of OP2 register by l and compares the new value with the content of
OP1 register. Data is regarded as binary numbers.
(5) Flag
V53 Greater-than flag(>) : Is set if the content of OP1 register is greater than that of OP2
register.
V52 Equal flag (=) : Is set if the content of OP1 register equals that of OP2 register.
V51 Less-than flag(<) : Is set if the content of OP1 register is smaller than that of OP2
register.
5-103
52. WINCP 4-digit BCD increment (FUN 200)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Increments the content of OP2 register by 1 and compares the new value with the content of
OP1 register. Data is regarded as BCD numbers.
(5) Flag
V53 Greater-than flag(>) : Is set if the content of OP1 register is greater than that of OP2
register.
V52 Equal flag (=) : Is set if the content of OP1 register equals that of OP2 register.
V51 Less-than flag(<) : Is set if the content of OP1 register is smaller than that of OP2
register.
V5E Data error flag(DER) : Is set When content of OP2 register is not in BCD format.
5-104
53. WDEC Word data binary decrement (FUN 64)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W- 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Decrements content of OP1 register by 1. Data is regarded as binary numbers.
(5) Flag
5-105
54. WDECP 4-digit BCD decrement (FUN 203)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Decrements content of OP1 register by 1. Data is regarded as BCD numbers.
(5) Flag
5-106
5.4.5. Search
5-107
55. WSRH2 Word data search 2 (FUN 213) PCk06
M
X Y K V T C L P D N S Constant
0W – 1FW 40W – 4FW
○
PCk06 OP1 ○ ○
0W – 1EW
○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○
(3) Symbol
(4) Function
Searches the area, starting at OP2 address and containing the number of data specified by
OP3, for the data matching the content of OP1 register. If found, sets carry flag(CY) and
stores the location data(the Nth address with respect to OP2 address =1) into the word
address location following OP1.
Also stores the number of pieces of coincident data into address location next to the address
following the OP1 address. The maximum area can be searched is 256 pieces of data long.
(5) Flag
V50 Error flag(ER) : Is set when the data designated by OP1 not exists in the specified
range.
5-108
5.4.6. Data conversion
Used to convert data format and are classified into the following.
5-109
56. WBIN 4-digit BCD to 16-bit binary (FUN 3)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Converts BCD data stored in OP1 register into binary data and stores it into OP2register.
(5) Flag
5-110
57. DBIN 8-digit BCD to 32-bit binary (FUN 153)
M
X Y K V T C L P D N S Constant
0W ‒ 0EW 40W - 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W ‒ 1EW 40W ‒ 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Converts BCD data stored in OP1 register into binary data and stores it into OP2register.
(5) Flag
5-111
58. WBCD 16-bit binary to 4-bit BCD (FUN 4)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Converts binary data stored in OP1 register into BCD data and stores it into OP2 register.
The BCD data of four subordinate position digits is stored in the register of OP2
when exceeding it to 9999 as a result of conversion.
(5) Flag
5-112
59. DBCD 32-bit binary to 8-digit BCD (FUN 155)
M
X Y K V T C L P D N S 定数
0W ‒ 0EW 40W - 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S 定数
0W ‒ 1EW 40W ‒ 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Converts binary data stored in OP1 register into BCD data and stores it into OP2 register.
The BCD data of eight subordinate position digits is stored in the register of OP2
when exceeding it to 99999999 as a result of conversion.
(5) Flag
5-113
60. JBIN JIS code to binary (FUN 156)
(1) Usable devices
M
X Y K V T C L P D N S 定数
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○
M
X Y K V T C L P D N S 定数
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○
(3) Symbol
(4) Function
It stores it in the area where the JIS code data of the number of words (even number value)
shown from the address of OP1 by OP3 is considered to be a hexadecimal number, this is
converted into the binary number, and OP2 is assumed to be the first address.
The number of maximum conversion data (word) is 32.
When OP3 is specified by the odd number value, the even number value of the value +1
becomes the number of conversion data.
It becomes a no function treatment when OP3 is 0 and it doesn't become an error.
(5) Flag
V50 Error flag(ER) : Is set when the register number exceeds it.
1) JIS code of six words (12 characters) is converted from D0123 into the binary number when
X000 is ON, and it stores it in the area where D0160 is assumed to be the first address.
5-114
2) Four characters' worth of JIS code input from X040 to the input card of X05F when X101 is
ON is converted into the binary number, and it stores it in the area where D0100 is assumed
to be the first address.
5-115
61. BJIS Binary to JIS code (FUN 157)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○
(3) Symbol
(4) Function
Interprets the binary data stored, starting at OP1 address, as hexadecimal numeric value with
the number of characters specified by OP3, and converts the data into JIS codes and then
stores them into area starting at OP2 address.
The maximum number of convertable pieces of data is 32.
It becomes a no function treatment when OP3 is 0 and it doesn't become an error.
(5) Flag
V50 Error flag(ER) : Is set when the register number exceeds it.
5-116
2) The stored binary data is converted from the subordinate position byte of D0150 into JIS
code by four digits when X101 is ON, and it outputs it to the output card of Y440-Y45F.
5-117
62. DECO 4 to 16 decoder (FUN 50)
M
X Y K V T C L P D N S Constant
0W ‒ 0EW 40W - 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W ‒ 1EW 40W ‒ 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Decodes lower 4 bits of the content of OP1 register into 16-bit data and stores it in OP2
address location.
(5) Flag
No change
5-118
2) When X000 is ON, decodes lower 4 Points of input cards, X010-X01F, and distributes the
decoded data to output cards, Y440-Y44F.
5-119
63. ENCO 16 to 4 encoder (FUN 51)
M
X Y K V T C L P D N S Constant
0W ‒ 0EW 40W - 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W ‒ 1EW 40W ‒ 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Bit position (0-15) of ON(=1) is converted into the binary number among 16 bits of the content
of the register of OP1 and it stores it in four subordinate position bits of the register of OP2.
It gives priority to the subordinate position bit when there are two bits or more that have been
ON. Moreover, when there is no bit that has been turned on, V50 operation error flag (ER) is
ON, and the content of the register of OP2 is not changed.
(5) Flag
V50 Error flag(ER) : Is set if the 16-bit content of OP1 register is all OFF(filled with 0).
Or, is set when two or more bits have been ON.
5-120
1) When X100is ON, encodes the data of D0200(finds ON-bit) and stores the equivalent
value in the lower 4bits of D0210 lower byte.
5-121
2) When X000 is ON, encodes the data of D0220 and routes the result to lower 4points of
output cards, Y440-Y44F.
5-122
5.4.7. Comparison
5-123
64. WCP Word data comparison (FUN 12)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Compares contents of OP1 and OP2 registers and sets either of >, = or < flag, depending on
which one of the contents is larger.
(5) Flag
V53 Greater-than flag(>) : Is set if the content of OP1 register is greater than that of OP2
register.
V52 Equal flag (=) : Is set if the content of OP1 register equals that of OP2 register.
V51 Less-than flag(<) : Is set if the content of OP1 register is smaller than that of OP2
register.
5-124
65. DCP 32-bit data comparison (FUN 211)
M
X Y K V T C L P D N S Constant
0W – 0EW 40W - 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Compares contents of OP1 and OP2 registers and sets either of >, = or < flag, depending on
which one of the contents is larger.
(5) Flag
V53 Greater-than flag(>) : Is set if the content of OP1 register is greater than that of OP2
register.
V52 Equal flag (=) : Is set if the content of OP1 register equals that of OP2 register.
V51 Less-than flag(<) : Is set if the content of OP1 register is smaller than that of OP2
register.
5-125
5.4.8. Bit operation
Used to test ON or OFF state of bits and to set or reset a bit. The instructions are classified as
follows :
5-126
66. WSUM Word data ON-bit count (FUN 209)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Count all ON-bits ("1" level) in the content of OP1 register and stores the number data into
OP2.
(5) Flag
5-127
67. DSUM 32-bit data ON-bit count (FUN 210)
M
X Y K V T C L P D N S Constant
0W – 0EW 40W - 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Count all ON-bits ("1" level) in the content of OP1 register and stores the number data into
OP2.
(5) Flag
5-128
5.4.9. Shift
n bits shift……...Shifts data left or right any bit positions within the length of data.
Data shift……….Shifts addresses of data group forward or backward in unit of data set.
5-129
68. SFR Byte data 1 bit right shift (FUN 217)
M
X Y K V T C L P D N S Constant
0L - 0FH 40L - 4FH
PCk05 OP1 ○ ○
M
X Y K V T C L P D N S Constant
0L - 1FH 40L - 4FH
PCk06 OP1 ○ ○
(3) Symbol
(4) Function
If T input condition is met, shifts the content of OP1 register right 1 bit position (lower digit).
After the shift the content of D input enters the highest bit.
(5) Flag
No change
5-130
69. WSFR Word data 1 bit right shift (FUN 36)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○
(3) Symbol
(4) Function
If T input condition is met, shifts the content of OP1 register right 1 bit position (lower digit).
After the shift the content of D input enters the highest bit.
(5) Flag
No change
5-131
70. DSFR 32-bit data 1 bit right shift (FUN 218)
M
X Y K V T C L P D N S Constant
0W – 0EW 40W – 4EW
PCk05 OP1 ○ ○
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○
(3) Symbol
(4) Function
If T input condition is met, shifts the content of OP1 register right 1 bit position (lower digit).
After the shift the content of D input enters the highest bit.
(5) Flag
No change
5-132
71. WBSFR Word data n bits right shift (FUN 225)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Shifts the content for OP1 register right (lower digit) N bit positions with N being specified by
OP2. The upper unoccupied bit positions will be filled with "0s". When number of bits specified
by OP2 is larger than data length, the data bits are zeroed.
(5) Flag
No change
5-133
72. DBSFR 32-bit data n bits right shift (FUN 226)
M
X Y K V T C L P D N S Constant
0W – 0EW 40W - 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Shifts the content for OP1 register right (lower digit) N bit positions with N being specified by
OP2. The upper unoccupied bit positions will be filled with "0s".
The number of bits specified with OP2 is specified within the range of 1-32.
(5) Flag
No change
5-134
73. SFL Byte data 1 bit left shift (FUN 219)
M
X Y K V T C L P D N S Constant
0L - 0FH 40L - 4FH
PCk05 OP1 ○ ○
M
X Y K V T C L P D N S Constant
0L - 1FH 40L - 4FH
PCk06 OP1 ○ ○
(3) Symbol
(4) Function
If T input condition is met, shifts the content of OP1 register left 1 bit position (upper digit).
After the shift the content of D Input enters the lowest bit.
(5) Flag
No change
5-135
74. WSFL Word data 1 bit left shift (FUN 37)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○
(3) Symbol
(4) Function
If T input condition is met, shifts the content of OP1 register left 1 bit position (upper digit).
After the shift the content of D Input enters the lowest bit.
(5) Flag
No change
5-136
75. DSFL 32-bit data 1 bit left shift (FUN 220)
M
X Y K V T C L P D N S Constant
0W – 0EW 40W – 4EW
PCk05 OP1 ○ ○
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○
(3) Symbol
(4) Function
If T input condition is met, shifts the content of OP1 register left 1 bit position (upper digit).
After the shift the content of D Input enters the lowest bit.
(5) Flag
No change
5-137
76. WBSFL Word data n bits left shift (FUN 228)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Shift the content of OP1 register left (upper digit) N bit position with N being specified by OP2.
The lower unoccupied bit positions will be filled with "0s".
When number of bits specified by OP2 is larger than data length, the data bits are zeroed.
(5) Flag
No change
5-138
77. DBSFL 32-bit data n bits left shift (FUN 229)
M
X Y K V T C L P D N S Constant
0W – 0EW 40W - 4EW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Shift the content of OP1 register left (upper digit) N bit position with N being specified by OP2.
The lower unoccupied bit positions will be filled with "0s".
The number of bits specified with OP2 is specified within the range of 1-32.
(5) Flag
No change
5-139
78. SUP 4 bit data upper-digit direction shift (FUN 251) PCk06
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
OP1 is assumed to be the first address, and four bit data of the areas of the number of data
(word) specified with OP2 is shifted in the direction of the high rank (direction where the
address grows). At this time, the low rank data becomes “0".
(5) Flag
V50 Error flag (ER) : Is set when the shift area is outside of the data memory area.
5-140
79. UP2 Byte data upper-digit direction shift 2 (FUN 252) PCk06
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
OP1 is assumed to be the first address, and eight bit data of the areas of the number of data
(word) specified with OP2 is shifted in the direction of the high rank (direction where the
address grows). At this time, the low rank data becomes “0".
(5) Flag
V50 Error flag (ER) : Is set if the shifted data enters location for a device which is not
available for the current purpose or if the shift range exceeds the
limits.
5-141
80. WUP Word data upper-digit direction shift (FUN 253) PCk06
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
OP1 is assumed to be the first address, and 16 bit data of the areas of the number of data
(word) specified with OP2 is shifted in the direction of the high rank (direction where the
address grows). At this time, the low rank data becomes “0".
(5) Flag
V50 Error flag (ER) : Is set if the shifted data enters location for a device which is not
available for the current purpose or if the shift range exceeds the
limits.
5-142
81. DUP 32-bit data upper-digit direction shift (FUN 254) PCk06
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
OP1 is assumed to be the first address, and 32 bit data of the areas of the number of data
(word) specified with OP2 is shifted in the direction of the high rank (direction where the
address grows). At this time, the low rank data becomes “0".
(5) Flag
V50 Error flag (ER) : Is set if the shifted data enters location for a device which is not
available for the current purpose or if the shift range exceeds the
limits.
5-143
82. SDOWN 4 bit data lower-digit direction shift (FUN 255) PCk06
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
OP1 is assumed to be the first address, and four bit data of the areas of the number of data
(word) specified with OP2 is shifted in the direction of the subordinate position (direction
where the address becomes small). At this time, the most significant data becomes “0".
(5) Flag
V50 Error flag (ER) : Is set when the shift area is outside of the data memory area.
5-144
83. DOWN Byte data lower-digit direction shift (FUN 256) PCk06
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
OP1 is assumed to be the first address, and eight bit data of the areas of the number of data
(word) specified with OP2 is shifted in the direction of the subordinate position (direction
where the address becomes small). At this time, the most significant data becomes “0".
(5) Flag
V50 Error flag (ER) : Is set when the shifted data enters location for a device which is
outside of the data memory area.
5-145
84. WDOWN Word data lower-digit direction shift (FUN 257) PCk06
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
OP1 is assumed to be the first address, and 16 bit data of the areas of the number of data
(word) specified with OP2 is shifted in the direction of the subordinate position (direction
where the address becomes small). At this time, the most significant data becomes “0".
(5) Flag
V50 Error flag (ER) : Is set when the shifted data enters location for a device which is
outside of the data memory area.
5-146
85. DDOWN 32-bit data lower-digit direction shift (FUN 258) PCk06
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
OP1 is assumed to be the first address, and 32 bit data of the areas of the number of data
(word) specified with OP2 is shifted in the direction of the subordinate position (direction
where the address becomes small). At this time, the most significant data becomes “0".
(5) Flag
V50 Error flag (ER) : Is set when the shifted data enters location for a device which is
outside of the data memory area.
5-147
5.4.10. Rotate
Rotate without carry…..Rotates any number of bit-data right or left without a carry flag.
5-148
86. DRR 32-bit data right rotate without carry (FUN 244) PCk06
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Rotates content of OP1 register right (lower bit) by the number of bits specified by OP2. The
LSB is shifted into MSE position.
(5) Flag
No change
5-149
87. DRL 32-bit data left rotate without carry (FUN 247) PCk06
M
X Y K V T C L P D N S Constant
0W – 1EW 40W – 4EW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○
(3) Symbol
(4) Function
Rotates content of OP1 register left (upper bit) by the number of bits specified by OP2. The
MSB is shifted into LSB position.
(5) Flag
No change
5-150
5.4.11. Programmed branch
5-151
88. JMP JUMP (FUN 272) PCk06
Constant
X Y M K V T C L P D N S
L S EL
PCk06 OP1 ○
(3) Symbol
(4) Function
When the input condition is ON, executes a program bearing the label number specified by
OP1.
When the input condition is OFF, executes the program at the next step. Labels numbered
L0-L255 are available for this instruction.
(5) Flag
No change
5-152
89. CALL Subroutine call (FUN 273)
Constant
X Y M K V T C L P D N S
L S EL
PCk05 OP1 ○
Constant
X Y M K V T C L P D N S
L S EL
PCk06 OP1 ○
(3) Symbol
(4) Function
When the input condition is ON, executes a subroutine bearing the label number specified by
OP1 and will reenter the main program on the "RET" instruction, then go to a step following
the step where it branched. When the input condition is OFF, executes the next program step.
Labels numbered PCk05:S0-S63 and PCk06:S0-S127 are available.
(5) Flag
No change
Subroutine is written between the END and PEND instructions, starting with the LABEL
instruction and ending with the RET instruction.
Nesting is allowed, that is another subroutine call can be made in a current subroutine.
5-153
90. RET Return from subroutine (FUN 464)
(2) Symbol
(3) Function
Indicates the end of subroutine called by the CALL instruction.
This instruction, when executed forces the system to go to a step following the step where the
CALL instruction was executed to call the subroutine.
Note) The RET instruction is not omissible though the CRET instruction can be omitted.
(4) Flag
No change
5-154
91. CRET Return from subroutine (FUN 285)
(2) Symbol
(3) Function
Terminates the subroutine if the calculated result up to CRET is ON .
Note) The RET instruction is not omissible though the CRET instruction can be omitted.
(4) Flag
No change
5-155
92. FOR Start repetition (FUN 472)
X Y M K V T C L P D N S Constant
PCk05 OP1 ○
X Y M K V T C L P D N S Constant
PCk06 OP1 ○
(3) Symbol
(4) Function
Repeatedly executes the program between this and NEXT instruction for the number of times
defined by OP1. The number of repetitions definable from OP1 is 1-9999. Number 0 executes
the program between FOR and NEXT only once.
(5) Flag
No change
5-156
93. FORN Start repetition (indirect) (FUN 476)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Function
Repeats the program between this instruction and NEXT for the number of times defined by
the content(BCD) of OP1 register which will decrement the counts by 1 upon execution of this
instruction.
The program between FORN and NEXT is executed only once if OP1 register contains a 0.
(5) Flag
No change
The FORN instruction cannot include condition (contact). When the program has run for the
number specified, D1000 will contain 0.
The FORN is always paired with NEXT instruction when used.
5-157
94. NEXT End of repetition (FUN 480)
(2) Symbol
(3) Function
Runs the program between FOR or FORN instruction and this instruction for the number of
times defined by the FOR or FORN instruction.
(4) Flag
No change
5-158
5.4.12. Master control
5-159
95. MC Master control set (FUN 440)
X Y M K V T C L P D N S Constant
PCk05 OP1 ○
X Y M K V T C L P D N S Constant
PCk06 OP1 ○
(3) Symbol
(4) Function
This instruction indicates the start of the master control whose number is defined by OP1. The
range of the master control begins with this instruction and ends with MCR instruction starting
the same master control number with this instruction. When the input condition is ON, normal
program operation is performed within the area of master control. If the input condition is OFF,
however, all output instructions within the area are made off, and output type application
instructions cannot be executed. Master control numbers selectable from OP1 are 0 to 6.It
sequentially uses it from a small number at two or more use.
(5) Flag
No change
(When M017 is OFF, (L0 = OFF and W0VEare not executed regardless of X0 and X1
statuses.)
MC instruction is always paired with MCR instruction when used, MCR instruction cannot
include a condition (contact).
5-160
96. MCR Master control reset (FUN 444)
X Y M K V T C L P D N S Constant
PCk05 OP1 ○
X Y M K V T C L P D N S Constant
PCk06 OP1 ○
(3) Symbol
(4) Function
This instruction indicates the end of master control whose number is defined by OP1.
The range of the master control begins with MC instruction and ends with this MCR instruction.
Both instruction should carry the same master control number. For details, refer to MC
instruction described above.
(5) Flag
No change
5-161
5.4.13. Sequential interrupt
5-162
97. DI Interrupt inhibit (FUN 276)
(2) Symbol
(3) Function
Inhibits interrupt programs (external interrupt) until EI instruction is executed.
(4) Flag
No change
5-163
98. EI Interrupt enable (FUN 277)
(2) Symbol
(3) Function
Releases interrupt inhibit status kept after power-up, reset-start or DI instruction and enables
execution of interrupt program.
(4) Flag
No change
Once executed, the DI instruction remains effective until the DI instruction is issued or an
interrupt is generated; no need to issue DI instruction every scan.
5-164
99. RETI Return from interrupt routine (FUN 468)
(2) Symbol
(3) Function
This instruction indicates the end of interrupt program.
The Program that has been interrupted by the interrupt input can start again at the next step.
(4) Flag
5-165
5.4.14. Label
This instruction is used to define a program range and to indicate a jump address.
5-166
100.START Main program start (FUN 448)
(2) Symbol
(3) Function
Indicates the start of main sequential program.
(4) Flag
No change
START, END, LABEL, RET, RETI and PEND instructions cannot contain condition (contact).
START and LABEL instruction are non-operative instructions i.e. they do not perform effective
operation even when executed.
5-167
101.END Main program end (FUN 452)
(2) Symbol
(3) Function
Indicates the end of main sequential Program.
After completion of this instruction, START instruction is used to run the program (restart of
the main sequence program from the beginning).
(4) Flag
No change
5-168
102.PEND End of program (FUN 456)
(2) Symbol
(3) Function
Indicates the end of sequential program including subroutines and interrupt programs.
(4) Flag
No change
5-169
103.LABEL Label (FUN 460)
(2) Symbol
(3) Function
Indicates the jump destination upon issuing of JMP instruction, CALL instruction or interrupt.
5-170
5.4.15. Special module data transfer
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Explanation
The module corresponding to the special module data reading is current CPU port2 only.
The SPR instruction is read and executed networking as an instruction. The data block is read
from the slave device on the same network. The function parameter is written in a consecutive
data register of two words beforehand by using the WMOV instruction twice. To use the SPR
instruction, the steps necessary is shown in the following.
・Step 1: Master PLC port2(F2 hex) is written in a high byte of the data register of the first
word and slave station number (0-90 BCD) is written in the subordinate position
byte.
・Step 2: The forwarded number of bytes is written in the second word of the data register in
BCD.
・Step 3: The data register in step 1 is executed in the first operand of the SPR instruction,
and reading beginning memory on the slave is executed in the second operand
and the memory is executed specifying it at the copy destination of the data read
from the slave to the third operand.
5-171
In the following example, M000 turns on port2, and it accesses CPU port2 by the SPR
instruction when V60 (Refer to a special relay) shown while using it is off. Ten bytes' worth of
data (D0400-D0404) consecutive from slave CPU of child station number 5 is read, and it
copies it to data register position (D04C0-D04C4) of CPU via port2 of master CPU.
5-172
105. SPW Special module data write (FUN 306)
M
X Y K V T C L P D N S Constant
0W - 0FW 40W - 4FW
PCk05 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○ ○
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP2 ○ ○ ○ ○ ○ ○ ○ ○ ○
OP3 ○ ○ ○ ○ ○ ○ ○ ○ ○
(3) Symbol
(4) Explanation
The module corresponding to the special module data writeing is current CPU port2 only.
The SPW instruction is networking written and it executes it as an instruction. The data block
is written in the slave device on the same network. The function parameter is written in a
consecutive data register of two words beforehand by using the WMOV instruction twice. To
use the SPW instruction, the steps necessary is shown in the following.
・Step 1: Master PLC port2(F2 hex) is written in a high byte of the data register of the first
word and slave station number (0-90 BCD) is written in the subordinate position
byte.
・Step 2: The forwarded number of bytes is written in the second word of the data register in
BCD.
・Step 3: The data register in step 1 is executed in the first operand of the SPW instruction,
and reading beginning memory on the master is executed in the second operand
and the memory ..the third operand.. is executed specifying it at the destination of
writing the slave.
5-173
In the following example, M001 turns on port2, and it accesses CPU port2 by the SPW
instruction when V60 (Refer to a special relay) shown while using it is off. Ten bytes' worth of
data (D04C0-D04C4) consecutive from CPU on the master is read, and it copies it to data
register position (D0400-D0404) of slave CPU of station number 5 via master CPU port2.
5-174
5.4.16. Other application instruction
(2) Symbol
(3) Function
Halts the running sequential program. All the output relays are turned off.
To return from the state of STOP, the condition of abnormality is released. After that, it
changes to the RUN mode by using mode SW or PCwin-PCk of CPU.
2.It makes it to the RUN mode by reset/starting CPU→CPU of the menu in Pcwin-PCk.
(4) Flag
5-175
107.WDR Scan timer reset (FUN 46)
(2) Symbol
(3) Function
Resets the scan time monitor timer.
(4) Flag
No change
The setup value for the scan time monitor timer can be set by parameter (refer to Chapter 3
"PARAMETER"). When the scan time is longer than the time set by the scan time monitor
timer due to the program construction, the CPU will output an error. When you don't want it to
be an error, either change the scan time setup value parameter or reset the current value of
the scan time monitor timer.
5-176
5.4.17. Clock / Calendar instruction
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○
OP2 ○
OP3 ○
(3) Symbol
(4) Function
The setting at the date of CPU is executed.
OP1: System call number and 7F06h fixation.
OP2: Beginning house number of set data address of date.
It specifies it by the relative address of the data register.
(Two data address numbers are multiplied and + does offset value 2000h. )
(D0000-D0C7E)The done relative address for is (2000h-39FCh).
(D1000-D1FFE)The done relative address for is (4000h-5FFCh).
OP3:0 fixation.
(5) Flag
No change
The data of two words that starts from D0000 when M000 is turned on is assumed to be date data
and the date of CPU is set.
The data of two words that starts from D0000 is the order (day and day of the week)(year and
month). 0-6 corresponds to Sunday - Saturday on a day of the week.
Only data in each setting range of BCD becomes effective as for date set data, and other codes
are disregarded. (00-99) becomes the year, (01-12) becomes the month, (01-31) becomes the
day, and a day of the week becomes a range where (00-06) can be set.
CPU date is set on Monday, June 25,'07 in the place where it is D0000, and D0001=2501,0706.
5-177
109.SYS Time instruction (FUN 300) PCk06
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○
OP2 ○
OP3 ○
(3) Symbol
(5) Function
The setting of the time of CPU is executed.
OP1: System call number and 7F07h fixation.
OP2: Beginning house number of set data address of date.
It specifies it by the relative address of the data register.
(Two data address numbers are multiplied and + does offset value 2000h. )
(D0000-D0C7E)The done relative address for is (2000h-39FCh).
(D1000-D1FFE)The done relative address for is (4000h-5FFCh).
OP3:0 fixation.
(7) Flag
No change
The data of two words that starts from D0002 when M000 is turned on is assumed to be time data
and the time of CPU is set.
The data of two words that starts from D0002 is the order (minute and second) (unused and
time).
Only data in each setting range of BCD becomes effective as for time set data, and other codes
are disregarded. (00-59) becomes the second, (00-59) becomes the minute, and time becomes a
range where (00-23) can be set.
CPU is confirmed by reading the special register, S004 (second), S005 (minute), and S006 (time)
at time now.
5-178
5.4.18. MODBUS RTU instruction
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○
OP2 ○
OP3 ○
(3) Symbol
(4) Function
Settled data is read from the slave device connected with CPU port2 at the MODBUS
network master, and the data is written in the memory of CPU.
The MODBUS network reading is executed by describing the SYS function three instructions
continuously.
In OP1, order is fixation in this order by the system call number, 7F10h, 7F11h, 7F12h, and
fixation.
(4)-1.OP1=7F10h
OP2= A high byte is a data size specification type.
00h Data addressing(Specify it by the relative address. )
01h Constant specification
A low byte is MODBUS data form + port number. (2 fixation)
00h 584/984 MODBUS data form modes
80h 484 MODBUS data form modes
Therefore, the data that can be specified with OP2 becomes only the following
four kinds.
5-179
OP3= A high byte is MODBUS function code.
01 Read a group of coils
02 Read a group of inputs
03 Read holding registers
04 Read input registers
07 Read Exception status
A low byte is specify a slave station address. (0-247)
(example) 0302h= The holding register of the slave station address 2 is read.
(4)-2. OP1=7F11h
OP2= Start master memory address
Specifies the starting memory address in the master where the data will be
placed.
Master Memory Address Ranges
Relative address
Operand Data Type PCk06 Range
(OP2 setting)
Inputs X000~X1FF 1000~11FF
Outputs Y400~Y5FF 1400~15FF
Internal Relays M000~M1FF 1800~19FF
Keep Relays K000~K1FF 0200~03FF
Timer Bits T000~T0FF 0600~06FF
Counter Bits C100~C17F 0700~077F
Link Relays input L000~L3FF 0800~0BFF
Link Relays output L400~L7FF 0C00~0FFF
D0000~D0C7F 2000~39FE
Data Registers
D1000~D1FFF 4000~5FFE
5-180
(4)-3. OP1=7F12h
OP2= Number of elements
Specifies how many coils, input, holding registers or input register will be
read.
Number of Elements
Operand data PCk05/PCk06 Number of
Function Code elements
Type Range (OP2 setting)
. The specified content of the
Data D0000~D0C7F 2000~39FE
addressing
data register is assumed to
D1000~D1FFF 4000~5FFE
be data size specification
01-Read Coil 1~2000 0001~07D0
02-Read Input Status 1~2000 0001~07D0
Constant
specification
03-Read Holding Register 1~125 0001~007D
04-Read Input Register 1~125 0001~007D
07-Read Exception Status N/a 0000
(5) Flag
No change
5-181
Example of program
Six holding registers that start from address 464601 of slave address number 2 are done and the
MODBUS reading is done. 96 bits are written in the master side memory that starts from M140.
The error response data is stored in D1F00.
5-182
111.SYS MODBUS Write to Network (FUN 300) PCk06
M
X Y K V T C L P D N S Constant
0W - 1FW 40W - 4FW
PCk06 OP1 ○
OP2 ○
OP3 ○
(3) Symbol
(4) Function
Data to which CPU memory is settled is read at the MODBUS network master, and it writes it
in the MODBUS memory address in the slave device on the network connected with CPU
port2.
The MODBUS network writing is executed by describing the SYS function three instructions
continuously.
In OP1, order is fixation in this order by the system call number, 7F20h, 7F21h, 7F22h, and
fixation.
(4)-1.OP1=7F20h
OP2= A high byte is a data size specification type.
00h Data addressing(Specify it by the relative address. )
01h Constant specification
A low byte is MODBUS data form + port number. (2 fixation)
00h 584/984 MODBUS data form modes
80h 484 MODBUS data form modes
Therefore, the data that can be specified with OP2 becomes only the following
four kinds.
5-183
OP3= A high byte is MODBUS function code.(decimal)
05 Force single coil
06 Preset single register
15 Force multiple coils
16 Force multiple registers
A low byte is specify a slave station address. (0-247)
(example)1002h= The preset value is set to two or more registers of the slave
station address 2.
Function code 16(decimal) of a high byte converts into the
hexadecimal and becomes 10h.
The slave station address of low byte is converted into the
hexadecimal and it specifies it.
(4)-2. OP1=7F21h
OP2= Start master memory address
Specifies the starting address of the data in the master that is to written to
the slave.
Master Memory Address Ranges
Relative address
Operand Data Type PCk06 Range
(OP2 setting)
Inputs X000~X1FF 1000~11FF
Outputs Y400~Y5FF 1400~15FF
Internal Relays M000~M1FF 1800~19FF
Keep Relays K000~K1FF 0200~03FF
Timer Bits T000~T0FF 0600~06FF
Counter Bits C100~C17F 0700~077F
Link Relays input L000~L3FF 0800~0BFF
Link Relays output L400~L7FF 0C00~0FFF
D0000~D0C7F 2000~39FE
Data Registers
D1000~D1FFF 4000~5FFE
5-184
(4)-3. OP1=7F22h
OP2= Number of elements
Specifies how many consecutive coils or registers will be written to.
This field is only active when either function code 15 or 16 is selected.
Number of Elements
Operand data PCk05/PCk06 Number of
Function Code elements
Type Range (OP2 setting)
The specified content of the
Data D0000~D0C7F 2000~39FE
addressing
data register is assumed to be
D1000~D1FFF 4000~5FFE
data size specification
05-Force Single Coil N/a 1
Constant 06-Preset Single Register N/a 1
specification 15-Force Multiple Coils 1~2000 0001~07D0
16-Preset Multiple Registers 1~125 0001~007D
(5) Flag
No change
5-185
Example of program
The master side memory that starts from K000 is read by 112 bits, and MODBUS is written in 7
registers that start from address 464101 of slave station address 2. The error response data is
stored in D1F10.
5-186
6. Appendix Difference with DL05/06
Note that the ladder program to PCk05/06 cannot be converted when you use the instruction word
assumed to be not corresponding in the following table when the device that uses DirectLOGIC05/06 is
replaced with PCk05/06.
6-1
6.3. Comparative Boolean Instructions
6-2
6.5. Timer, Counter and Shift Register
DL Instruction DL05 DL06 PCk05/PCk06
TMR TMR TMR
TMRF TMRF TMRH
TMRA TMRA TMRS
Timer, Counter
TMRAF TMRAF TMRSH
and Shift
CNT CNT CNT
Register
SGCNT SGCNT Not correspond
UDC UDC CNTH
SR SR SFR SFL WSFR WSFL DSFR DSFL
6-3
6.7. Logical Instructions
DL Instruction DL05 DL06 PCk05/PCk06
AND AND WAND
ANDD ANDD DAND
ANDC ANDC WANDH DANDH
ANDF Not correspond
ANDS Not correspond
OR OR WOR
ORD ORD DOR
ORC ORC WORH DORH
ORF Not correspond
ORS Not correspond
Logical XOR XOR WXOR
Instructions XORD XORD DXOR
XORC XORC WXORH DXORH
XORF Not correspond
XORS Not correspond
CMP CMP WCP
CMPD CMPD DCP
CMPR CMPR Not correspond
CMPF Not correspond
RCMPR Not correspond It doesn't do for the floating point.
RCMPRC Not correspond It doesn't do for the floating point.
CMPS Not correspond
6-4
6.8. Math Instructions
DL Instruction DL05 DL06 PCk05/PCk06
ADD ADD W+P
ADDD ADDD D+P
ADDC ADDC W+HP D+HP
SUB SUB W-P
SUBD SUBD D-P
SUBC SUBC W-HP D-HP
MUL MUL W*P
MULS MULS W*HP
MULD MULD D*P
DIV DIV W/P
DIVS DIVS W/HP
DIVD DIVD D/P
INC INC WINCP
DEC DEC WDECP
INCB INCB WINC
DECB DECB WDEC
ADDB ADDB W+
BADDS BADDS W+H
ADDBD D+
BADDC D+H
SUBB SUBB W-
BSUBS BSUBS W-H
SUBBD D-
BSUBC D-H
Math MULB MULB W*
Instructions BMULS BMULS W*H
DIVB DIVB W/
BDIVS BDIVS W/H
ADDR Not correspond It doesn't do for the floating point.
RADDC Not correspond It doesn't do for the floating point.
SUBR Not correspond It doesn't do for the floating point.
RSUBC Not correspond It doesn't do for the floating point.
MULR Not correspond It doesn't do for the floating point.
RMULC Not correspond It doesn't do for the floating point.
DIVR Not correspond It doesn't do for the floating point.
RDIVC Not correspond It doesn't do for the floating point.
ADDF Not correspond Arbitrary bit
SUBF Not correspond Arbitrary bit
MULF Not correspond Arbitrary bit
DIVF Not correspond Arbitrary bit
ADDS Not correspond Stack operation
SUBS Not correspond Stack operation
MULS Not correspond Stack operation
DIVS Not correspond Stack operation
ADDBS Not correspond Stack operation
SUBBS Not correspond Stack operation
MULBS Not correspond Stack operation
DIVBS Not correspond Stack operation
6-5
6.9. Transcendental Functions
DL Instruction DL05 DL06 PCk05/PCk06
SQRTR Not correspond It doesn't do for the floating point
SINR Not correspond It doesn't do for the floating point
COSR Not correspond It doesn't do for the floating point
Transcendental
Functions TANR Not correspond It doesn't do for the floating point
ASINR Not correspond It doesn't do for the floating point
ACOSR Not correspond It doesn't do for the floating point
ATANR Not correspond It doesn't do for the floating point
6-6
6.12. Table Instructions
DL Instruction DL05 DL06 PCk05/PCk06
MOV MOV WBMOV
MOVMC MOVMC Not correspond
LDLBL LDLBL Not correspond
FILL WFIL
FIND WSRH2
FDGT Not correspond
FINDB Not correspond
TTD Not correspond
RFB Not correspond
Table STT Not correspond
Instructions RFT Not correspond
ATT Not correspond
TSHFL SUP UP2 WUP DUP
TSHFR SDOWN DOWN WDOWN DDOWN
ANDMOV Not correspond
ORMOV Not correspond
XORMOV Not correspond
SWAP WBXCH
SETBIT Not correspond
RSTBIT Not correspond
6-7
6.15. Program Control Instructions
DL Instruction DL05 DL06 PCk05/PCk06
GOTO JMP
LBL LBL LABEL
FOR FOR FOR FORN
NEXT NEXT NEXT
Program GTS GTS CALL
Control
Instructions SBR SBR LABEL
RTC RTC CRET
RT RT RET
MLS MLS MC
MLR MLR MCR
6-8
6.20. ASCII Instructions
DL Instruction DL05 DL06 PCk05/PCk06
AIN Not correspond
AFIND Not correspond
AEX Not correspond
ASCII CMPV Not correspond
Instructions SWAPB Not correspond
VPRINT Not correspond
PRINTV Not correspond
ACRB Not correspond
6-9
Index of instruction words
OR STR 5-6
OR, OR NOT 5-4
OUT 5-7
SDOWN 4 bit data lower-digit direction shift (FUN 255) PCk06 5-144
SFL Byte data 1 bit left shift (FUN 219) 5-135
SFR Byte data 1 bit right shift (FUN 217) 5-130
SPR Special module byte-data read (FUN 304) 5-171
SPW Special module byte-data write (FUN 306) 5-173
START Main program start (FUN 448) 5-167
STOP Program stop (FUN 287) 5-175
STR, STR NOT 5-2
SUP 4 bit data upper-digit direction shift (FUN 251) PCk06 5-140
SYS Date setting (FUN 300) PCk06 5-177
SYS Time setting (FUN 300) PCk06 5-178
SYS MODBUS Network read (FUN 300) PCk06 5-179
SYS MODBUS Network write (FUN 300) PCk06 5-183
UP2 Byte data upper-digit direction shift 2 (FUN 252) PCk06 5-319
* The specification and other given in this manual are subject to change due to improvement without prior notice.
* Any product applicable to the strategic goods (or the services) stipulated in the Foreign Exchange and Foreign Trade Control Act is
subject to export license of the Japanese Government, where exported to overseas.