3

cONTENTS
KEC 302: Digital System Design
UNIT-1: LOGIC SIMPLIFICATION &COMBINATIONAL LOGIC DESIGN
(1-1 B to 1-32 B)
Binary codes, code conversion, review of Boolean algebra and
Demorgans theorem, SOP & POS forms, Canonical forms,
Karnaugh maps up to 6 variables, tabulation method.

UNIT-2 MSI DEVICES (2-1 B to 2-31 B)

MSI devices like comparators, multiplexers, encoder, decoder, driver
& multiplexed display, half and full adders, subtractors, serial and
parallel adders, BCD adder, barrel shifter and ALU.

UNIT-3:SEQUENTIAL LOGIC DESIGN (3-1 B to 3-40 B)

Sequential logic design: Building blocks like S-R, JK and Master-
Slave JK FF, edge triggered FF, state
diagram, state counters,
design of sequential circuits, ripple and synchronous reduction,
shift registers, finite state machines,
design of synchronous FSM,
algorithmic state machines charts. Designing synchronous circuits
like pulse train generator, pseudo random binary sequence generator,
clock generation.

UNIT-4 LOGIC
TIL NAND gate,
FAMILIES&MEMORIES (4-1 B to 4-32 B)
specifications, noise margin,
fan-in, fan-out, tristate TTL, ECL, CMOS propagation delay,
families and their
interfacing, memory elements, concept of
programmable logic
devices like FPGA, logic
devices.
implementation using programmable
UNIT-5 D/A AND A/D CONVERTER (5-1 B to 5-21 B)
Digital-to-Analog converters (DAC): Weighted resistor, R-2R ladder,
resistor string etc.
analog-to-digital converters (ADC): single slope,
dual slope, successive
circuits: Basic concept,
approximation, flash etc. Switched capacitor
practical configurations, application in
amplifier, integrator, ADC etc.

SHORT QUESTIONS (SQ-1 B to SQ-17 B)

SOLVED PAPERS (2014-15 TO 2021-22) (SP-1 B to SP-64 B)

 1
UNIT
Logic Simplification
and Combinational
Logic Design

CONTENTS
Part-1 :
Binary Codes.. *****asse**ee*rn****************** 1-2Bto 1-3B

Part-2 Code Conversion..

***************** 3 B to 1-12B
..
Part-3:Review of Boolean Algebra and...1-12B to 1-15B
Demorgan's Theorem: SOP and
POS Porms, Canonical Forms

Part-4 Karnaugh Maps Upto 6 ************ 1-15B to 1-22B

Variables

Part-s Tabulation (Quine McCluskey) . . . . 1-22B to l-31B

Method

1-1B(EC-Sem-3)
1-2B (EC-Sem-3)
Logic Simplification & Combinational Logic Design

PART1
Binary Code.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que1.1. Describe the binary codes. Show the classification of

binary codes in tabular format.

Answer
Code is the representation of group of symbols, words, or letters. As the
digital data is used as group of binary numbers, so, we call it as the
binary codes.
2. These binary codes are used for the designing and
analysis of digital
circuit, computer applications, in digital communication. The codes are
classified into certain following categories
Weighted codes
i Non-weighted codes
ii. Reflective codes
iv. Sequential codes
V. Alphanumeric codes
vi. Error detecting and correcting codes.
3 Since, all these codes use only 0 and 1, so it is easier to implement. The
binary codes can also be used for representing the numbers as well as
the alphanumeric letters.
The classification of codes can be composed in tabular form which is as
follows
Codes

Weighted Reflective Alphanumeric

codes codes codes
ASCI Error detecting
Non-weighted2421
EBCDIC
Binary BCD codes
Excess-3 &Hamming
correctingcodes
8421 Excess-3 Sequential codes
Paritty
2421 °Gray 8421
Excess-3
Fig. 1.1.1.
Digital System Design 1-3 B (EC-Sem-3)

5.
Weighted binary codes
the number to represent.
are those which obey the positional weight for

6 In non-weighted codes, the positional weights are not assigned.

In reflective code, the reflectivity is desirable. For example, in 9's
complement subtraction, ie., code for 9 is the complement for 0, code for
8is complement of 1. 7 for 2, 6 for 3 and 5 for 4.
8. In sequential code, each succeeding code is one binary number greater
than the preceding code.
9. The alphanumeric codes are designed to represent numbers as well as
characters.
10. The error detecting and correcting codes are used to detect and correct
the error like 0 may change to 1 or vice-versa by using some special
codes which possess the capacity to detect and correct the error.

Que 12. Represent the decimal number 6 in (i) excess-3 code, ()

BCD code, ii) Gray code, (iv) 8421 code and (v) 2421 codes.

Answer
Excess-3 code
6 (in BCD) = 0110
+3 0011

1001
ii. BCD code: (6)10 = 0110 (in BCD)

ii. Gray code (6) = 0110

0 1 0 1
Gray code = 0101

iv. 8421 code: (6), = 0110

4-2,-1 1010
v. 2421 code:
624.21 1100

PART 2
Code Conversion.

Questions-Answers
Long Answer Type and Medium Answer Type Questions
1-4B (EC-Sem-3) Logic Simplification & Combinational Logic Design

Que 1.3. Design Binary to BCD code converter.

Answer

Truth table:

Binary code BCD code

DCB A
B B,B,
0
1 0 0
0 0 0
0 1 0 0

0 0 0

0 0
1 0
1 0 0
1 0 0 0 0
1 0
1 0

K-map simplification:

Expression for B Expression for B,

p 00 01 11 10 DC 0 01 10
2
o 00
5 6 6
01 01

1112 13 1514 112 31514

1|
11 10
10
B, = A DCB + DB
=
Digital System Design 1-5B (EC-Sem-3)

Expression for B, Expression for B

00 01 11 10 BA 00 01 11 10
Oo/o
1 3 2 1 3

11 12 13 12 13 14
15 4
11 |15

1 10 10
10

DC +CB B, = DCB
B, =

Expression for B,
BA 00 01 11 10
DC
00
b

1112 13 15 14

9 11 10
10
B, =
DC + DB

Logicdiagram:
Binary code

BCD code
B, LSD

D
B
D
U B, MSD

Fig. 1.3.1. Logic circuit for binary to BCD converter

1-6B (EC-Sem-3) Logic Simplification & Combinational Logic Design

Que1.4. Design a combinational circuit that converts a BCD

code to excess-3 code.

AKTU 2016-17, Marks 15
Answer
Truth table:
Input BCD Output excess-3 code

ABCD 0
0 0
0
0

1
The maps in Fig. 14.1, are plotted to obtain simplified boolean functions
for the outputs.
2. A two-level logic diagram of each output may be obtained directly from
the boolean expressions derived from the maps.
For z For y
CD 00 01 11 10 CD 11 10
AB AB 00 01
001 0o
01 o1 1 6
11
11
10
z =D y CD + CD
For x For w
CD
CD 00 01 11 10 00 01 11 10
AB AB
00 00
o1 01

111
10
1o W = A+ BC + BD
x = BC + BD + BD

Fig. 14.1. Mups for BCD to excess-3 code converter.

Digital System Design 1-7B (EC-Sem-3)

3. The expressions derived from the maps are:

D
y = CD+ CD =CD + (C+ D)
x
=BC + BD BCD BC + D)+ BCD
B(C+ D) + B (C + D)
w =A + BC + BD =A +B(C + D)
The logic diagram that implements these expressions is shown in
Fig 1.4.2.

C D
B-

Fig. 1.4.2.

Que 15. 1 Design excess-3 code to BCD code converter.

Answer

Truth table:
Excess-3code BCD code

E EE E B B B B
1 0 0 0)

0
0 0
0
0

The unused Excess-3 codes are 0000,0001, 0010, 1101, 1110 and 1111.
So place X (Don't Care condition) for the corresponding codes.
1-8B (EC-Sem-3) Logie Simplification & Combinational Logic Design

K-map simplification:
Expression for B Expression for B,

01 11 10 E,o 0o01 0
3 3
00
01
11 12 13 15

B Eg B, E, Eg+ E, Eg =E, E
Expression for B, Expression for B
E o0 01 11 10
o 00
01 11 10
E20
JO
3
Eo
O1

1112 13 11 12 13 15 14

1110
10
B E, E +E, E, Eg . E, E, Eo B E E+E,E, Eo
Logicdiagram:

-Bo
B,

Fig. 1.5.1.
Digital System Design 1-9B (EC-Sem-3)

Que 1.6. Design Binary code to Gray code converter.

AKTU 2018-19, Marks 07

Answer
Truth table:

Binary code Gray code

DC B A
GG G Go
0 0 0 0 0 0
0 0
0 0

0
0

K-map simplification :

Expression for G Expression for G,

BA 00 01 11 10 BA 00 01 11
DC 10
2 0
00

1112 3 15 14

10 |11 10

G =BA + BA = B A
G = CB+CB =C ® B
1-10 B (EC-Sem-3) Logic Simplification & Combinational Logic Design

Expression for G Expression for G

BA
DC 00 01 11 10 D 00 01
0 1 3 2 DC 11 10
00
6
01

13
1112 14
112 13 15 14

11 10 11 10

G2 DC + DC =C ®D Gg = D
We get the simplified boolean expression for the code converter of Binary
to Gray code.
G = BA+ BA B9 A

G, CB+ CB = C B

G = DC+ DC =COD
G, = D

Logic diagram:
D C B
ABinarycode

G3 G2 G Go= Gray code

Fig. 1.6.1,

9ue 1.7. Design a combinational cireuit that eonverts a 3-bit

Gray code to a 3-bit binary number. Implement the circuit with
i. Exclusive-OR gate
ii. NAND gate only.
 1-11 B (EC-Sem-3)
Digital System Design

Answer
Gray code to binary code converter :
Gray code Binary code

G G, G C
0 0
0 0
0 0
0 0
0
0

K-map simplification
ForrA or

G 00 01 11 10 00 01 11 10

A GG, G,+G,G, G +G,G, G,+ G,G,G B GG, +G,G

A G29 G, ® Go B G,9 G,
For C
GGo
G2\ 00 01 11 10

C i2

i.
Logicdiagram:
Using XOR gates :

G, G,9 Go A

9G = B

C-G
Fig 1.7.1.
1-12 B (EC-Sem-3) Logic Simplification & Combinational Logic Design

ii. Using NAND gates:

GG,GG,G,G, G,6,GG,6,G
A=G,G.G,+ G,G,G,+GG,G,+G,GG,

Go
,
G,

G,G). GG,) =G,G,G,G, =

B

-C - G2

Fig. 1.7.2.

PART-33
Review of Boolean Algebra and Demorgan's Theorem: SOP and
POS Forms, Canonical Forms.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 1.8. State De Morgan's theorem.

Answer 1
First De Morgan theorem : It states, complement of two or more
variables and then AND operation on these is equivalent to NOR

operation on these variables. (NOR means complement of two or more

variables OR).
A, + A, = A A
Second De Morgan theorem: It states that complement of two or
is equivalent to NAND
more variables and then OR operation on these a

operation on these variables (NAND means complement of two or more

variables AND).

A, A, A, = A,+ A, + A
 Digital System Design 1-13 B (EC-Sem-3)

Que 1.9. Simplify the following expression as much as possible:

F(u, x, y, z) = y~ + uwrz + üxy~ + wy~

and implement your result using universal gates only.

Answer
Fw, x, y, 2) = yz +wxz + w xyz + wyz

= yz +uwyz + wxz + wxyz

=2 (y +wy) + wz (x +xy)
=
(y+w) + wz (x+y) :A+ AB- A +B]
=
y2 +wz + Wrz +wyz
= yz + wyz + wz +wxz

z (y+ uy) + z
=
(w+ wx)
= (y + ) + (w + )

= (y + k+w + )
= z(y+1+7)
I 1+A =
1]
= 7 +1) A
: 1+ =1

Using NAND gate Using NOR gate

a)
Fig. 1.9.1. (b)

ue 1.10. Simplify thefollowing boolean equation

YA, B, C, D) = ABC + ABCD

Answer
Given, YA, B, C, D) = ABCD+ ABCD = ABDC+ )
8ince, C+C 1
YA, B, C, D) = ABD
Que 1.11.| Express the following boolea. funetion F in a sum of
and product of maxterms.
mintermsFa, a
y, 2) = (ay + z) (y + xz)

Answer
Given Px, y, 2) = (ry + z) (y+ xz)
+ X.Xy2 + y2 + xz.2
Xyy
2. By ass0ciative property, xx =x
 1-14B (EC-Sem-3) Logic Simplification & Combinational Logic Design
m y + Xy2 + y2 + xz = xy(z + z ) + xyz + (x + X yz + xz(y+ y)

xy2 + Xy z +xyz + xy2 + r yz + xyz + x y z

Xyz +xy z + Xy2 + x y2

CX+X =x)
F=Em(3, 5, 6, 7)
FM Fm = (f +ù+ XT + ù+ 2\x +y+2)(x+ y+)
F=II MO, 1,2, 4)
Que 1.12. Simplify the following boolean expression to a minimum
number of literals.
i. AC +ABC+ AC +
AB
ii. ( y +z) +z + ry + wz
AKTU 2014-15, Marks 3.5
Answer
i. AC +ABC + AC + AB
Let Y= AC + AC + AB+ ABC
=
C(A+ A)+ A (B + BC)
= C+ A(B +C) : A+ A = 1l]
= C+ AC AB : C +AC C A)C +C}
+ = +

= C+A+AB
= C+ A(1 +B)
= A+

ii. (y +z) +z+ ry +Ywz= (xy

Let +z) + 2 + y + Wz

= Xy + 2 + Xy + wz

xy +Xy +2 (1 + W)
=
Xy +xy +2 =x
Oy+2 : 1 +w = 11
Que 1.13.| Convert the given expression into canonical SOP form
Y A
+AB +BC
Answer

Y =A(B+BXC +C)+ ABC +C)+ BC(A+ A)

Y= (AB+ ABNC +
C)+ ABC+ABC+ ABC ABC
= ABC+ ABC+ ABC+ ABC+ ABC+ ABC ABC ABC

ABC+ABC+ABC +ABC + ABC

A +A =A|
 1-15B (EC-Sem-3)
Digital System Design

expression into canonical POS form

Que 1.14.Convert the given
Y AlA+ B)A +B+ C)
Answer

Y= (A BB CCXA +B+CCXA+ B+C)

= (A - BB CKA BB CHA +B +CXA + B C) (A +BC)
= (A B+CKA +B CHA +B+CXA +B +C)
(A+ B+CXA + B +CXA + B +C)

Y= (A+B+CXA
+B+CXA + B+ CXA +B+C)
PART-4
Karnaugh Maps Upto 6 Variables.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

ue 1.15. Write a short note on Karnaugh map. Also show the

reduction of boolean expression and how to mark pairs. How gate
level minimization is implemented ?

Answer
Karnaugh map is another way of presenting the information given by a
truth table. These maps are also known by the name K-map. Let us
consider the map for two variables. There may be four
possible
combinations within four squares
2 Each square represents unique minterms as shown in Fig. 1.15.1
B
B B
A
A AB AB DO 01
OR
AB AB 10 11

Fig 1.16.1.
For three variables:
There are eight minterms for three binary variables. Hence the
k-map
consists of eight squares.
1-16B (EC-Sem-3) Logic Simplification & Combinational Logie Design
2 The R-map drawn in Fig. 1.15.2, for three variables is marked with
numbers in each row and each column to show the relationship between
the squares and the three variables.
3C
BCBC BC BC A00 01 11 10
mo ma m2 0 000 001 011 010
OR 2
A mms m7 1
100 101| 111|
5 7 1106
Fig 115.2
3. For example, the square assigned to m, which corresponds to row
and column 01. When these two numbers reconsidered, they give the
binary number 101, whose decimal equivalent is 5.
For four variables
1. The map for boolean function of four binary variables require sixteen
minterms, hence the map consists of sixteen squares.
The listed terms are from 0 to 15, i.e., 16 minterms. The map shows the
relationship with the four variables.
3. In every square the numbers are written. The number
denotes that
this square corresponds to that number's minterm.

AB CD CD CD CD CD
AB00 01 11 10

AB m m m3 00 0000 0001 0011 0010

AB m4 m5 m7 01 0100 0101 0111 0110 6
OR
AB m12 m13 m15 m14 11 1100 1101 1111 1110
12 13 15 14
AB m 10 1000| 1001 1011 1010
8
11 10
Fig. 1.16.3S.

Que 1.16. Simplify the boolean function.

F (w, x, y, z) Em(1,3,7, 11, 15)
=

which has the don't care conditions

d (w, x, y, z) =
Ed(0, 2, 5) AKTU 2016-17, Marks 10
Answer
1. Pw, x, y, z) = Lm(1, 3, 7, 11, 15)
and don't care conditions
dw, x, y, z) = ud0, 2, 5)
Digital System Design 1-17B (EC-Sem-3)

2 The minterms of F are the variable combinations that make the function
equal to 1. The minterms of d are the don't care minterms that may be
either 0 or 1.
3 The K-map simplification is shown in Fig. 1.16.1.

W 01 11 wX 00 1 11 10

o
01 .

F= yz
+WX F = yz + Wz

a) (b)
Fig. 1.16.1
The minterms of F are marked by 1's, those of d are marked by x's and
the remaining is filled with 0's.
To get the simplified expressionin SOP form, we must include all five 1s
in the map, but we may or may not include any of the x's, depending on
the way the function is simplified.
6. In Fig. 1.16.1(a), don't care minterms 0 and 2 are included with the l's,
resulting as
F= yz + wx
7. In Fig. 1.16.1(b), don't care minterm 5 is included with the 1's, resulting
as

F= yz + Wz

8. The K-map in Fig. 1.16.1(b) is more feasible because, we have to use the
minimum don't care.

que 1.17. Simplify the following expression into product of sum

(POS) form
ABC+ ABD+ BCD
ii. ACD +CD +
AB +ABCD AKTU 2014-15, Marks 3.5|

Answer
i. ABC+ ABD+ BCD
1. Let Y= ABC+ ABD BCD
=

ABC (D+ D)+ AB C C)D+(A+ A) BCD

= ABCD+ ABCD+ ABCD+ ABCD+ ABCD ABCD
Y = m(7, 9, 11, 12, 13, 15)
 Combinational Logic Design
1-18B (EC-Sem-3) Logic Simplification &

Now for POS form we will take compleinent function,

Y = I1 M0, 1, 2,3, 4. 5,6,8, 10, 14)

is shown in Fig. 1.17.1.
3. Minimization through K-map

ARC+D C+D C+D C+D

A+BO 0| 0
A+B 0

A+B 13
12|

A+ B
Fig. 1.17.1
Y =
(A + B) A + CMC + D) (B + D)

ii. ACD D + Aß +ABCD

1 Let, Y= ACD+CD+ AB+ ABCD

A(B+B)CD+(A+AXB+BD +AB(C+©XD+D)+ ABCD
= A(B+)C+(A + BD +ABIC+ÕXD+)+ ABCD
= ABCD+ ABC + ABD+ ABCD +
+ABCD+ ABCD+ ABCD+ ABCD
Y =
Em(1, 5, 8, 9, 10, 11, 13, 14, 15)
2. Now for POS form, we have to take compiement function,

Y = I MO, 2, 3,4,6,7, 12)

3. Minimization through K-map is shown in Fig. 1.17.2.
CD C+ D C+D + D C+ D
AB
AB
A+BO E
AB
B

Fig. 1.17.2
Y = (A + D) (A + C)(B +C + D)
Digital System Design 1-19B (EC-Sem-3)

Que 1.18. Implement the following boolean function with NAND

gates. Flx, y, z)= m(1, 2, 3, 4, 5, 7) AKTU 2016-17, Marks 10

Answer
The R-map simplification is shown in Fig. 1.18.1.

DO
01 11 10

Fig. 1.18.1.
2. Hence, the simplified function is
F z+y + xy
3. Implementation using NAND gates is shown in Fig. 1.18.2.
F= (r+ ). (7+ y).E)
= 2+*y+R.y

xy =x +
-xy =X +y

Fig. 1.18.2.

Que 1.19. Simplify the boolean function Y together with don't

care condition d using K-map and implement it with two level NAND
gate circuit.

Y BD BCD+ ABCD AKTU 2014-16, Marks 3.5

Answer
1. Given, Y = BD + BCD+ ABCD

= (A A) BC +C)D+ (A+ A) BCD+ ABCD

=
ABCD+ ABCD+ ABCD+ ABCD+ ABCD+ ABCD ABCD
Y = Em5,6,7, 10, 13, 14, 15)
1-20 B (EC-Sem-3) Logic Simplification & Combinational Logic Design

2. As there is not given any don't care condition so K-map is as shown in

Fig. 1.19.1
AB 00 01 11 10

00

01
15 7
13

Fig 1.19.1.

Y= BD+BC+ ACD
3. NAND gate implementation:

D BD+ B (BD +BC)

BC

D-D ACD
Fig. 1.19.2.

Que 1.20. Minimize the given boolean function using Kmap.

FA, B, C, D) = Zm(3, 4,5, 7,9, 13, 14, 15)

AKTU 2018-19,
Marks07
Answer
CD
AB CD CD CD CD
AB
AB
AB

AB

Fig. 1.20.1.

F= ABC+ ACD + ACD+ ABC

 Digital System Design 1-21 B (EC-Sem-3)

Que 1.21.| Simplify the following Boolean function

using K-map
Y=
Em (0, 1,3, 5,6, 7,9, 11, 16, 18, 19, 20, 21, 22, 24, 26)
AKTU 2017-18, Marks 07
Answer
K-map:
fC. D, E, A, B)

AB
CDE 000 001 011 010 110 111 101 100

01

1 27 31
10
14 30 22 18

Fig. 1.21.1
Y= DEAB CDB+ ACDE +CAB +DB +CDB+CDE CDA
DBEA+ CA)+ CB+ D) +DE(A
+
=

A)
=
DBEA +
CA) + B+ Ë)+ DE(A ®C)+CDB + DA)
Que 1.22. Simplify the Boolean function
FA, B, C, D, E, F) =
Em(0, 5, 7, 8,9, 12, 13, 23, 24, 25, 28, 29, 37, 40, 42, 44,
46, 55, 56, 57, 60, 61)

Answer
Group 1 and group 2 are two pairs of l's in the first 16-cell map.
2. Group 3 is formed by two isolated 1's from first 16-cell map and third
16-cell map.
3 Group 4 is a combination of two quads from first 16-cell and second
16-cell mapP
Similarly group 5 is a combination of two quads from second 16-cell map
and fourth 16-cell
map.
5 Group 6 is again a combination is isolated l's from second and fourth
16-cell maps
6. Finally group 7 is a quad within the third 16-cell map
1-22 B (EC.Sem-3) Logic Simplification & Combinational Logic Design

Group 2
AB JABCDF) AB
cD00 01 1110 cDEF0001 1110
ooui 00
17 19 18
01
Group 1
O 01
20 21 231

ABDE1 Group 411282

1
30
(ACE)10 A25 20
10
Group 3 Group 5 Group 6
BCDEP) BCE) (BCDEF)
AB
EF00 o1 11 10 O0
CD
01
00
01
01 36 373938 52| 53
11 1
46 116061 6362
10 10 56 57 59 58
Group 7
(ABCF)
The expression is,

ABDEF ABCDF + BCDEF

F
ACE BCE +BCDEF+ ABCF
PART-5

Tabulation Quine-MeCluskey) Method.

Questions-Answers

Long Answer Type and Medium Answer Type Questions

What is the significance of Quine-MeCluskey method

or
Que 1.23.
tabular method ?
Digital System Design 1-23 B (EC-Sem-3)

Answer
The K-map method is suitable for simplification of boolean function
upto 5 or 6 variables

As the number of variables increases beyond this, the visualization of

adjacent square is difficult, as the geometry is more involved.
The Quine-McCluskey or tabular method is employed in such cases.
Consider the function,
FA, B,C, D) = Em(0, 2,3,6, 7,8, 10, 12. 13) for simplifying using tabular
method.
Process of solving MeCluskey method
The binary representations are grouped a section of numbers in terms
of the number or l's index as shown in Table 1.23.1.
Now compare each binary term with every term in the next higher
category.
3 Make the two number sectional combination which differ by one bit.
Write binary form of the ninterm cell.
Compare each binary term with higher adjacent cell and write the
combination of 4 cell which are differ by 1-bit.
6 Mark all combinations which are made by the digits of 4 cell.
7 Write the binary form of 4 cell and place a () in place of differ bit.
Table 1.23.1.

No.of Minterms Binary Minterms Binary Minterm Binary

1's (2 cell) 4 cell)

0 0000 2 00 0 0,2, 8,10 00

0, 8 000

2,3 001 2, 3, 6, 7 0 1
0010 2, 010
2, 10 010
1000 8, 10 10 0

, 12 100

2 0011 3,7 0_11

0110 6,7 011

10 1010 12,13 1 10
m2 1100
3 0111
m 1101
1-24 B (EC.Sem-3) Logic Simplification & Combinational Logic Design

Apply same process to the resultant stage.

All the terms which remain unchecked are the PI's. Now prepare a PI
9
chart to determine essential prime implicants
10. All the Pl's are represented in rows and each minterm of function in a
column as shown in Table 1.23.2.

11. Put the O in each row to show the composition of minterms that make
PT's.
Table 1.23.2.

Prime
Minterms| implicant|m m2g s1o a 3

ACD , 12

ABC 12, 13

BD 0, 2, 8, 100

AC 2, 3, 6, 7

13. The column that contains a single dot O is essential prime implicant.

14. A tick mark is put above each column which has only one O mark.

15. The sum of all EPI's gives the function in its minimal SOP form.

FA, B, C, D) = ABC + BD + AC

Que 1.24. Minimize the following switching function using

Quine-MeCluskey method.
Fx,*, , s,) = Em(0, 1,2,8,9, 15, 17, 21,24,25,27,31)

AKTU 2016-17, Marks 15

Digital System Design 1-25B (EC-Sem-3)

Answer
Table 1.24.1. For obtaining all the prime implicants.

No. of Minterms Binary Minterms Binary Minterm Binary

1's 2 cell) (4 cell)
0
000000,1 0000 0,1, 8,9 0 00 C
m
00001 0,2H000 0 1,9, 17,25_001B
m 00010 0,8 0_000 8,9, 24,25_100 _A
01000
1, 9 0_00 1
2 01001 1, 17 -0001
m
10001 8,9 0100
m 11000 8, 24 1000
10101 9, 25 1001
ma 11001 17,21G 10_01

01111 17,25 1_001|

m27 11 011 24,25 1100_
m31 11111 25,27 F 110 1
15,31 E-1111
27,31D 11-11
Table 1.24.2. Prime-implicant

Mintermm, m m, m, m, 7 m
A

F
G

So the essential prime implicants are,

Px, Xg X, X X,)= E+G+A+ H= x,x,t,A, + t , X , +X,t,x,*, t X,X,X,
1-26 B (EC-Sem-3) Logic Simplification & Combinational Logic Design

Que1.25. Minimize the following using Quine-McCluskey

method:
F(W, X, Y, ) = Z m0, 3, 5, 6, 7, 10, 12, 13) +E d(2, 9, 15)

AKTU 2015-16, Marks 15

Answer
1. FW, X, Y, Z) =E m0,3, 5, 6, 7, 10, 12, 13) + Ed (2, 9, 15)
First, we group the minterms according to the numbers of l's.

No. of Minterms Binary Minterms Binary Minterm Binary

(2 cell) 4 cell)
I's
0 m 0000 0,2 00 0 2*,3,6,7 0-1-
dm 00102*,3 001 5, 7,13, 1 5 * 1 1
2 0011 2*, ,6 0 10
0101 2*, 10 _010

m6 0110 3,7 0_11

mo 1010 |
5,7 011_1

m2 1100 5, 13 101

dm, 1001 | 6,7 011

3 0111
12,13110
m3 1101
9,13 1_01
1111 7, 15* 111
13, 15 11-1
2. Then, we
prepare the table of prime implicants.
Prime
Minterm | implicant m m m m,
WXZ D,,2

XYZ 2 ,10

WXY 12, 13

WYZ 9 ', 13

WY 2,3,6,7
XZ 5,7, 13, 15*| O
F(W, X, Y, Z) = WY + XZ + WXZ XYZ WXY
Digital System Design 1-27 B (EC-Sem-3)

Que 1.26.Use Quine-McCluskey (QM) method to solve the

following function:
FA, B, C, D) = E m(5, 7,8, 9, 10, 11, 14, 15)

AKTU 2014-15, Marks 3.5

Answer
1 F(A, B, C, D) =
Em(5, 7, 8,9, 10, 11, 14, 155
No. of Minterms Binary Minterms Binary Minterm
(2 cell)
Binary
(4 cell)
1000 89 100- 8, 9, 10, 11
10
2. 0101 8,10 10_0 10, 11, 14, 15 11
1001 5,7 011
1010 9, 11 10 1
3 0111 10,111
m 101
m 1011 10, 1 4 1-10
1110 , 15 .111
4
m15 1111 11, 15 1-11
14, 15 111
2 All the terms which unchecked
are are prime implicants.
Now, we prepare a prime implicant chart to determine essential
prime
implicant is as follows

Minterms Prime implicants m s m10 1 "141

ABD 5,7

BCD , 15

8,9, 10, 11
AB
oooo
AC 10, 11, 14, 15
olo oo
Therefore, FA, B, C, D) =AC+ AB ABD
1-28 B (EC-Sem-3) Logic Simplification & Combinational Logic Design

3. Logic diagram:

AB -F= AC+ AB+ ABD

B-
ABD
D

Fig. 126.1.

Que 1.27. Use the Quine-McCluskey method to generate the set of

prime implicants for the following function:
FA, B, C, D) = Zm(0, 1, 4, 5, 6, 7, 9, 11, 15) +D¢ 10, 14).
Also obtain all minimal expressions for the function. Draw a logic
diagram using only NAND gates to implement your best solution
obtained.

Answer
1. Given, FA, B, C, D) = Xm(0, 1, 4, 5, 6, 7,9, 11, 15) + Xo(10, 14)

No. of Minterms Binary Minterms Binary Minterm Binary

1's (2cell) 4 cel)
m 0000 0,1 000 0, 1, 4,5 0
0001 0, 4 0_00 4,5,6,7 01
m 0100
1,5 0_01 6, 14*',7. 15111
2 m 0101 1,9 001

0110 4,5 010

m 1001 4,6 01

dm o 1010 ,7 011

0111 6,7 011

1011 6, 14 110
10 1
dm 11109,11
1111 10, 11 101-
15
11, 15 11
14*, 15
111-
Digital System Design 1-29 B (EC-Sem-3)

Mintermns Prime
o m,| m mu
implicants
A'C' 0, 1,4,5

A'B 4,5, 6,7

BC 6, 14*,7, 15

B'C"D 1,9

AB'C 9,11

ABC 10,11

ACD 11,15

ABC 14*, 15

The essential prime implicant,

FA, B, C, D) = AC

A-DA
Fig. 1.27.1.

que 1.28.| Minimize the following using Quine-MeCluskey

method:

FA, B, C, D) = Zin(0, 1,9, 15, 24, 29, 30) + E d(8, 11, 31)

AKTU 2018-19, Marks 07

Answer |

1 Arrange minterms according to categories of I's as shown in table 1.28.1

1-30 B (EC-Sem-3) Logic Simplification & Combinational Logic Design

Table 1.28.1.

No. Min-
of terms
Binary Minterms Binary Min- Binary
(2 eell) terms
's 4 cell)
ABcDE A BcDE ABCDE
mo00000 0,1 0o 0 0-0,1,8*90 0 0 -
m 0 01 0,8*
dm 10 olo 1,9 0-00 1
g
o 1oo1 8,9 0
m m24 olo|o824-oo

3 dmu o18,11 0 -1|

m5 0 11 1 1 11, 15 1-|1|1
mg9 1 110 1 15, 31
m3o 1 11 1 029, 31*
6 dmg 1111 30.,31 1 11
2 List of prime implicants:
Table 1.28.2.
Prime implicants Binary representation
B C D E
8 , 24
1 0 0 0
9,1
11*, 15
15, 31
29, 31*

30,,31
0, 1,8,9
3. Select the minimum number of
the minterms except don't care
prime implicants which must cover all
minterms.
 1-31 B (EC-Sem-3)
Digital System Design
Table 1.28.3.

Mintermn
Primeimplicant
9 15 24 29 30
24

9,111*

11*, 15 O

15, 31*

29,31*
30,31
0, 1,8,9

Y BCDE+ ABCE+ ABCD+ ACD

VERY IMPORTANT QUESTIONS

Following questions are very important. These questions
may be asked in your SESSIONALS a s uwell as

UNIVERSITY EXAMINATION.

Q.1. Design a combinational circuit that converts a BCD code

to excess-3 code.
S s Refer Q. 1.4, Page 1-6B, Unit-1
Q2. Simplify the following boolean expression to a minimum
number of literals.

i. AC +ABC+ AC + AB
ii. ( y + z)+z+ *y+ wz
Ana Refer Q. 1.12, Page 1-14B, Unit-1.

Q3. Simplify the boolean function.

F (w, x, y, z) = Eml1,3,7, 11, 15)
which has the don't care conditions
d (w, x, y, z) = Ed0, 2, 5)
AB Refer Q. 1.16, Page 1-16B, Unit-1.
1-32 B (EC-Sem-3) Logic Simplification & Combinational Logic Design

with don't care

Simplify the boolean function Y together
Q.4. condition d using K-map and implement it with two level
NAND gate circuit.
BCD+ ABCD
Y=BD+
Ans Refer Q. 1.19, Page 1-19B, Unit-1.

function using K-mapP

Q.5. Simplify the following Boolean 26)
Y= Em(0, 1,3, 5, 6, 7, 9, 11, 16, 18, 19, 20, 21, 22, 24,
An Refer Q. 1.21, Page 1-21B, Unit-1.

Minimize the following switching function using

Q.6.
Quine-McCluskey method.
1,2, 8, 9, 15, 17, 21, 24, 25, 27, 31)
Fa, x, *, * *,)= Zm(0,
Ans Refer Q. 1.24, Page 1-24B, Unit-1.
method to solve the following
Q.7. Use Quine-McCluskey (QM)
function:
15)
FA, B, C, D) Z m(5, 7, 8, 9, 10, 11, 14,
=

Ans Refer Q. 1.26, Page 1-27B, Unit-1.

2 UNIT
MSI Devices

CONTENTS
Part-1 MSI Devices Like Comparators.. 2-2B to 24B

Part-2 Multiplexers ***

2-5B to 2-11B

Part-3 Encoder .****************************************************

.. .212B to 2-14B

Part.4:Decoder . . . *********************************.
.2-14B to 2-19B

Part-5 Driver and Multiplexed Display. 2-19B to 2-20B

Part-6 Half and Full Adders *** .2-20B to 2-23BB

*********************

Part-7 : Subtractors.******************************************* 2-23B to 2-26B

Part-8 Serial and Parallel Adders ******************2-26B to 2-27B

Part-9 BCD Adder ************************ **** 2-27B to 2-28B

Part-10: Barrel Shifter and ALU...

********************* 2-29B to 2-30B

2-1 B (EC-Sem-3)
2-2B (EC-Sem-3) MSI Devices

PART-1
MSI Devices Like Comparators

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que2.1. What is magnitude comparator ? Design a three bit

comparator circuit using logie gates.

Answer
1. Amagnitude comparator is a combinational circuit designed primarily
to compare the relative magnitude of the two binary numbers A and B.
2 Naturally, the result of this comparison is specified by three binary
variables that indicate, whether A> B, A = B or A <B.

3. The block diagram of a single bit magnitude comparator is shown in

Fig. 2.1.1.

Inputs Magnitude
Comparator A <B
Fig 211
4. EX-OR and AND gate is used to implement the circuit. If the
EX-OR gate and two AND gates are combined, the circuit will function
as a single bit magnitude comparator as shown in Fig. 2.1.2.
5. The cirecuit diagram and truth table of a single bit magnitude comparator
is shown in Fig. 2.1.2.

Inputs Outputs
AB Z 2Z2
A 0

-2 1 0 0

Fig. 2.1

2, is high when A > B,

Z, is high when A = B,
Z, is high when A < B.
Digital System Design 2-3 B (EC-Sem-3)

The concept adopted to form ann-bit

same is
magnitude comparator.
3-bit magnitude comparator:
A = A,A, A,

Two number A and B

B B,B, B
are equal, only if all the pairs of significant digits
are equal. i.e.,
A, B, A, = B,, A, = B,
When numbers are binary, then equality relation of each pair of bits
can be
expressed by the equivalent function as,
x= AB +AB,i =0, 1,2
Design procedure
(A B)
=

x *, , (A O B,) {A\ OB)(A, O B,)

= =

(A> B)= A,B,

+z,A,B,+xgaAnBy
(A <B)=
AB, x,A,B, +2t1ApB%
+

Ag
A < B)

B2D D
A
Bi D A > B)

Ao D1

(A B)

Fig. 2.13. 3-bit magnitude comparator using logie

gates
Que 2.2. Design and explain the logie and circuit of 4-bit
magnitude comparator. AKTU 2014-15, Marks 06
OR
Design a 4-bit magnitude comparator using one bit comparator
modules.
OR
AKTU 2016-16, Marko 10
Draw and explain 4-bit magnitude comparator.

AKTU 2017-18, Marka 07

2-4 B (EC-Sem-3) MSI Devices

Answer
1 Let two numbers A and B with four digits each.
A A,A,A,A
B B,B, B,B,
The two numbers are equal if all pairs ofsignificant digits are equal
2 ie., ifA, = B,A= B, A, =B, and A, =B, Equality relation is generated
by EX-NOR gate.
x, AB+ AB,; i = 0, 1, 2, 3.
where x, is equality of two numbers
x= 1, if A B
=

x = 0, otherwise,
A =B) = xzp,= 1, if all pairs are equal.
3. To determine if A> B or A < B,

A>B)= A,B,+zA,8, +z% A,B, +x4,iAB,

(A «B)= +, + xA,, + z,*aA,B,
4. The logical implementation is shown in Fig. 2.2.1.
As

B3

A
B2

A A<B)
B

Ao
AB)
BoA

D- -(A = B)

Fig 22.1.4-bit magnitude comparator using logic gates

 Digital System Design 2-5 B (EC-Sem-3)

PART-2
Multiplexers8

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 23 What is the role of multiplexer in the digital electronics ?

Explain the logic how it selects a one input among several inputs.

Answer
1. A multiplexer (MUX) is a combinational circuit that selects one input
out of several inputs and directs it to a single output.

2 The particular input selection is controlled by a set of seleet inputs

3 The block diagram of a digital multiplexer with n input lines and single
output line is shown in Fig. 2.3.1(a).

n
-Y 4:1
MUX
MUX

S, S Sm
(a) n: 1 MUX (6)4:1 MUX
Fig 2.3.1
4 Por selecting one input out ofn inputs, a set of m select inputs is
required where, n = 2
5. On the basis of binary code applied at the select inputs, one output of
n data source is selected. An enable input (E') is built-in for cascading
purpose. Enable input is generally active low.
6 A circuit diagram for a possible 4: 1 data multiplexer as shown in
Fig. 2.3.1(b).

Que 24. Implement the function

FA, B, C) ABC+ ABC

Using 4:1 multiplexer using B and C variables to the selection lines.
2-6B (EC-Sem-3) MSI Devices

Answer
Given. FA, B, C)= ABC+ AB + ABC + ABC
2. Implementation using 4: 1 MUX, FA,B, C) = Em(1, 2, 4, 7)

Input I,21
A O 3 MUX
AO6
Output to A A' A' A
A'
A
multiplexer C
Fig 2.4.1.

Que 2.5. Construct a 16 x 1 multiplexer with two 8 x 1 and one

2x1 multiplexer. Use block diagrams.
Answer

8 x1
MUX

2x1
MUX

Ss
8x1
0-
3 MUX

F .6.1
Que 2.6. Design the following boolean function using 4 x 1

multiplexer. AETU 2014-15, Marke 0

PA, B, C, D) = Z m(0, 1,3,4, 8, 9, 15)
Digital System Design 2-7B (EC.Sem-3

Answer
Given, F (A, B, C, D) = E mi0, 1, 3, 4, 8, 9, 15)
2 We have to design it using 4: 1 multiplexer, so we can use two variable
(A, B) for select lines and implementation table is as follows:

2
CD 12

CD 5 13

CD 2 10
14
CD 3 7 11

CD
3. Now,. CD+CD+ CD =+D

I= CD
4. Logic diagram is shown in Fig. 2.6.1
C-
D-

D 4x1
MUX
-F(A, B, C, D)

Que2.7 Design the following boolean funetion using the

multiplexer :

PA,B,C, D) = Z
m(0,3,5, 6, 8,9, 14, 15).
Answer
FA, B, C, D) = E m(0, 3, 5, 6, 8, 9, 14, 15)
2-8B (EC-Sem-3) MSI Devices

Do
D
D2
8:1
MUX
DD,D, D, D,D, D, D,
Ps
D
OO 101 12 13
1 A 0 A0 A 1 A
BCD
(a) Implementation table (6) Multiplexer implement..tion
Fig. 2.7.1
Que 2.8. Implement the function F =Em(0, 1, 3, 4, 7, 8,9, 11, 14, 15)
using 8:1 mux. AKTU 2017-18, Marks07
Answer
1. The given Boolean function is a four variable function. Any one variable
of the function can be taken as input to the MUX and the remaining
variables are connected to the selection lines.

Decimal A D
0

9 0

14
15
Digital System Design 2-9B (EC-Sem-3)
2 A is assumed to be MUX input and B,C, D are used as selection lines.

A is complement variable of A for the minterm 0 to 7.

A is normal variable (A) for the minterm 8 to 15.

We enter the complement variable minterms in first row of

implementation table and enter normal variable minterm in second
row of implementation table.

Implementationtable

5 6

A
1 0 12 13
1 1 AO A 1

Logic diagram:
Logic 1

Logic0

81
MUX
F(A, B, C, D)

BC D
Fig. 2.8.1.

Que 2.9. Implement the following Boolean function.

FA, B, C, D) = 20, 1,3, 4,7,8,9, 11, 14, 15)
i 4:1 MUX
is. 2:1 MUX
AKTU 2018-19, Marks07
 MSI Devices
2-10B (EC-Sem-3)

Answer
4:1 MUX:
Implementation table :
AB AB AB AB

(00) C O 0 12

(01)CDO 5 13

(10)
CD 2 6
1019

First column (,) = CD+CD+ CD

= CD+ D) +CD = + CD

= +D
Second column , )
= CD+ CD =C O D Ex-NOR)

Third column (7,)

= CD +CD + CD

= D+ D)+ CD
C+CD = C+D

Fourth column , )
= CD+CD

CD + D) =C
Logic diagram :

T T|
DH 4:1
-FA, B, C, D)

MUX

Select
A B lines
Fig. 2.8.1.

ii. Implementation using 2:1 MUX: MUX and one variable as

We have to use three variables as input of

select line
Digital System Design 2-11 B (Ec-Sem-3)

Implementation table:

o
ABC
ABC 2 3
ABC

ABC 6

ABC
ABC 10

12 13
ABC
ABC

First column ,)

ABC+ABC+ AB+ ABC

AC (B+ )+ A(BC +BC)
= AC+ AB OC)
Second column (7,)
ABC+ ABC + ABC+ AB+ ABC + ABC
= BC (A+ A)+ BC (A + A) + BC(A A)
BC +BC+ BC
BC+C)+BC
B+BC
B+C
Logic diagram:
A
C-Do

B o
2
MUX FA, B, C, D)

C
Select line
D
Fig. 2.9.2.
2-12 B (ECSem-3) MSI Devices

PART-3

Encoder

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 2.10 What do you mean by encoder 7

Answer
Encoder:
The encoder is another example ofcombinational circuit that performs
the inverse operation of a decoder. It is designed to generate a different
output code for an input which becomes active.
2 In an encoder, the number of outputs is less than the number of
inputs. There are 2" input lines and n output lines.
3. The block diagram ofan encoder is shown in Fig. 2.10.1.

2
inputs Encoder
outputs
Fig. 2.10.1

Que 2.11.What is priority encoder ? Explain with the help of

suitable example.
OR
Write short note priority encoder.
a on
AKTU 2018-19, Marks 07
Answer
Priority encoder: In priority encoder if two or more inputs are equal
to l at the same time, the
input having highest priority will be considered.
Example:
Four inputs Dg, D,, D,, D, where D, has highest priority and D, has
lowest priority

YoY,: binary output

V: validity of output
Digital System Design 2-13B (EC-Sem-3)

Table 2.11.1 Truth table for 4-bit priority encoder

Input Output
D,D, D,D
0 0

D,D3 For 1
DD3 ForYo
D,D 00 01 11 10
D,D00 1 11 10

00 o

01 01

11

10
9 11 10 9 10
Y = D2+ D3
Yo Dg+ D,D,
DD For V
00 01 11 10
D,D
00

01

11
12 15 14

10
V-
D+D+ D,+ D
Fig 2.11.1,
2-14 B (EC-Sem-3) MSI Devices

Logicdiagram:
D D2 D, D

Fig. 2.11.2.

PART-44|
Decoder.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 2.12.|Write a short note on decoder.

Answer
1. A decoder is a combinational circuit that converts binary information
from n input lines to a maximum of 2" unique output
lines
2. If the n-bit coded information has unused combinations, the decoder
may have fewer than 2" outputs.
The decoders presented here are calledn to m line decoders, where
m
s2". Their purpose is to generate the 2" (or fewer) minterms of n
input variables.

n input lines
n:2 m output lines
decoder m = 2n

Enable
Pig. 212.1.Block diagram ofadecoder
Digital System Design 2-15B (EC-Sem-3)

2 to 4 binary decoder:
Fig. 2.12.2shows the 2 to 4 decoder. Here 2 represent the input lines and
4 represents output lines. Fig. 2.12.2 shows the truth table for a
2to 4 decoder. Ifenable (E) is 1, one and only one of the outputs Y, to Y,
is active for the given input.

A B Enable
Inputs Outputs | E

EABY,Y,Y,Y
X0 0 0 0
o o0o1 Yo
101 o 0 1o Y
1 1 0 010
1 1 110 0 Y3
Fig. 2.12.2. Logic diagram of 2 to 4 decoder.

Que 2.13. Using a decoder and external gates, design the

combinational eircuit defined by the following three boolean
functions:
F -*'yz'+ z, F,= zy?+yz', F, =*'y? +ay
AKTU 2015-16, Marks 10
Answer
Let us consider 3 to 8 line decoder. The implementation of the given
three funetions using 3 to 8 line decoder and a few OR gates are shown
as follows
F = x'yz'+ xz = x'yz' +xz(y +y')
*'yz' +xy2 + xy'z = Em(2, 7, 5)
F, = xy'z' + yz' = xy'z' + (x +x')>yz'
= xy'z' +xyz' + x'yz' = m(2, 4, 6)

x'y'z' +xy =x'y'z' +ay(z + z')

= xy'z' + xyz + xyz' = L m(0, 6, 7)

3: 8
Decoder Y

Fig2.13.1. 1mplementationofthe given Boolean funetion using 3:8 decoder.

 MSI Devices
2-16 B (EC-Sem-3)

logie diagram of two to four line decoder

Que 2.14.| Draw the a

using NOR gates only. AKTU2016-17,Marka10

Answer
Truth table:

Enable Input Output

E A B

0 0

0 0 0
0
Circuit using NOR gate :

B Y (A + B + E) =

Y =(A +
B +) =

) ABE
-Y ( B+ =

Y +) =
A BE
E- Fig. 2.14.1.

Que 2.15. Design a full subtractor circuit with a decoder and two
OR gates.

Answer
Full subtractor using decoder:
Input Output
B C
B

Difference D m1, 2, 4, 7)
Borrow B, =
2m(1, 2, 3, 7)
Digital System Design 2-17B (EC-Sem-3)

3:8
Decoder
C-
B
Fig.2.15.1. Full subtractor using 3:8 decoder.

Que 2.16.| Design a BCD to 7 segment decoder. Assume positive

logic, minimize the function.
AKTU 2014-16, Marks 06
Answer
1. The truth table for a BCD to 7 segment decoder is as given as follows:

Digit BCD input 7-segment

A BCD C
d f
1 0 0
0 1
3 0 0 1 1
0 0
5 1 1
6 1
0
0 0
9 1 0 0
2. The unused BCD codes are 1010, 1011, 1100, 1101, 1110, and 1111. So
place x (don't care condition) for these corresponding cels.
K-map simplification
CD For a CD For b
00 01 11 10 00 01 1 1 0
AB AB

0 00

01 01

11

10 10

a =A +C+BD+ BD B
b CD CD
2-18 B (EC-Sem-3) MSI Devices

For c For d
CD CD
00 01 11 10 01 11 10
AB AB

00 00

01 1

11 1

10 10

C B + C + D d BD + CD + BCD +BC + A
For e For f
CD CD
00 01 11 10 00 01 11 10
AB AB

00 00

01
11
0111 /1

e BD+CD f= A+ CD+ BC + BD5

CD Forg
AB0001 11 10,

00
01

1o
g AB C+ BC +C D
Pig. 2.16.1.
3. Fig. 2.16.2 shows the logic diagram of BCD to 7 segment display decoder.
Digital System Design 2-19B (EC-Sem-3)

A B
R
BD

BD

CD

CD
BCD

BC
BC
-f

Fig. 2.16.2,

PART-5
Driver and Multiplexed Display.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 2.17. Explain multiplexed display.

Answer
In a multiplexed display, each seven-segment display is lit in turn with
its appropriate value. This is done by outputting the appropriate lines
with one part of the driver chip, while another part of the logic enables
2-20 B (EC-Sem-3)
MSI Devices

the common cathode connection of the selected seven-segment display,

(Fig. 2.17.1).
small time later, the common cathode of the next display is
2 Then a

activated and lit with its required number.

would s e e each
3. Thus if you could look at the display in slow motion, you
of the seven segment displays light then go out sequentially.

4. The trick is that if the displays are strobed suficiently rapidly (say a few
on all
hundred times a second) the eye is deceived into thinking they are
the time, just like a television set.
of
The advantages of multiplexed displays are as follows: only
one set
5.
connections need to
current-limiting resistors is required, fewer wiring
be made and power consumption is less since only one seven-segment

display is lit at any given time.

manufacturers,
6. Also, since multiplexed display chips are available from
one yourself.
you do not have to design and build

330
Multiplex
driver

B
IA lit
Blit
IC lit

A lit Blit| Clit

Fig.217.

PART 6J
Halfand Full Adders
Questions-Answers
Long Answer Type and Medium Answer Type Questions
Digital System Design 2-21 B (EC-Sem-3)

Que 2.18.| Describe half adder and full adder in brief. Implement
the circuit using logic gates.
OR
Design a full adder using two half adders.

AKTU 2015-16, Marks 7.5

Answer
Half adder:
1. The block diagram of half adder is shown in Fig. 2.18.1.

B- Half Adder
Fig. 2.18.1. Half adder.
where, A and B are the inputs and S and C are the outputs sum and
carry respectively.
2. The truth table and K-map of the system are shown in Fig. 2.18.2.

Input Output B
For S B For C

A B S C A 0 0
0
0 1
0

Fig.2.18.2
3. Using two-variable K-map, separately for the sum and carry.
S AB+ AB =A ®B
AB
4. The circuit be
can
implemented using XOR gate.
D-s
D-c
Fig. 2.18.3.
Full adder:
Full adder is circuit that performs the addition of three binary
a
has three inputs A, B and C with two
digits. It
output S and C,, where C is the
previous carry. The block diagram is shown in Fig. 2.18.4.
S
B Full Adder
C
Fig. 2.18.4. Pull Adder
If there are three
input variables the combinations are eight (2" =
8).
Now form the truth table of the full
adder
2-22 B (EC-Sem-3) MSI Devices

Inputs Outputs
B C S C
0

For S For (
BC
A 00 0111 10 00 01 11 10

Fig. 2.18.5.

3. Sumn: S ABC+ ABC+ ABC+ ABC

Carry C. AB+AC +BC
4 A full adder can be implemented using two half adders and one OR gate.
Sum : S ABC+ AB + ABC
= ABC+ AB +

= C(AB + AB) + (AB+

= C(AB+ ÄB) + (AB+ AB)

= (A B ) OC

Carry C AB +AC + BC
AB +C A + B)
= AB+C A+ B)(A+ A)(B + B)
= AB+ClAB+ AB+ AB]
= AB+ ABC +C(AB+ AB)
AB(1+ C)+CA ® B)
= AB+C A DB)

Hulf adder

Fig. 2.18.6. Full adder cireuit using 2 half adder

Digital System Design 2-23 B (EC-Sem-3)

Que 2.19. Implement a full adder circuit using 4 x 1 multiplexer.

Answer
1. Canonical form of sum and carry for full adder
Sum E m(1, 2, 4, 7) = BCA + BCA+ BCA +BCA

Carry m(3, 5, 6, 7) = BC BCA + BCA + BCA

= BCA+ BCA + BC

For sum:

4:1 Sum
MUX

A A A A B C
MUX implementation for sum
Implementation table

Fig. 2.19.1
For carry:
I1 4:1ECarry
O 2 a MUX

0 A A
Implementation table MUX implementation for carry
Fig-2.19.2.

PART-7
Subtractors
Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 2.20, Describe a half subtractor with its logic diagram.

Answer
1. The block diagram is shown in Fig. 2.20. 1.
A-
Half subtractor
B- Bo
Fig, 2.20.1. Halfsubtractor
2-24 B (EC-Sem-3) MSI Devices

2. It has two inputs, A (minuend) and B (subtrahend) and two outputs D

(difference) and B, (borrow) are produced by subtraction of two bits.
3. The truth table can be formed by keeping in mind that difference (output)
B. The and truth table are shown in
is 0 if A = B and 1 if A *
K-map
Fig. 2.20.2.

Inputs Outputs A 0 A 0

A BD B
0 0
0 1

D ABA'B =A ® B B. A'B

Pig 9.20.2
4. The logical implementation using basic logic gates and XOR gate
D
XOR gate
implementation
-B,
Pig 220.8.

Que 2.21. Design a full subtractor circuit with three inputs x, y.

Band two outputs Diff and Bu The circuit subtracts x-y-B
where, B, is the input borrow, Bu is the output borrow and Diff is
the difference. AKTU 2016-17, Marka 10
Answer
It isa combinational cireuit that performs the subtraction ofthree binary
digits.
Diff
Full subtractor
Bin Dout
Flg. 9.21.1
2. Fig. 2.21.1 shows the block diagram approach of full subtractor. It has
three inputs x, y and B and two outputs Diff and B produced by
subtraction of three input bits.
3. For the formation of truth table, eight possible combinations of three
input variables with their outputs are required.
Digital System Design 2-25 B (Ec-Sem-3)

Inputs Outputs
Diff

4. Using the concept of K-map, reduce the truth table to a function (algebraic
or boolean).

yB,
01 11 10 00 01 11 10

Diif= x y Bin + x y Bin + xyBin + xyBin BoutX Bn+yBin+ Xy

Fig. 2.21.2
5. A full subtractor also be
can
implemented using two half subtractors
and an OR gate.
Diff
syB + B. + +y B, + E JB,,
B,(xy + ï )+ B, (x j+ ï y)

Bxy)+ B. x ®y) =(x ® y) O B,

and B y+ ~ B, + yB, = 7y+ B_(F + y)
=
y+ B, (+ y)(x +
+) (y +5)
y +
B (+y + ay +ï y) =
+y +
+yB +B,(ry + F 5)
=
y{B +1)+ B,,(x y) =
F y +
B, (x Dy)
Half subtractor
Bin Diff

--.
-Bout
Fig. 2.213. Full subtractor cireuit using 2 half subtractor.
2-26 B (EC-Sem-3) MSI Devices

Que 2.22. Draw a full subtractor eircuit using NAND gate.

|AKTU2018-19, Marka 3.5

Answer
Full subtractor using only NAND gates

A®Be B, =
(A ® BXA ®BB, B,(A ® B)B,
BAAB+
out
B,(A ® B) = AB+ B,(A ® B)

AB. B(A® B) =B( +B) B, +

(A ®B)|
BouB AB B. B, (A e B)
By using the above expressions for D and Bt the full subtractor is
implemented using only NAND gates as shown in Fig. 2.22.1.

Bi n

Fig. 2.22.1.Full subtractor using only NAND gate.

-Bout
PART-8B
Serial and Parallel Adders.
Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 2.23. Design a 4-bit binary parallel adder.

Answer
1 The sum of two n-bit binary numbers, A and B, can be generated in two
ways: either in a serial fashion or in para llel.
2. The series addition method uses
only one full-adder circuit and a
storage
device to hold the generated output
carry.
3 The pair of bits in A and B are transferred serially, one at a time,
through the single full-adder to produce a string of output bits for the
sum.
Digital System Design 2-27B (EC-Sem-3)

4
The stored output carry from
for the next pair of bits.
one pair of bits is used as an input carry

. The parallel method usesn full-adder circuits, and all bits of A and B
are applied simultaneously.
6. A binary parallel adder is a digital function that produces the arithmetic
sum of two binary numbers in parallel.
7. It consists of full-adders connected in cascade, with the output carry
from one full-adder connected to the input carry of the next full-adder.

FA FA 3 FA FA

S Sa S
Fig.2.23.1.4bit full adde

PART-9
BCD Adder.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 2.24.| Draw a BCD adder circuit and explain its working.

OR
AKTU 3013-10, Mlarka07
Draw a decimal adder to add BCD number.

AKTU9017-18,Marke 07
Answer
1. BCD adder is circuit that adds two BCD digits in parallel and produces a
Bum digit which is also BCD. BCD numbers use 10 symbols (group of
4 bits 0000 to 1001). BCD adder circuit must be able to do the following
and it is shown in Fig. 2.24.1
Add two 4-bit BCD numbers using straight binary addition.
 MSI Devices
2-28 B (EC-Sem-3)

the sum is a valid BCD number and

equal to or less than 9,
3. If 4-bit sum is

no correction is needed.
is generated from the sum,
Ifthe 4-bit is greater than 9 or ifa carry
sum
should be added
invalid BCD number. Then the digit 6 (0110),
the s u m is

the sum to produce the

valid BCD symbols.
to

Addend (BCD digit) Augend (BCD digit)

Binary adder-1 Carry in

Output
carry

C K+ Zg Z4+ Zg2

4-bit binary adder

S, S, S, S
Fig. 2.24.1. Block diagram of a BCD adder

Binary Sun BCD Sum Decimal

Z cs5,, S
0 0 0
1 0 0
0 0
1 0
0 0
0
1
0 0 0
0 0 0 9
10
11

PART 10
Barrel Shifter and ALU.
Digital System Design 2-29 B (EC-Sem-3)

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 2.25. Explain barrel shifter.

Answer
1. A barrel shifter performs a right rotate operation. It handles left
rotations using the complementary shift amount.
2. Barrel shifters can also perform shifts when suitable masking hardware
is included.
3. Barrel shifters come in array and logarithmic forms; we focus on
logarithmic barrel shifters because they are better suited for large
shifts
A A A A Aa A A Ao left

Preshift

Y YY Y
(a) (b)

A A left

T*
sign Mask arithmetic
shift

(c)

Fig. 2.26.
2-30 B (EC-Sem-3) MSI Devices

Fig 2.25. 1(a) shows a simple-4 bits barrel shifter that perfor ms right
rotations. How, unlike funnel shifters, barrei shifters contain long
Wrap-around wires.
In a large shifter, it is beneficial to upsize or buffer the drivers for
these wires. Fig. 2.25.1(b), shows an enhanced version that can rotate
left by prerotating right by 1, then rotating right by k .
6 Performing logical or arithmetic shifts on a barrel shifter requires a
way to mask out the bits that are rotated off the end of the shifter, as
shown in Fig. 2.25. 1(c).

Que 2.26. Write a short note on Arithmetic Logic Unit (ALU).

Answer
An Arithmetic Logic Unit (ALU) is a multioperat ion, combinational
logic digital function.
It can perform a set of basic arithmetic operations and a set of logic
operations. The ALU has a number of selection lines to select a
partieuBar operation-in the unit.
3 The selection lines are decoded within the ALU so that k selection
variables can specify up to 2" distinct operations.
4 Fig. 2.26. 1 shows the block diagram of a 4-bit ALU.
5. The four data inputs from A are combined with the four inputs from BB
to generate an operation at the F output.
6 The mode-select input s, distinguishes between arithmetic and logic
operations.
7 The two function-select inputs s, and s, specify the particular arithmetic
or logic operation to be generated. With three selection variables, it is
possible to specify four arithmetic operations (with s, in one state) and
four logic s, the other state).
operations (with in
8 The input and output carries have meaning only during an arithmetic
operation.
9. The inputcarry in the least significant position of an ALU is quite often
used as fourth selection variable that can double the number of
arithmetic operations. In this way, it is possible to generate four more
operations, for a total of eight arithmetic operations.

A, A A A B, B, B, B, -B (Mode-select)
Arithmetie logic unit
Cout Funetion-selecth
(ALU)
(Output carry
F, F,F, F -C nput carry

Fig. 2.26.1.
Digital System Design 2-31 B (Ec-Sem-3)

VERY IMPORTANT QUESTIONs

Following questions are very important. These questions
may be asked in your SESSIONALS as well as
UNIVERSITY EXAMINATION.

Q.1. Draw and explain 4-bit magnitude comparator.

Ans Refer Q. 2.2, Page 2-3B, Unit-2.
Q.2. Design the following boolean function using 4 x1
multiplexer.
FA, B, C, D) =
Em(0, 1,3, 4, 8, 9, 15)
Ans Refer Q. 2.6, Page 2-6B, Unit-2.
Q.3. Implement the function F Em(0, 1, 3, 4, 7, 8, 9, 11, 14, 15)
using 8:1 mux.
AE Refer Q. 2.8, Page 2-83, Lzit 2.
Q.4. Using a decoder and external gates, design the
combinational circuit defined by the following three
boolean functions :

Ans
F *'yz' *z, F, ay'zr yz', F,=*'y? +*y
= + =

Refer Q. 2.13, Page 2-15B, Unit-2.

+

Q.5. Draw the logic diagram ofa two to four line decoder using
NOR gates only.
Ans. Refer Q. 2.14, Page 2-16B, Unit-2.
Q6. Implement the following Boolean function.
PA, B, C,D) = Z(0, 1,3, 4,7,8,9, 11, 14, 15)
i. 4:1 MUX
ii. 2:1 MUX
Ans Refer Q 2.9, Page 2-9B, Unit-2.
Q7. Design a full adder using two half adders.
AM ReferQ.2.18, Page 2-21B, Unit:2.
Q8. Design a full subtractor eircuit with three inputs x, y, B,
and two outputs Diff and B The circuit subtracts
x-y -B where, B, is the input borrow, B is the output
borrow and Diff is the difference.
Ana Refer Q. 2.21, Page 2-24B, Unit-2.
Q.9. Draw a BCD adder circuit and explain its working.
A& Refer Q. 2.24, Page 2-27B, Unit-2.
Q10. Draw a full subtractor circuit using NAND gate.
Ans Refer Q. 2.22, Page 2-26B, Unit-2.
 3
UNIT
Sequential Logic
Design

CONTENTS
Part-1 Building Block Like S-R Flip Flop.. 3-2B to 3-3B

Part-2: JK and Master-Slave JK FF. ****************** 3-3B to 3-5B

Part-3 Edge Triggered FF. 3-5B to 3-6B

Part-4 State Diagram, State Reduction. - 6 B to 3-16B

Design of Sequential Circuits

Part-5 Ripple and Synchronous Counters..3-16B to 3-24B

Part-6: Shift Registers. *****************************

******** .3-24B to 3-31B

Part-7 Finite State Machines (FSM),.**** ******. 3-31B to 3-33B

Design of Synchronous FSM

Part-8 Algorithmic State Machines. - 3 3 B to 3-35B

(ASM) Charts

Part-g : Designing Synchronous Circuits..3-36B to 3-38B

Like Pulse Train Generator

Part-10: Pseudo Random Binary Sequence 3-38B to 3-398

Generator, Clock Generation
-

3-1B (EC-Sem-3)
3-2B (EC-Sem-3) Sequential Logic Design

PART 1
Building Block Like S-R Flip Flop.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que3.1.What do you mean by flip flop? Explain SR flip-flop.

Answer
Flip-flops:
Flip-flops are binary cells capable of storing one bit of information. A
one for
flip-flop circuit has two outputs, one for the normal value and
the complement value of the bit stored in it.

SR flip-flop:
The circuit diagram and truth table of SR flip-flop are shown in

fig.3.1.1. This is also known as clocked set-reset flip-flop.

The circuit functions when clock puise is active, i.e., 1 otherwise it will

hold its output values (Q and Q).

Input Output
s R
DT-9 0 (Hold)
CLK -
0 (Reset)
0 (Set)
(Invalid)

Pig, 3.1.1. SR Flip-lop

3 It can be observed from the truth-table thM ifS = R = 0 and CLKis active

then the output is sane as previous

IfS= 0 and R = 1, the fip-1lop will be in reset stage, i.e., output Q wil be
0.
5 IfS-1and R =0, the lip-op will be in set stage,ie,outputG will be 1

6 IfS=1and R = 1 then output is invalid ie., Qand Q both willattain

logic I which contradicts the assumption of comple mentary outputs

Que 3.2. Write the difference bet ween latches and flip-nops.
 3-3 B (EC-Sem-3)
Digital System Design

Answer

S.No. Latch Flip-lop

Storage element that Storage elements that are
operate with signal levels controlled by clock transitions.

It is level triggered. It is edge triggered.

3. There is no clock pulse. There is a clock pulse.
4. Circuit diagram Circuit diagram
Latch Flip-Plop
A -Q A-
CLK

PART-2
Jkand Master Slave JK FF.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 3.3, Discuss JK flip-flop with its circuit diagram.

Answer
1. The circuit diagram and truth table of JK 1 -flop is shown in
Fig. 3.3.1.

K a 1
No change
ie. 9,
Reset
CLK
Set
Togsle
Fig. 3.3.1.JKip-op
 3-4B (EC-Sem-3) Sequential Logic Design
2. The previous problem that S =R = l is invalid in SR flip-flop has been
overcome by JK flip-flop.
The working of JK flip-flop is similar to SR flip-flop except that when
J=K=1, the output exists, i.e., when J=K=1, the output is 1 when its
previous output is 0 and 0 if its previous output is 1.
The condition J = K = 1 causes a major problem, i.e., race-around
condition. Consider J=K=1 and Q =0 and a pulse is applied at CLK
input.
After a time interval At equal to propagation delay through two NAND
gates in series. The output will oscillate between 0 and1.
6 At the end of CLK the output is uncertain and the condition is
race-around condition. There are two methods to avoid race-around
condition by using
a. Master Slave JKflip-flop.
b. Edge-triggered fip-lop.

Que 34.Write a short note on master-slave JK flip-flop.

Answer
1. Master-slave combination can be constructed for any type of
adding a gated SR flip-flop. Fig.
flip-flop by
3.4.1 explains the master-slave
of JK flip-flop.
operation

Master Slave
Set ( J -
Clock JDSM JK D SR
pulse.
C Flip-flop Flip-flop
Reset (K)

Fig 341. Master-slave JK lip-ip

It requires two flip-flops where one is gated JK acts as master and other
SR ip-flop acts as slave. Output of slave flip-flop is fed as input to AND
gate of master flip-flop which acts as JK lip-flop.
3. Information present at JK lip-flop is transmitted to output of master
flip-flop on positive level clock and is held there until negative level elock
pulse appears.
4 The truth table 3.4.l follows negative level
triggering. This cascading
avoids race around condition when J and K inputs are having
logic-1
information.
Digital System Design 3-5B (EC-Sem-3)

Table 3.4.1. Characteristics of master and slave JK fip-flop.

Input Outputs Remarks

(Set) K(Reset) Qt+1
0 Q) Previous state|

0 1 Set

Clear (Reset)

1 Toggle state

Let both inputs J and K are 1. Previous outputs of master and slave
flip-flops are y =0 and , =0, respectively.
6. During high level clock pulse, information is transmitted to master
flip-flop because C. 1 for master and slave flip-flop holds previous
0. So output of master flip-flop 1 and
output because C, are

0 and outputs of slave flip-flop are 0 and > 1 .

7. During low level clock pulse, information is transmitted to slave flip-flop
because C. 1 for slave and master flip-f1op holds previous output
1 and 0
because C, 0 . So outputs of master flip-flop are
and outputs of slave fip-flop are , 1 and 0.

information is transmitted to master

8 During next high level clock pulse,
flip-flop because C, 1 for master and slave flip-flop holds previous
output because 0
C, for slave. Input of master flip-flop is
1.1.0 0 and R, KC,Q, » 1.1.11 will reset the
Sy= JC,Q,
=
= »

master flip-flop.
information is transmitted to slave flip-flop
9. During low level clock pulse, Slave flip-flop copies master's
and master flip-flop holds previous output.
around situation is avoided.
output. Hence, race

PART-3
Edge Triggered FF

Questions-Answers

and Medium Answer Type Questions

Long Answer Type
 3-6B (EC-Sem-3)
Sequential Logic Design

Que 3.5. Explain edge triggered flip-flop.

Answer
1. Edge triggered flip-flop synchronizes state change with clock pulse.

Clock pulse-

Data (D)

Fie 3.5.1.D type positive odge triggered

2
ip-op
Output is transmitted at a specific level of clock pulse otherwise
are locked and inputs
flip-flop does not perform operation.
3. The operation is resumed when the clock
pulse level return to zero and
high level pulse occurs.
4. Flip-flop shown in Fig. 3.5.1 is positive edge-triggered flip-flop. Flip-flop
can be negative edge-triggered also.
5. Le Dbe 0 and clock pulse,
C, ->0. NAND-II and NAND-III gates give
outputs R> 1 and S > 1 as one input;
NAND-I and NAND-IV gates are 0 and 1,
C, is 0. Outputs of
not change any state. So, the
respectively. The output will
inputs are locked.

PART-4
State Diagram, State Reduction, Design of
Sequential Circuits.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 88.Discuss theconcept of state equation, state table and

state
diagram in elocked sequential cireuit.
Answer
State equations:
The behavior ofa clocked
sequential circuit can be described algebraically
by means of state
equations.
Digital System Design 3-7B (Ec-Sem-3)
2. A state equation (also called a transition equation) specifies the next
state as a function of the present state and
inputs a set of state equations
for the circuit:
At + 1) = A(tx(t) + B(tx(t)

Bt+1)= A(t)x(t)
3. The present state value of the output can be expressed algebraically
yt) = [A(t) + B(0)] x(t)

4. By removing the symbol (t) for the present state, we obtain the output
boolean equation :

y = (A + B)x
State table:
The time sequence of inputs and flip-flop states can be enumerated in a
statetable (sometimes called a transition table). The state table for the
circuit of Fig. 3.6.1 is shown in Table 3.6.1.
2. The Table 3.6.1 consists of four sections labeled present state, input,
next state, and output. The present state section shows the states of
flip-flops A and B at any given time t.
3. The input section gives a value ofx for each possible present state. The
next state section shows the states of the flip-flops one clock cycle later,
attime (t+1).
4. The output section gives the value of y at time t for each present state
and input condition.
5. The next state of flip-flop A must satisfy the state equation
At + 1) = Ax + Bx

Table 3.6.1
Present state Input Next state Output
A B A B

6. The next state of flip-flop B is derived from the state equation

Bt+1)= Ar
3-8 B (EC-Sem-3) Sequential Logic Design
7 The output column is derived from the output equation
y = Ax B x
State diagram:
1. The information available in a state table can be represented graphically
in the form of a state diagram.
2 In this type of diagram, a state is represented by a circle, and the
(clock-triggered) transitions between states are indicated by directed
lines connecting the circles.
Table 3.6.2.

Present state
Nextstate Output
0 * 0

0
AB 0
1 1
0 0 0 0
0

o/0 0/1

(00 (10)
O/1
1/0 0/1 1/0

1/0

Fl, 3.6.1.State diagram of the eireuit

3. The state diagram provides the same information as the state table and
is obtained directly from Table 3.6.1 or Table 3.6.2.

Que 3.7, Design the clocked sequential eireuit for the following
state diagram using JK nip-lop.

00

(10

Fig 3.7.1.

AKTU 2015-16, Marks 15

Digital System Design 3-9B (EC-Sem-3)

Answer
The state table for the given state diagram is (Moore model):

| Input Present state Next state Flip-lop inputs

0 0
0 0
0

0
0 1

Columns of J,, K, J, K, are filled by the help of excitation table of JK

flip-flop.
Excitation table of JK Aip-lop:
Present state Next state

1
1

K-maps for J, K, J, and K, are:

For For K1
00 01 11 10 00 01 11

J = X Qo K = x Qo

For J For K
Q1o
00 01 11 10 01 11 10
00
of
Fig. 3.7.2. K =x Q1+xQ
The boolean expressions for J , K, and K, are:
3-10B (EC-Sem-3) Sequential Logic Design

K, = xQ,

CLK
Jo

Fig. 3.7.3.

Que 3.8. Derive the state table and state diagram for the
sequential circuit shown in Fig. 3.8.1.

CLK

B
Fig. 3.8.1.

AKTU 2015-16, Marks 10

Answer
1. Type of circuit :
The output y of the sequential circuit depends on present statee only, so
the given logic circuit is the Moore type circuit.
2. Excitation equations

For fip-flopA: J, =B
For flip-lop B: J, =

K, =
A Dr
Digital System Design 3-11 B (EC-Sem-3)

For output y: y = A B

3. We know that characteristics equation of JK flip-flop :

A J+KQ,
4. State equation for flip-flop A:
A BA +(Bx) A (Q =A)
= BA+ AB + x)

= B AB+ xA
An (A DB)+ xA
5 State equation for flip-flop B:
B TB+ (A x)B ( : , BB)
= TB+ (Ar + A7) B
B B+ AxB +ArB
State table:
Presen tat Next state Output
|*«0 *=11
AB AB AB
00 01 0
01 10
10 11 10
11 00

State diagram:

D0- State
Output

10

Fig. 8.8.2.

Que 39.What do you understand by state reduction ? Reduce

the state diagrum shown in Fig. 3.9.1.
3-12B (EC-Sem-3)
Sequential Logic Design
O/0

o/0/ 0/0

1/0 1/0

0/0
1/1
O/0

Fig. 3.9.1.

AKTU 2015-16, Marlks 10

OR
Draw the reduced state table and reduced state
diagram for the
state table given in Fig. 3.9.1.
AKTU 2016-19, Marks 07
Answer
State reduction
1. Any logic design process must consider the problem of
cost of the final minimizing the
circuit. One way to reduce the cost is, by
reducing the
number of lip-flops, i.e., by reducing the number of states.
2 The state reduction technique basically avoids the introduction of
redundant equivalent states. The reduction of redundant states
reduces
the number of flip-flops and logic
cost of the final circuit.
gates thus required, reducing the

3. Two states are said to be

redundant or equivalent, if every possible set
of inputs generate exactly the same outputs and the same next states.
4. When two states are
equivalent one of them can be removed without
altering input-output relationship.
Numerical:
1. The given Fig. 3.9.1 has seven states, one input and one output. The
given state diagram is converted to state table.
2. From the state table, it is clear that statese
state g is replaced by state e.
and g are
equivalent. So the
Digital System Design 3-13B (EC-Sem-3)

State table:
Present state Next state Output
-0 1 0 x=1

Both are equivalent

e states because of
state e andg having
state and
- - -
Same next
same output.

Reducing the state table :

Present state Next state Output

0 1 01

C 0 0

Both are 1
equivalent
states

3. From the reduced table, states d and fare equivalent, hence fcan be

replaced by d and it can be removed.

Reduced table:
Present State Next state Output
a=0 = 1 = 0 =1

0 0
d d 1
d

The state diagram of the reduced state table is shown in Fig. 3.9.2.
.
3-14B (EC-Sem-3)
Sequential Logic Design

O/0 o
10
oo O/0
1/0
1/1
1/0

Fig 3.9.2. tate diagram

Que 3.10. Derive the state table and state diagram for the
sequential cireuit is shown in Fig. 3.10.1.

AKTU 2018-19, Marks 07

A_-A

P B
QB B
Cp
Fig. 8.10.1
Answer

1. The behaviour of circuit is determined

by the following Boolean
expression,
Y= AB +T ..(3.10.1)
D = Ax + Bx ...3.10.2)
D = Ax
.(3.10.3)
2. From eq. (3.10.1), (3.10.2) and (3.10.3) then state table will be
Table 3.10.1.
Present State Next state Output
B *=0 *=1 0
0 0 0 0

00 1

0 1 0 1
Digital System Design 3-15B (EC-Sem-3)

3. We draw state diagram with the help of state table

0/1 o/1
01

1/0
Fig. 3.10.2

Que 3.11 Derive the etate table and state diagram of the
synchronous sequential circuit shown below (X is aninputto the
cireuit). Explain the circuit function. AKTU 2017-18, Marks 07
B

x CLK
B

D
CLK CLK
Fig. 3.11.11
Answer
1. From the circuit shown in Fig. 3.11.1, the output equation can be
obtained as,
At + 1) = (BX + BX)+ A
B(t +1) = (AX + AX) + B

2. The state table for the circuit shown in Fig. 3.11.1.

Present state Input Next state
At+1) Bt+1)
0
0
0

1
1 0
0
1
3-16B (EC-Sem-3) Sequential Logic Design
3. State diagram

10
Fig. 3.112.

PART-S
Ripple and Synchronous Counters.

Questions-Answers
Long Answer 1ype and Medium Answer Type Questions

Que 3.12. Design a 3-bit up/down ripple counter.

AKTU 2017-18, Marks 07

Answer
1. The 3-bit up/down
ripple counter, which can count in upward direction
of sequence from 000, 001, 010,
011, 100, 101, 110, 111 and downward
direction of sequence from 111, 110, 101, 100, 011, 010, 001, 000.
2. 3-bit counter consists of 3
flip-flops. In ripple counter, a flip-flop output
transition serves as a source for triggering other
flip-flops.
3 The control signal M is used to select the
direction of count sequence.
Fig. 3.12.1 shows the 3-bit ripple.
M=1, counter acts as up-counter
M 0; counter acts as down counter
M
Logic I Logic 1
Logie 1

CLK H
f.© DFET

FMg. 8.12.1. 3-bit ripple up-down.

Digital System Design 3-17B (Ec-Sem-3)

Que 3.13.Draw the logic diagram of a 4-bit binary counter with

parallel load.

Answer
1. The operation of the counter is summarized in Table 3.13.1. The four
control inputs-Clear, CLK, load, and count, determine the next state.
The clear input is asynchronous and when equal to 0, causes the counter
to be cleared regardless of the presence of clock pulses or other inputs.
Table 3.13.1.

Clear CLK Load Count Function

Clear to 0
Load inputs
Count next binary state
No change
The logic diagram for 4-bit binary counter with parallel load is shown in
Fig. 3.13.1.
Count

Load--

1-
A

D
A2

=D
Ag

Clear
CLK

Fig. 3.18.
D out
3-18B (EC-Sem-3) Sequential Logic Design

Que3.14. Draw diagram of a 4-bit binary ripple down counter

using flip-flops that trigger on negative edge transition. Also draw
a timing diagram of the counter.
OR
Design a ripple decade counter using JK flip-flop.

AKTU 2018-19, Marks 3.5

Answer
4-bit binary ripple down counter:
1 The 4-bit asynchronous counter is constructed by using JK flip-flop
(asynchronous counter are also called ripple counter).
2. The output must be externally connected to clock input offip-flop B.
3. The input count pulses are applied to clock input of flip-flop A.
divisions
Simultaneous of2,
4, 8, and 16 are performed at the
ec outputs.
Timing diagram :

CLK 0 1 2345 6 7 8 9 10 111213 14 15

Ac

Fig. 3.14.1.

Logic diagram:
M

Hign

L Fig. 3.14.2,

4-bit ripple counter needs 4 flip-flop. To work in down mode M should

he high.
Digital System Design 3-19B (EC-Sem-3)

for the
Que 3.15. Design a synchronous counter using JK flip-flop
following input sequences:

AB C

Fig. 3.16.1.

Answer
Present Next Flip-Flop inputs
State state

KJ K
x

0 0 X

0
0
1 1 0
1
1

K-maps:
For JA For SA

00 01 11
Q 00 01

JA=Q
3-20B (C-Sem-3) Sequential Logic Design

For For Kg

A 0 0 01 1 10 A00 01 11 10
2

c For«
QpQc For Kc
A 0 0 01 11 10 A 0 01 11

Jc Ko=1
Flip-lop required are: 2"2N
Here N= 6
So, n =3, i.e., three flip-flops are required.

CLK
Fig 3.15.2.Synchronous counter using JK lip-lop
ue 3.16.1 Design a 3-bit asynchronous up-down counter using

Tlip-nop. AKYWU 2016-16, Marks 7.5

Anewer
The number of flip-flop to be used is three. We shall use three toggle
flip-flop. Let, up counting takes place with M = 0 and down counting
take place for M = 1.

2. First, we write the cireuit excitation table.

 3-21 B (EC-Sem-3)
Digital System Design
counter
Table 3.16.1: Excitation table for a3-bit up/down synchronous
Mode Present state Next state Flip-flop inputs
control M ,
0
0 0
0
0 1 1
1
0 0 1
0 0
1
0 1
0
1 1 1
0 1 0
1
0
0
1

For Tc For Ts
QpA
MQc 00 01 11 10 MGc00 01 11 10
0o l11

11 1015014

1
To= MQ QA + MQp QA TB MQA+QM

For TA
MQ 00 01 11 10

01

10
TAI
3-22 B (EC-Sem-3)
Sequential Logic Design
4. Finally, let us draw the logic diagram.
Mode
control M =0 for up
(M) M =1 for down countingB
counting
Logic 1
MQAB

CLK MQAB

Fig. 3.16.1. Logic diagram of a 3-bit synchronous up/down

counter
Que 3.17.Design a 3-bit synchronous counter using JK flip-flops.
Answer
3-bit synchronous counter:
For a 3-bit synchronous counter
usingK flip-flop, we need 3 flip-tlops.
Excitation table and state diagram of JK flip-flop
Present Next Flip-flop
state state inputs
1
0

Excitation table of JK flip-flop State diagram.

Fig. S.17.1.
Excitation table for 3-bit synchronous counter:
Table 3.17.1: Circuit excitation table

Present state Next state Flip-flop inputs

1 0x 0 x
0 0 1 1 0 0 1
1 0 x

0
0 x o
0

0 0
 3-23 B (EC-Sem-3)
Digital System Design
all flip-flop inputs
K-maps and simplified expressions for
For For Kc
00 01 11 10 Qc 00 01 11 10

K Qa
For KB
QpAFor
Qc00 01 1110 00 01.11 10

y=a

For JA For Ka

c00 01 11 10 Qc 00 01 11 1 0

Ba=1
A=1
Thus the simplified equations are

Jc =QA
Jp =
J =1 Ka
Logicdiagram: 3-bit synchronous counter using
shows the
Fig. 3.17.2 logic diagram of a
JK lip-flops.

Logic 1 QA
J K-A
JA K1
FF-A FF-B FF-C

CLK
JK FFs.
Fig. 3.17.2. 3-bit synchronous counter using
3-24 B (EC-Sem-3)
Sequential Logic Design

Que 8.18. Describe the operation of four bit synchronous binary

counter with neat sketch.
AKTU 2016-17, Marks 10
Answer
The C inputs of all flip-flops are connected to a common clock. The
counter is enabled by count enable.

2. If the enable input is 0, all J and K inputs are equal to 0 and the clock
does not change the state of the counter.

3. The first stage A, has its J andKequal to 1 if the counter is enabled.

The other Jand Kinputs are equal to 1 ifall previous least
significant
stages are equal to 1 and the count is enabled.
4. The chain of AND gates generates the required logic for the J and KK
inputs in each stage.
5. The counter can be extended to any number of stages, with each stage
having an additional flip-flop and an AND gate that gives an output of
1 ifall previous flip-flop outputs are 1.

Ap
Count enable

A
K

A2

Ag

- T o next stage
CLK

ig3.18.1 Pour-bit gynchronous binary counter

PART-6
Shift Registers
 3-25 B (EC-Sem-3)
Digital System Designm

Questions-Answers

Long Answer Type and Medium

Answer Type Questions

Que 8.18. Write down the classification of shift registers.

OR
What do you mean by shift register ? What is the need of shift
register ? Draw and explain bidirectional shift register.

AKTU2018-19, Marks07
Answer
Shift registers:
The binary data in a register can be moved within the register from one

flip-flop to the otheroutside it with application of clock pulses. The

or
registers that allow such data transfers are called shift registers.
Need of aregister:A register is a sequential logic circuit with two basic
functions:
Temporary storage.
i Shifting capability.
Classification of shift registers
Classification based on the direction of data movement:
i Shift left register.
i. Shift right register.
ii. Bidirectional shift registers.
2. Classification based on the mode ofinput and output:
Serial in serial out shift register (SISO)
ii. Serial in parallel out shift register (SIPO)
i Parallel in serinl out shift register (PISO)
iv. Parallel in parallel out shift register (PIPO)
v. Universal shift register.
Biarectional shift register:
1. It consists of four D flip-flops, four OR gates, eight AND gates and one
NOT gate as shown in Fig. 3.19.1.
 3-26B (EC-Sem-3)
Sequential Logic Design
M

CLK-
D3 D 2
D
Fig. 3.19.1
Operation:
When mode control M =
1, all the A AND gates
enabled and the data at (A,y A Ay A,) are
D, is shifted to the right when clock pulses are
applied.
When M 0, all A gates are disabled and all B
=

enabled B gates allow data

gates are enabled. These
M should be changed
D, to be shifted to left.
only when CLK 0, otherwise the data stored in
=

the register may be changed.

Que 320. Write a short note on different types
of shift register.
OR
Draw and explain the PIS0, PIPO register.

AKTU 2017-18, Marks 07

Answer
Serial in serial out shift register (SISO):
The serial in serial out shift
input line.
register accepts the data serially ona single
2. It also produces the
stored information on its
can shift the data from output in serial form. We
left side or right side.
3. Based on the shifting of
data, the register is called shift left or shift
register. Fig. 3.20.1 shows the block diagram of serial right
in serial out shift
register (SIsO).
Serial
in
Serial Serial F
(a) Shift right
0ut Serial
(6) Shift left
Fig. 8.20.1. 4-bit serial in serial out shilt
register
Shift right register
1. In this register while accepting data serially, the group
towards the right side. of bits is shifted
Digital System Design 3-27B (EC-Sem-3)

Hence the serial data is entered onto the left side of register and it
leaves from the right side serially. Fig. 3.20.2 shows the logic circuit for
a 4-bit shift right register.

Do
Dout

CLK
Fig. 3.20.2. Logic circuit for a 4-bit shift right register
Shift left register:
The group of bits is shifted towards the left side in serial form. Hence the
serial data is entered from right and the binary data at the output is
taken from the left most flip-flop.
2. Fig. 3.20.3 shows the logic circuit for a 4-bit shift left register.
FF3 FF FF
DD D D

CLK
Fig. 3.20.3. Logie circuit for a 4-bit shift left register

3. The binary data is entered into right most flip-flop (FF,) and output is
taken from the left most flip-flop (PF) in serial form.
Serial in parallel out shift register:
This is one type of shift register in which the data is entered in serial
form and output is in parallel form.
2. Hence, it is necessary to have all the data bits available as outputs at the
same time.
3. This type of shift register operation is same as the serial in serial out
shift register.
4. The difference between serial out and parallel out shift registers is the
way in which the data bits are taken out of the register.
5. Fig. 3.20.4 shows the block diagram of 4-bit serial in parallel out shift
register.
Parallel out
Serial in
| O
Fig. 8.204 Block diagram of 4-bit serial in parallel out shift register
5. Fig. 3.20.5 shows the logic eircuit for 4-bit serial-in parallel out shift
register.
3-28 B (EC-Sem-3)
Sequential Logic Design

D2
Dout

CLK
Fig. 3.20.5. Logic circuit for 4-bit serial in parallel out shift register.
Parallel in serial out shift register:
1 Fig. 3.20.6 shows the block diagram of a parallel in serial out shift register.
In this type, the bits are entered in
parallel, i.e., simultaneously into
their respective stages on a parallel line.
2. It produces the stored information on its output, in serial form.

Parallel in

Serial out

Fig. 3.20.6.Parallel in serial out shift register

Parallel in parallel out shift register:
All the data appear simultaneously along with all the flip-flop inputs and
outputs.
2. Fig. 3.20.7 shows the logic diagram for 4-bit parallel in parallel out shift
register.
Parallel outputs

D Do Qo

CLK-
B
A
Parallel inputs
Fig, 8.20.7. Logie diagram for 4-bit parallol in parallel out shit register

Que 821 With the help of diagram, explain the operation of

universal shift register.
AKTU 2014-15, Marks 06
Digital System Design 3-29 B (Ec-Sem-3)

OR
Draw and explain 4-bit universal shift register.

AKTU 2016-16, Marke 10

OR
Design a universal shift register that performs HOLD, SHIFT RIGHT,
SHIFT LEFT, and LOAD. AKTU 2017-18, Marks 07
Answer
1. A shift register that can shift the data in both the directions (shift right
or left) as well as load it parallely, it is called as a universal shift register.
2. This shift register is capable of performing the following operations :
Parallel loading (parallel input parallel output).
Left shifting. ii. Right shifting.
3 The block diagram of a 4-bit universal shift register is shown in
Fig. 3.21.1. It consists of four D flip-flop and four 4: 1 multiplexers.
The four multiplexers have two common select lines S, and So. Input 1,
in each multiplexer is selected when S,S% = 00, input I, is selected
when S,S = 01 and so
on.
5. The selection inputs (S,S) control the mode of operation ofthe register
according to the function table shown in table 3.21.1.
Parallel output

Clear- FF FF3 FF
LA D
CLK

4x1 MUX 4x1 MUX 4x1 MUX

H4x1 MUX
Serial.
input
for shift Serial
input
right for shift
Parallel inputs
left
Fig 3.21.1. Block diagram of 4-bit univorsal shift rogister
Table 3.21.1. Punction table

Function
S, 0 Hold
Shift right
Shift left
Load
3-30B (EC-Sem-3)
Sequential Logic Design
Operation:
When S,S, 00, the present value of the
=
register is applied to the D
inputs of the flip-flops. This condition forms a path from the output of
each flip-flop to the binary value input of the same flip-flop.
2. The next clock edge transfers into each flip-flop the binary value it
held
previously and no change of state occurs.
3. When S,S, 01, the input
=

I, of the multiplexer has a path to the D

inputs of the flip-flops. This causes a shift right operation, with the
serial input transferred in flip-flop FF4
. When S,S, =
10, a shift left operation results, with
the other serial
input going into flip-flop FF,. n this case, Input I, of each multiplexer
is connected to the output of each flip-flop. The data bit is shifted to left
side for every clock.
. When S,S, = 11, the binary information on the parallel input lines is
transferred into the register simultaneously during the next clock edge.

Que 3.22. What are the applications of shift register ?

Answer 1
i. Time delay: The serial out shift register can be used to provide a time
delay from input to output that is a function of both the number of
stages (n) in the register and the clock frequency.
ii. Serial to parallel data converter: Serial data transmission from one
digital system to another is commonly used to reduce the number of
wires s in t transmission line. \ can convert the received serial data
to parallel data by using serial in parallel out shift register.
ii. Parallel toserial data converter: Serial data transmission requires
3 stream of serial data to be transferred from one digital system to
another. We can convert the parallel data to serial data by using parallel
in serial out shift register.

Que 3.23. Design a 4-bit serial in serial out shift register using JK
flip-flop.
Answer
Serial in-serial out shift register using JK flip-flopp:

Serial
in (D) 9 Serial
out

CLK-
Fig. 3.28.1
 Digital System Design 3-31 B (EC-Sem-3)

Conversion table and K-map

For J ForK

D, 0
K DD D

J= D K= D

PART7
Finite State Machines (FSM), Design of Synchronous FSM.

Questions-Answers
Long Answer Typeand Medium Answer Type Questions

Que 3.24. Explain Moore type of synchronous sequential machine

FSM) using block diagram and suitable example.

Answet
1. When the output of the sequential network depends only on the present
state of the flip-flop, the sequential network is referred to as Moore
model.

2. Fig. 3.24.1 shows a sequential network which consists of two JK flip-flop

and AND gates.

CP

Fig. 3.241 Example of Moore model

3. The network has one input X and one output Y.
4. As shown in the Fig. 3.24.2, input is used to determine the inputs of the
flip-flops
5. It is not used to determine the output.
6. The output is derived using only present states of the flip-flops or
combination ofit (in this case Q, ,).
3-32 B (Ec-Sem-3) Sequential Logic Design
7. In general form the Moore model can be represented with its block
schematic as shown in Fig. 3.24.2 (a) and (b).
8. In the Moore model, as output depends only on present state of the
tip-tlops,it appears only after the clock pulse is applied, i.e., it varies in
synchronism with the clock input.

Inputs Next Memory

state elements Outputs
decoder

(a) Moore model.

Next Output
Inputs state Memory decoder Outputs
decoder elements| (combinational
circuit)

(b) Moore circuit model with an output decoder.

Fig. 3.24.2.

Que 3.25.
Explain Mealy model.
Answer
1. When the output of the sequential network depends on both the present
state of flip-flop(s) and on the inputís), the sequential eireuit is referred
to as Mealy model.
2. Fig. 3.25.1 shows the sample Mealy model.

CP

Fig. 3.26.1. Example of Mealy model

 3-33 B (EC-Sem-3)
Digital System Design
derived from the
3. As shown in the Fig. 3.25.1, the output of the circuit is
of present state of flip-flops and input() of the
circuit.
combination
Looking at Fig. 3.25.1, we can easily realize that, changes in the input
within the clock pulses cannot affect the state of the flip-flop. However,
they canaffect the output of the circuit.
If the input variations are not synchronized with the clock, the derived
w e get false
output will also not be synchronized with the clock and
network).
output (as it is synchronous sequential
The false outputs can be eliminated by allowing input to change only at
6.
the active transition of the clock (in our example HIGH-to-LOW).
7. In general form the Mealy model can be represented with its block
schematic as shown in Fig. 3.25.2.

Output
decoder Outputs
Inputs Next
state Memory
decoder |elements

Fig. 3.25.2.Mealy circuit model

PART8
Algorithmic State Machines (ASM) Charts.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 3.26. What is ASM chart ? Explain. Draw the state diagram,
state table and ASM chart for a D flip-flop.

Answer
ASM chart is composed of three basic elements : State box, decision box
and conditional box.
3-34B (EC-Sem-3)
Sequential Logic Design
State box: The state
of the system is indicated by a state box. The shape
of the state box is a rectangle.
General description entry
State name Binary code
Register operation or
unconditional list

Exit
Fg. 326.1.
Decision box: It is a diamond shaped box used to describe the effect of
an input on the control subsystem.
Entry

VP
condition

Exit path 1 Exit path2

Fig. 9.26.2
Conditional box: It is a unique box of ASM chart. The area shape of
the conditional box is showa in Fig. 3.26.3. The round corners
differentiate it from the state box.
Entry path from decision box

Conditional register
operation l output

Exit
Pig. 3.26.3.
To draw ASM chart, first we form a state table for easy understanding of
the operation of the given circuit.

Dp

CLK
Fig. 3.26.4.
 3-35 B (Ec-Sem-3)
Digital System Desigm
State table:

Present Nextstate, output

state 0 X=1

0
0

State diagram:

1/
00 0o/1
1/y
O/0
(11 0 1 o1
1/1

O/0

Fig 8.26.5

ASM chart
So 00

Z=1

S
Z=1

2-1 2=0
10
S,
0

Fig. 3.26.6.
3-36B (EC-Sem-3) Sequential Logic Design

PART-9
Designing Synchronous Circuits Like Pulse Train Generator

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 3.27 Generate the following pulse train using indirect logic.

Answer
1. The given sequence is 10110. It is written vertically under the column
heading output () in the truth table of Fig. 3.27.1(a).
2. It is 5 bits long, so we need five unique states to generate pulse train so,
any mod-5 counter can be used.
3. For simplicity, we use a ripple counter.
4. It goes through states 0, 1, 2, 3, 4, 0.. States 5, 6,7 are invalid, so the
corresponding outputs arc don't cares.
5. The K-nmap for the output 1 in terms of the outputs of the flip-dops, its
minimization, and the minimal expression obtained from it are shown in
Fig. 3.27.1.
6. The logic diagram (using a mod 5ripple counter) based on that minimal
expression for fis shown in Fig. 3.27.2.
7. While at state 0, it output a 1, ie., the first bit of the sequence.
8. While at state 1, it outputs a0; ie., the second bit of the sequence, and so
on.

Output (0 States
0
2
3

5
0

(a) Truth table.

 3-37B (EC-Sem-3)
Digital System Design

00 011 1 10

Output, f= Q2+1
(b) K-maP tor
Fig. 3.27.1. Pulse train generator

1 102 10
oPF

Fig 3.27.2. Logic diagram of the pulse train generator

9ue 3.28. Design a pulse generator using indirect logic to produce

the following waveforms.

o 10 0T 10 o o
oT I11110o
Answer
1. The pulse trains to begenerated written vertically under column heading
f and fp in the truth table 3.28.1(a) are (a) 100 11000 and (b)
of Fig.
11111100.
2. These are both eight bits long
3. So we need eight unique states to generate those two pulse trains.
4. Therefore, a mod-8, ie., a 3-bit ripple counter can be used.
5. Letf and f2 be the outputs of the combinational circuits.
6 The state assignment is shown in the truth table.
7. The K-map for outputsf and f, in terms of the outputs of the tlip-flops,
their minimization and the minimal expressions obtained from them
are shown in Fig. 3.28.1(b).
8. The logic diagram (using a mod-8 ripple counter) based on those minimal
expressions for / and f, is shown in Fig. 3.28.2.
3-38 B (Ec-Sem-3)
Sequential Logic Design
States Q, Q, f1 f2
0 0 0 0 11 *3 00 01 11 10 a00 01 11 10
0 0 1 0 1
I 0 0 1
3 0 1 1 11
4 0 1
01 0 1
6 0 0 0 =9+,9,
1
(a) (b)
Fig. 3.28.1. Truth lable and Komaps for f, and f

1 1 2
o FF FF2 tPF
CLK LK,

82. Logic diagram of the pulse train generator

PART 10
Pseudo Random Binary Sequence (PRBS) Generator,
Clock Generation.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 828Write a short note on PSBR generator.

Answer
1 Another important application of shift register is a Pseudo-Random
Binary Sequence (PSBR) generator. Here, suitable feedback is used to
generate pseudo-random sequence.
2. The term random here means that the outputs do not cycle through a
normal binary count sequence.
3. The term pseudo here refers to the fact that the sequence is not truly
random because it does cycle through all possible combinations once
every 2"-1 clock cycles, where n represents the number of shift register
stages (number of flip-flops).
Digital System Design 3-39 B (EC-Sem-3)

Que 3.30. Explain clock generator.

Answer
1. The clock generator is a circuit that produces a timing signal for
synchronization of the circuit's operation.
2. Examples of clock generators used in microprocessor systems include
8284 and 82284. 8284 generates the system clock for the 8086 and 8088
processors.
3. It requires a crystal or a TTL signal source for producing clock waveforms.
It provides local READY and MULTIBUS READY synchronization.
82284 is a clock generator/driver that provides clock signals for the
80286 processor and support components.
5. It aiso contains logic to supply READY to the CPU from either
asynchronous or synchronous sources and synchronous RESET from
an asynchronous input with hysteresis.
6. The 82284 is packaged in 18-pin DIP and contains a crystal-controlled
ocillator, an MOS clock
generator, a peripheral clock generator, multibus
ready synchronization logic and system reset generation logic.

VERY IMPORTANT QUESTIONS

Following questions are very important. These quuestions
may be asked in your SESSIONALS as wellas
TVERSITY EXAMINATION

Q1. Design the clocked sequential cireuit for the following state
diagram using JK flip-flop.

00

10
Fig. .

Refer Q.3.7, Page 3-8B, Unit-3.

Q.2. Derive the state table and state diagram for the sequential
circuit is shown in Fig. 2.
3-40 B (EC-Sem-3) Sequential Logic Design

-
B
DB -B
-B
Cp
Fig. 2.
ARS: ReferQ.3.10, Page 3-14B, Unit-3.
Q3. Draw the reduced state table and reduced state diagram
for the state table given in Fig. 3.
O/0

1/0
0/0
O/0
1/0 1/0

0/0
1/1
O/0

Fig. 3.
Ana Refer Q. 3.9, Page 3-11B, Unit-3.
Q.4. Design a ripple decade counter using JK flip-flop.
AS Refer .3.14, Page 3-18B, Unit-3.
5 . Describe the operation of four bit synchronous binary
counter with neat sketch.
a n Refer Q. 3.18, Page 3-24B, Unit-3.
96. Write down the classification of shift registers.
Kns: Refer Q. 3.19, Page 3-25B, Unit-3.
7 . Draw and explain 4-bit universal shift register.
e Refer Q.3.21, Page 3-28B, Unit-3.
4 UNIT
Logic Families and
Semiconductor
Memories

CONTENTS
Part-1 TTL NAND Gate, Specifications. -2B to 4-3B

Part-2 : Noise Margin...

*************************************** 4-3B to 4-4B

Part-3 :Propagation Delay . ************************************

.. 4 4 B to 4-5B

.. 4-5B to 4-6B
Part-4 Fan-in, Fan-out. u********* ***************

Part-5 : Tristate TTL. .... 4-6B to 4-9B

*************************************

.4-9B to 4-11B
Part-6 : E C*************************************************************
L.

Part-7 : CMOS Families and. ************ 4-11B to 4-17B

Their Interfacing

Part-8:Memory Elements, Concept of .4-183 to 4-20B

Programmable Logic Devices
Like FPGGA

Part-9 : Logic Implementoation using ********* .4-20B to 4-31B8

Programmable Devices

4-1B (EC-Sem-3)
 4-2B (EC-Sem-3) Logic Pamilies & Semiconductor Memories

PART-1
TTL NAND Gate, Specifications.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 4.1.Describe the construction and operation of TTL NAND

gate.
OR
Draw and explain the operation of a TTL NAND gate.

AKTU 2017-18, Marks 07

Answer
1. The circuit of the two-input TTL NAND gate is shown in Fig. 4.1.1. The
input transistor, 9, ís a multiple emitter transistor.

R 130 Q I
RB4 k
C2
TTL
multiple
emitter
VDr
B

APAD
1 k

Fig. 4.1.1.TTL NAND gates

2. Transistor Q, is called the phase splitter. Emitter of transistor, Q,is
connected to collector of transistor, Q, through diode D
3. Transistors Q and Q4 form a totem-pole arrangement. Diodes, D and
D protect transistor, 4, from being damaged by the negative spikes of
voltages at the inputs.
4. When negative spikes appear at the input terminals, the diodes conduet
and bypass the spikes to ground.
Digital System Design 4-3 B (ECSem-3)

Diode Dr ensures that transistors, 3 and Q4 do not conduct

simultaneously. Transistor, Q, acts as an emitter follower.

1.
Operation:
A LOW voltage at either emitter E, or emitter E, forward-biases the

corresponding diode D, or D, and reverse-biases diode Dg which is a

base-collector junction of transistor .There is no flow of current from

base to collector oftransistor

ALOW voltage on both emitters of transistor , does the same action.
AHIGHvoltage on both emitters reverse-bias both input diodes D, and D, and
forward bias Dg. The current flows from base to collector of transistor .
Base, B

Diode, D Diode, Da
Emitter, E -
Collector, C
Diode, D2
Bmitter, E, K
Fig. 4.1.2.Diode equivalent of TTL multiple emitters
Table 4.1.1. Operationof TTL NAND gate
Inputs Transistors Output
Emitterjunction, A Emitter junction, B
Forward bias(ON) Forward bias(ON) OFF
Forward bias (ON) Reverse bias (OFF)
OFF ON
FF |OFF ON 1
Reversebias(OFF) Forward bias(ON) OFF | OFF |ON1
Reverse bias (OFF) Reverse bias(OFF)ONON OFF 0
PART-2
Noise Margin.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 42What do you understand by noise margin of logie

circuit ? Explain with an example.

Answer
The noise immunity of a logic cireuit refers to the circuit's ability to
tolerate noise voltages at its inputs. A quantitative measure of noise
immunity is called noise margin.
44B (EC-Sem-3) Logic Families & Semiconductor Memories
2. Noise margin represents the maximum noise signal that can be added to
the input signal of a digital circuit without causing an undesirable change
in the circuit output.
3. Noise margin can be HIGH state noise margin or LOW state noise margin.
HIGH state noise margin (NMH)is, VNH =VOHVIH
LOW state noise margin (NM,) is, VNL VIL- VoL
=

High state noise margin is the difference between the lowest possible
high output and the minimum input voltage required for a HIGH. Low
state noise margin is the difference between the largest possible LOW
and the maximum input voltage for a
5.
output
Consider
LOW.
an example of a TTLAND gate. The TTL gate has VOH 2.4V,
VoL=0.4 V, VIH =2V and VIL =0.8 V. The noise introduced in the signal
(NH Or VNz) is shown in Fig. 4.2.1.
OL 0.4 V_ IL 0.8V
Logic 0 Noise
OL 0.4 V
Logic 0
Logic 0

Fig 42.1
6. Let the inputs of gate, G, cause output as logic 0. This output acts as
input for gate, G2. Due to noise, actual input given to gate, G, is

7. the
NLVIL-VoL ..(4.2.1)
Let inputs ofgate, G, cause output logic1as in Fig.
4.2.2. This output
acts as input for gate, G2. Due to noise, actual input given to gate, G, is

NHVOH -VIH ..,4.2.2)

OH 2.4 V IH 2.0 V
Logic 1
Logic1 G) : Noise
OL 0.4V

Logic 0
Fi 42.2
VIH in eq. (4.2.2) that acts as input to gate G2. Minimum high level noise
level is
NH2.4 V- 2.0 V= 0.4 V

| PART-3
Propagation Delay.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 4.3.Write a short note on propagation delay.

 4-5B (EC-Sem-3)
Digital System Design

Answer
1. Propagation delay is defined as the time interval between changes in a defined
logic level input and reflection of its effect at the output logic level.
2. The propagation delay for an integrated circuit (IC) logic gate may
differ for each of the inputs. If all other factors are held constant, the
average propagation delay in a logic gate IC increases as the complexity
of the internal circuitry increases.

PART-4
Fan-in, Fan-out.

Questions-AnswersS
Long Answer Type and Medium Answer Type Questions

Que 4.4 Describe the fan-out and fan-in condition of the digital

logic gate.
Answer
Fan-out
The fan-out of a logic gate is defined as the maximum number of standard
load that the output of the gate can drive without impairing its normal
operation. Fan-out is also called the loading factor.
2. HIGH state fan-out is the fan-out of the gate when its output is logic 1.
LOW state fan-out is the fan-out of the gate when its output is logic 0.
The smaller of these two numbers is taken as the actual fan-out.
3. High state fan-out is given by
HIGH state fan-out = OH
IH
where, IoH is the maximum current that the driver gate can source
when it is in a 1 state. IIn is the current drawn by each driven gate from
the driver gate.
4. Similarly, low state fan-out is given by
OL
LOWstate fan-out =

where, oLiS the maximum current that the driver gate can sink when
its output is a logic 0. I is the current drawn from each driven gate by
the driver gate.
5. The fan-out of a logic family can be calculated a s

Fan-out = minimum ofo o

4-6B (EC-Sem-3) Logic Families & Semiconductor Memories
Fan-in:
The fan-in of a digital logic gate refers to the number of inputs. For
1 fan-in
example, an inverter has a fan-in of 1, a 2-input NOR gate has a

of 2, a 4-input NAND gate has a fan-in of 4 and so on.

2. Alogic designer has to select the fan-in of the gate to accommodate the

number of inputs.
3. At the hardware level, however, the fan-in provides information about
the intrinsic speed of the gate itself.
In general, the propagation delay increases with the fan-in. This means
that 2-input NAND gate is faster than the 4-input NAND if both are
from same logic family.

PART 5
Tristate TTL

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 4.5. Describe the construction and operation of TITL inverter

gate (NOT gate).
Answer
1. Fig. 4.5.1 shows a standard TTL circuit for an inverter.Transistor, i s
the input coupling transistor, and D, is the input clamp diode. Transistor,
Q, is called a phase splitter, and the combination of Q, and , forms the
output circuit often referred to as a totem-pole arrangement.
cc
130 n
o1.6

YDr

D
RE

Fig. 45.1. TTL inverter gates

 Digital System Design 4-7B (EC-Sem-3)

2. When the input is HIGH, the base-emitter junction of transistor, 9, is

reverse-biased and the base-collector junction is forward-biased.
3. This condition permits current to flow through Rg, and the base-collector
junction of transistor, Q, into the base of transistor, Q2
4. It drives transistor, Q into saturation. As a result, transistor, Q, is
turned ON due to ON state of transistor, Qg and its collector voltage,
which is the output, is near to ground potential.
5. Therefore, a LOW output is produced for a HIGH input. At the same
time, the colector of transistor, , is at a sufficiently LOW voltage level
to keep transistor, Q, OFF.
6. When the input is LOW, the base-emitter junction of transistor, Q, is
forward-biased, and the base-collector junction is reverse-biased.
7. The current flows through resistor, Rz, and the base-emitterjunction of
transistor, Q1, to the LOW input. A LOW provides a path to ground for
the current.
8. No current flows into the base of transistor, Q,. So it is OFF. The collector
oftransistor, Q, is HIGH, thus turning transistor, ON. A saturated
transistor, Q, provides a low-resistance path from Vcc to the output.
9. Therefore, a HIGH on the output is produced for a LOW on the input. At
the same time, the emitter of transistor, Q is at ground potential, keeping
transistor, Q, OFF.
Table 4.5.1. Operation of TTL inverter.

Inputs Transistors Output

A
1
Emitterjunction, A
Logic 0 Forward bias (ON) OFF OFF ON Logic
Logic1 Reverse bias (OFF) ON ON OFF| Logic 0

Que 4.6. Describe the construction and operation of TTL NOR

gate.
Answer
1. The circuit of the two-input TTL NOR gate is shown in Fig. 4.6.1. Two
input transistors and Q are emitter transistors.
2. Transistor Q, and Q, are called the phase splitters. Emitter of transistor
i s connected to collector of transistor Q, through diode D.
3. Transistors and Q, form a totem-pole arrangement. Diodes D and
Dg protect transistor and Qg from being damaged by the negative
spikes of voltages at the inputs.
4 When negative spikes appear at the input terminals, the diodes conduct
and bypass the spikes to ground.
5. Diode D ensures that transistors Q, and Q, do not conduct
simultaneously. Transistor Q, acts as an emitter follower.
4-8B (EC-Sem-3) Logic Families & Sermiconductor Memories

'+Vcc

RC1.6kn Re130 ni
RBB 4 k2

A .

V Dr
B

Ds
RE121k2.
Fig. 4.6.1. TTL NOR gate.
Operation:
Table 4.6.1. Operation of TTL NOR gate.
inputs Transistors Output
B

Emitter junction,AEmitter junction, B

0 Forward bias (ON) Forward bias (ON) OFF OFF| OFFON
Forward bias (ON) Reverse bias (0FF) OFF ON ON OFF
Reverse bias (OFF)Porward bias (ON) ON| OFF ON OFF
Reverse bias (OFF)| Reverse bias (OFF)ION | ON | ONOFF |

ue 4.7, State various TTL parameters in brief.

Answer
Current sinking:
ATTL circuit acts as a current sink in LOW state, as it receives current
from the input of the gate by which it is driving.
2. Transistor is the current-sinking transistor or the pull-down transistor,
because it brings the output voltage down to its LOW state.
ii. Current sourcing:
1. A TTL circuit acts as a current source in the HIGH state, as it supplies
current to the gate by which it is driving.
Transistor is the current-sourcing transistor or the pull-up transistor,
because it pulls up the output voltage to its HIGH state.
iii. Floating inputs
When a TTL input is HIGH (ideally +5 V), the emitter current is
approximately zero. When a TTL input is floating no emitter eurrent is
possible because of the open circuit.
Digital System Design 4-9B (EC-Sem-3)
i. Therefore, floating TTL
a
input is equivalent to a HIGH output. Because
of this, unused TTL inputs are left unconnected: an open input allows
the rest of the gate to function
iv.
properly.
TTL loading and fan-out:
1. The TTL output has a limit,
sink in LOW state and a limit,
lo that gives the maximum current it can

loH, gives the maximum current it can

source in HIGH state.
2. To determine the fan-out, the drive
and oH and the current
capabilities of the output, i.e., IoL
requirements of each input, i.e., and areIy, IIH
known.
3. So, HIGH and ILOW state fan-outs are given by:
HIGH state fan-out =
oz
LOW state fan-out oL
1.
4. The actual fan-out capability is equal to the smaller of the above two
fan-out values and is given by

Actual fan-out capability= minimum4o,o

v. Unit load
Unit load means the current drawn or sourced back by similar gates.
Example: For 7400,
One unit load is 40 A in HIGH state that is known as
One unit load is 1.6 mA in LOW state that is known as
IH
I
PART-6

ECL

Questions-Answers
LongAnswer Type and Medium Answer Type Questions

9ue4.8.Explain the basic eireuit andoperationofemitter coupled

logic (ECL). What are the functions of emitter follower ?

Answer
Basic ECL eircuit :
1 The basic circuit for emitter-coupled logic is a differential amplifier
configuration as shown in Fig. 4.8.1.
2. The VEE supply produces a fixed current 1p, which remains around 3 mA
during normal operation. This current is allowed to flow through either
transistor , or transistor , depending on the voltage level at ViN
4-10B (EC-Sem-3) Logic Families & Semiconductor Memories

R
VCie
Vc
VINe

VEE
Fig. 48.1
3. In other words, this current switches between colector of , transistor
and collector of @, transistor as VN Switches between its two logic levels
of-1.7 V (logical 0 for ECL) and-0.8 V (logical 1 for ECL).
4. Table 4.8.1 shows the resulting output voltages for these two conditions
at VN
Table 4.8.1. Operating states of ECL

VN Outputs Remarkss
Voltage level Binary logic
1.7 V Logic 0 OV - 0.9 V
Q conducts
-0.8 V Logic 1 -0.9 V OV , conducts

Two important points are noted:

Vc and Vca are the complements of each other, and
i. The output voltage levels are not same as the input logie levels.
6. The emitter followurs perform two functions:
i Emitter followers subtract approximately 0.8 V from Vei and Vea to shift
the output levels to the correct ECL logic levels.
Emitter followers provide very low output impedance (typically 7 2),
which provides for large fan-out and fast charging of load capacitance.

Que 4.9 Describe the construetion and operation of ECL

OR/NOR gate.
Answer
1. A two-input ECL OR/NOR gate is shown in Fig. 4.9.1.
2. It has two outputs which are complements of each other. Transistors
and Q, forma differential amplifier. TransistorsQ, and Q are in parallel.
3. TransistorsQ, and Q, are emitter followers whose emitter voltages are
the same as the base voltages (less than 0.8 V base to emitter drops).
Digital System Design 4-11B (EC-Sem-3)

Rc1 Kcavca
A +B
Be 1
LA +B V EE

VEE
EE
Fig. 4.9.1. ECL NOR and OR gates
4. Inputs are applied to transistors andQ, and transistor ,is supplied
with constant- 1.3V.
Table 4.9.1. Operation of ECL OR/NOR gate.
Inputs Transistors Output
B 4 A+BA +B
OFF OFF ON ON OFFF 1
1 OFF ON OFF OFF | ON
0 ON OFF OFF
ON ON
OFF| ON
OFF OFF | ON

PART7
CMOS Families and their Interfacing.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 4.10.Describe the circuit and performance of CMOS inverter

and state the characteristics of CMOS.
AKTU 2018-19, Marks 3.5
Answer
CMOSinverter:
1. It consists of an NMOS transistor Q and a PMOS transistor
Q. The
input is connected to the gates of both the devices and the
output is at
4-12 B (EC-Sem-3) Logic Families & Semiconductor Memories

the drain of both the devices. The positive supply voltage is connected to
the sources of the PMOS transistor Q2, and the source of transistor
is grounded.
2. When A is LOW (O V). Gate to source voltage Vas2 of transistor Q2 is
5 V, and gate to source voltage Vos1 of transistor is 0 V.
Q1
-

So,
transistor Q2 acts as ON and transistor Q, acts as OFF. Therefore, the
switching circuit shown in Fig. 4.10.1(6) results in V, as logic HIGH that
is +5 V.
+5 V
+5V +5 V
ON)
QOPF)
A=1
A
A =0 V, =5V V, = 0V

OFP)
-ON)D
(a) (b) A = 0 (c) A 1
Fig. 410.1.(a
CMOS As ioverter, (6) and (o)
equivalent circuit
3. WhenA is HIGH(+5 V), gate to source voltage
Vos2 of transistor ,is
OV, and gate to source voltage VaS1 of transistor Q1 is +5 V. So, transistor
Q2 acts as OFF and transistor Q acts as ON. Therefore, the switching
circuit shown in Fig. 5.13.1(c) results with V, as logic LOW that is 0V.
Table 4.10.1. Operation of CMOS inverter.
Input, A
P-channel n-Channel Output,
MOSFET, MOSFET,
LOW (O V) ON OFF +5 V(HIGH)
HIGH (5 V) OFF ON OV (LOWV)
Truth table:

Characteristics of CMOS
Supply voltage: The 4000 and 74C series can operate with Vpp values
ranging from 3 to 15 V. The 74HC and 74HCT series can operate with
VDD Values ranging from 2 to 6 V.
ii. Voltage levels: When a CMOS output drives only a CMOS input and
CMOS gate has an extremely high input resistance, the current drawn
is almost zero and, therefore, the output
voltage levels will be very close
to zero for LOW state and
Vpp for HIGH state.
 4-13 B (EC-Sem-3)
Digital System Design
ii. Power dissipation: When a CMOS circuit is in a static state, its power
with increase in
dissipation per gate is extremely small, but it increases
level. For DC, CMOS power
operating frequency and supply voltage it increases to
dissipation is only 2.5 nW per gate when VpD 5 V, and
=

iv.
10 nW per gate when VDD 10 V.
=

Switching speed: 'The speed of the CMOS gate increases with increase
in Vpp. The increase in Vpp results in increase in power dissipation too.
Unused inputs: The CMOS inputs should never be left disconnected.
All CMOS inputs have to be tied either to a fixed voltage level
(OV or VpD) or to another input.

Que 4.11.Discuss the circuit diagram and operation of CMOS

NAND gate.

Answer
1. Fig. 4.11.1 shows a CMOS two-input NAND gate. Here, p-channe!
MOSFETs Q and Q, are connected in parallel and n-channel MOSFETs
and are connected in series.
Q, ,
2. When Ais Low (o V) and B is also LOW (O ).p-channel MOSFET9
acts ON, n-channel MOSFET , acts OFF, p-channel MOSFET 9, acts
ON and n-channel MOSFET 4, acts OFF. Thus, the switching results
V, as logic HIGH i.e., +5 V.
When A is LOW (0 V) and B is HIGH (5 V). p-channel MOSFET Q, acts
3.
ON, n-channel MOSFET Q, acts OFF, p-channel MOSFET Q, acts
OFF and n-channel MOSPET Q, acts ON. Thus, the switching circuit
results V, as logic HIGH ie., +5 V.
4. When A is HIGH (+5 V) and B is LOW (O V). p-channel MOSFET Q,
acts OFF, n-channel MOSFET Q, acts ON, p-channel MOSFETe, acts
ON and n-channel MOSFET Q, acts OFF. Thus, the switching circuit
results V, as logic HIGH i.e., + 5 V.
5. When A is HIGH (+5 V) and Bis also HIGH(+5V).p-channel MOSPET
Q, acts OFF, n-channel MOSFET , acts ON, p-channel MOSFET Q,
acts OFF and n-channel MOSFET Q, acts ON. Thus, the switching
circuit results V, as logic LOW i.e., O V.
+6 V

Vo

Fig4114.CMOSa NANDgate
4-14B (EC-Sem-3) Logic Families & Semiconductor Memories

Table 4.11.1. Switching operation of CMOS NAND gate

Inputs p-channel MOSFET -channelMOSFET Output
A
2
ON ON OFF OFF
ON OFF OFF ON
1 OFF ON ON OFF
OFF OFF ON ON

Que 4.12 Discuss the circuit diagram and operation of CMOS NOR
gate.
Answer
1. Fig. 4.12.1 shows a CMOS two-input NOR gate. Here, p-channel
MOSFETs Q, and , are connected in series and n-channel MOSFETs
3 and 4are connected in parallel.
DD +5 V

Fig 4.12.1, CMOS as NOR

Table 4.12.1. Switching operation of CMOS NOR gate

Inputs p-channel MOSFETn-channel MOSFETOutput

B

ON ON OFF OFF
ON OFF OFF ON
0 OFF ON ON OFF
OFF OFF ON ON

Que 4.13. Discuss the circuit and operation of CMOS transmission

gate.
Digital System Design 4-15B (EC-Sem-3)

AnsweT
1. Atransmission gate is simply a digitally controlled CMOS switch. When
the switch is open (OFF), the impedance between its terminals is very

large.
Itis used to implement special logic functions. Since the CMOS gate can
transmit signals in both directions, it is called a bilateral transmission
gate or bilateral switech.
3 It is useful for digital and analog applications. The TTL and ECL gates
are essentially unidirectional.
4. Fig. 4.13.1 shows the schematic diagram and logic symbols of a CMOS
transmission gate. The n-channel MOS and p-channel MOS transistors
are connected in parailel.
5. So, both polarities of input voltages can be switched. The control signal,
Cis connected to then-channel MOSFET and its inverse is connected to
the p-channel MOSFET.
O/P

+V pD

Control, C IIP

Fig. 4.13.1. CMOS transmission gate

Table 4.13.1. Operation of CMOS transmission gate

Inputs p-channel n-channel Action
MOSFET MOSFET
C IIP Vos
+ve OFF OV OFF No transmission
OV OFF -ve OFF No transmission
OV OFF +ve ON Transmission
-ve ON OFF Transmission
ö. So, it can be concluded that when the control, C is HIGH, the circuit acts as a
closed switch and allows the transmission of the
When the control, C is LOW, the circuit acts as an
signal from input to output.
open switch and
blocks the transmission of the signal from input to
output.
8. Since, the input and output terminals are interchangeable, the circuit can also
transmit signals in the opposite direction. So, it acts as a bilateral switch.

Que 4.14. Explain TTL to CMOS interfacing and CMOS to TTL

interfacing.
 4-16B (EC-Sem-3)
Logic Families & Semiconductor Memories

Answer
TTLto CMOS
1. The MOS and CMOS
gates are slower than the TTL gates, but consume
less
space. Hence, there is an
advantage is using TTL and MOS devices
in combination.
2. The input current values of CMOS are low as
current capabilities of any TTL series. compared to the output
Thus, TTL has no problem in
meeting the CMOS input current requirements.
So, a level translator is used to raise the level of the
the TTL gate to an acceptable level for CMOS.
output voltage of
4. The presence of the
pull-up resistor will cause the TTL output to rise to
approximately + 5 Vin the
HIGH state, thereby providing an adequate
CMOS input as shown in Fig. 4.14.1.
+5V 5 V 10 V

Rp
---
Buffer
TTL JCMOS |TTL JCMOS
(a) TTL to CMOS interfacing 6) TTL to CMOS
(low voltage)
interfacing
(high voltage)
Fig 4.14.1
CMOS to TTL:
The CMOS output can supply enough voltage and current to satisfy
the TTL input requirements in the HIGH state. Hence, no special
consideration is required for the HIGH state.
But the TTL input current requirements at LOW state cannot be met
directly.
3. Therefore, an interface circuit with a LOW input current requirement
and a sufficiently high output current rating is required. The
arrangement is shown in Fig. 4.14.2.
When a high voltage CMOS has to drive a TTL gate, a voltage level
translator that converts the high voltage input to a +5 V output is used
between CMOS and TTL as shown in Fig. 4.14.2.
16 V +5 V

CMOS Buffer Buffer

TTL input CMOS TTL

(a) CMOS to TTL (6) CMOS to TTL

interfacing (low voltage) interfacing high voltage)
Fig.4.14.2
 Digital System Design 4-17B (EC-Sem-3)

Que 4.16. Explain the interfacing of TTL to ECL and ECL to TTL.

Answer
TTL to ECL:
1 The TTLis the most widely used logic family, but its speed ofoperation
is not very high.
2. The ECL is the fastest family. In some applications, the rate at which
input data is to be handled may be much lower than the rate at which
the output data is to be handled.
3. Therefore, it becomes necessary to interconnect the two different logic
systems, such as TTL and ECL
A TTL cannot interface directly with an BCL; it requires a translator as
shown in Fig. 4.15.1.

A-

B X
TTL
L------ TTL to ECL
ECL
translator

Fg 4.16.1 TTL drivingRCL

5. One such application is in the time division multiplexing of n digital
signals to form a single digital signa.
Although, the bit rate ofeach of the n signals may be handled using TTL,
the bit rate of the composite signal is n times faster and may require
ECL to process it.
ECL to TTL:
Sometimes, the input data is at a faster rate, but the output data is at
a slower rate like in demultiplexers.
2 An ECL to TTL logic translator will be of use in such cases. It shows
that the input logic levels of a translator are compatible with the output
logic levels of ECL and the output logic levels of a translator are
compatible with input logic levels of a TTL.
the
3. Fig. 4.15.2 shows the ECL gate driving a TTL gate.

A*

B. OX
ECL
ECL to TTL TTL
Vcc i translator
-----

Fig 415..ECL driving TL

4-18 B (EC-Sem-3) Logic F'amilies & Semiconductor Memories

PART-8
Memory Elements, Concept of Programmable
Logic Devices Like FPGA

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 4.16. Discuss the concept of field programmable gate array

FPGA). Describe the various structures of FPGA.
AKTU 2018-19, Marks 3.5
Answer
Field Programmable Gate Array:
FPGAis high capacity PLD (programmable logie device). The gate array
of FPGA has the ability to be programmed for a function by the user
instead of the manufacturer of device.
FPGA consists of three configurable (programmable) logic modules
(LMs): configurable logic blocks (CLBs), input and output blocks and
Switching matrix for interconnection.
3. The CLB consists of a combinational logic array, data multiplexer (MUX)
and flip-flops. The combinational array function is performed by look-up
table (LUT).
Structures of FPGA:
i Programmable logic structure:
The programmable logic structure of FPGA consists ofa two-dimensional
array of CLBs.
Each CLB typically contains one or two flip-flops to allow implementation
of sequential logic.
Large designs are partitioned and mapped to a number of CLBa with
each CLB configured (programmed) to perform a particular function.
These CLBs are then connected together to fiully implement the target
design.
Programmable routing structure:
1. To allow for flexible interconnection of ClLB, FPGA has three
programmable routing resources.
2. Vertical and horizontal routing channels which consist ofdifferent length
of wires that can be connected together if needed.
3. These channels run vertically and horizontally between columns and
rows of CLBs as shown in the Fig. 4.16.1.
 4-19B (EC-Sem-3)
Digital System Design
4. Connection boxes, which are set of programmable links, can connect
or the horizontal
input and output pins of the CLBs to wires of the vertical
routing channels.
5. Switch boxes are located at the intersection of the vertical and horizontal
channels.
These are a set of programmable links that can connect wire segments
6.
in the horizontal and vertical channels.
Vertical
Cnanne

Programmable Horizonta
input/ output channe
Conigurable
L logic block(CLB)

Switch box

-Horizontal
connections

Vertical channel

Fig. 4.16.1. Programmable structure of

field programmable logic array (FPGA).
iii. Programmable input/output:
1. These are mainly buffers that can be configured either as input buffers
or output buffers or
input/output shown in Fig. 4.16.1.
as
These allow the pins of the FPGA chip to function either as input pins or
output pins or input/output pins.
iv. Configurable logic blocks:
1. There are a number of CLBs in an FPGA organized as an array of rows
and columns. The logic blocks are connected to the VO blocks through
common row/ column programmable interconnects.
2. The common row/ column interconnects are known as global
interconnects.
3. A logie block consists of a number of LMs. The LMs are the basic logic
elements in a FPGA. The LMs within a CLB are connected through local
programmable interconnects.
Logie module:
A logie module (LM) consists of a LUT, a D-type fip-flop and a MUX.
Most of the FPGAs are based on 4-input LUT. Fig. 4.16.2 shows a block
diagram of a LM with 4-input LUT.
2. Output of the LUT becomes the output of the LM either directly or
through D-type flip-flop. Thus, the output can be configured for
combinational or registered ti.e., through flip-flop).
4-20B (EC-Sem-3) Logic Families & Semiconductor Memories

Four-input
Input look-up D
MUX Output
table
(LUT)
|Flip-flop
Clock- Select lines
Fis 4.16.2. Blocdk disgramoflogic module
PART-99
Logic Implementation Using Programmable Devices

Questions-Answers
Long AnSwer 1ype and Medium Answer Type Questions

Que 4.17. Draw the basic configuration of three PLDs.

AKTU 2016-17, Marks10

Answer
1. The PROM is a combinational programmable logic device (PLD)-an
integratedcircuit with programmable gates divided into an AND array
and an OR array to provide an AND-OR sum-of-produet
implementation. Fig. 4,17.1 shows the configuration of the three PLDs

Fixed AND Programmable Outputs

Inputs
array (decoder) OR array
a) Programmable read-only memory (PROM)
Inputs rogrammable Fixed
AND array Outputs
OR array
(6) Programmable array logic (PAL)
Inputs Frogrammable Programmable Outputs
ANDarray OR array
(c) Programmable logic array (PLA)
Fix. 4.17.1.

2. The PROM has a fixed AND array constructed as a decoder and a

programmable OR array. The programkable OR gates implement the
boolean functions in sum-of-minterms form.
 4-21 B (EC-Sem-3)
Digital System Design
The PAL has a programmable AND array and a fixed OR array. The
3.
AND gates are programmable to provide the product terms for the
boolean functions which are logically summed in each OR gate.
The most ilexible PLD is the PLA, in which both the AND and OR arrays
can be programmed. The product terms in the AND array may be shared
by any OR gate to provide the required sum of products implementation.

What is the basie architecture of PLA ? How is the

Que4.18. a

capacity of a PLA specified ? How is it programmed? Explain.

OR
Write a short note on PLA. AKTU 2017-18, Marks 3.5
OR
Write down the classification of semiconductor memories. Draw
and explain the programmable logic array (PLA).
AKTU 2014-15,Marks 06
Answer
Classification of semiconductor memories :
Fig. 4.18.1 shows an overview of semiconductor memory types.
Semiconductor memories

Read only memory

Read/write memory
or random access memory (RAM) (ROM)

Dynamic RAM Statie Mask (Fuse) ROM

(DRAM) RAM Programmable ROM (PROM)
(SRAM) Erasable PROM (EPROM)
Electrically Erasable PROM
Plash memory
Ferroelectric RAM (FRAM)

Pig. 4.18.1.Classification ofsemiconductor memories

Programmable logic array (PLA) :
PLAs are used to map irregular combinational funetion onto regular
structures. The PLA provides the designer with a syatematie and regular
way of implementing output functions of n variable in sum of produet
form.
2. PLA is one of the regular macro used in the implementation of FSM
(finite state machine). PLA funetions may be significantly changed
without requiring major changes of either the design or layout. It is
more compact in nature. Any of the logical function can be expressed in
terms of SOP or POS
4-22 B (EC-Sem-3) Logie F'amilies & Semiconductor Memories

3. PLA be
can
implemented in several forms, i.e., NOR-NOR,
NAND-NAND, NAND-NOR.
4 The structure of PLA is shown in Fig. 4.18.2, and its internal logic with
three inputs and two outputs is shown in
Fig. 4.18.3.
5. The particular boolean functions implemented in the PLA of
Fig. 4.18.3, are

F AB + AC + ABC
F, = (AC + BC)

m input AND OR
lines array array

n output lines
Fig. 4.18.2. PLA structure.
6. The programming table that specifies the PLA of Fig.4.18.3 is listed in
the table 4.18.1. The PLA programming table consists of three sections.
A

B
C
D - AB'

2- AC

3)- -BC

-A'BC
C C'BB'A A'

Fig. 4.18.3, PLA with three inputs, four product terms, and two outputs.
7. The first section lists the product term numerically. The second section
specifies the required paths between input and AND gates. The third
section specifies the path between the AND and OR gates.
8. For each output variable, we may have a T (true) or C (complement)
for programming the XOR gate.
9. For each product term, the inputs are narked with 1, 0 o r - (dash).
 Digital System Design 4-23 B (EC-Sem-3)

10. If the variable in the product term appears in the form in which it is
true, the corresponding input variable is marked with a 1. Ifit appears
complemented, the corresponding input variable is marked with a 0. If
the variable is absent from the product term, it is marked with a dash.
Table 4.18.1. PLA programmin8

Input Output
Product term (7 F(C)F
AB
AC
BC
0
ABC
11. The size of the PLA is specified by the number of inputs, the number of
product terms, and the number of outputs. A typical integrated circuit
PLA may have 16 inputs, 48 product terms and eight outputs.
12. For n inputs, k product terms, and m outputs, the internal logic of the
PLA consists of n buffer-inverter gates, k AND gates, m OR gates, and
m XOR gates.

Que 4.19 Draw the logic configuration of four input and four
output PAL and explain.

Answer
1. A programmable array logic has the same structure as a ROM, but has
a programmable AND array anda fixed OR (or NOR) array.
2. Because of the fixed OR array, a PAL device is cheaper comparatively
and easier to program.

3. However, the lack of shared rows with the column requires that each
output function be simplified, with no common product term with others.
It is easier to program, but is not flexible.
PAL with the four input and four output

1 Each input has a buffer-inverter gate and each output is generated by

fixed OR gate.

2. In designing with a PAL, the boolean funetion must be simplified to fit

into each section unlike the situation with a PLA, a product term cannot
be served among two or more OR gates. Therefore, each function can
be simplified by itself, without regarding common product terms.
4-24 B (EC-Sem-3) Logic Families & Semiconductor Memories

3. The number of produet terms in each section is fixed, and ifthe number
of terms in the function is too large, it may be necessary to have two
sections to implement one boolean function.
AND gate input

12 34 910
Product term

10

11

12

23 45 6 78910
Pig. 4.19.1, PAL with four inputs, four outputs and a three wire
AND-OR structure.

Que 420. Realize the full adder circuit using the PAL.

Answer
Full adder using PAL : There are two funetions used for the
implementation of full adder:
S= ABC + AB + AB + ABC

C ABC+ ABC + ABC + ABC

Digital System Design 4-25 B (EC-Sem-3)

A A B B C

Fig. 4.20.1
Que 421. Differentiate between PLA and PAL. Realize the ful
adder circuit using PAL. AKTU 2018-19, Marks 3.5
Answer
A Difference:

S.No. PAL PLA

1. It is moderately expensive It is expensive than PAL and PROM
and moderately complicated. and complicated to use.

In this, only the AND array | In this, both AND and OR arrays
is programmable, OR array are programmable.
is fixed.

3.
It is easier to progran |It is complicated to program because
because only the AND gates both the AND and OR gates are
are programmable programmable.
It is less flexible due to fixed It is more flexible than
PAL.
OR gates

B. Full adder using PAL: Refer Q. 4.20, Page 4-24B, Unit-4

4-26 B (EC-Sem-3) Logic Families & Semiconductor Memories

Que 4.22. Implement the following four boolean functions with a

PAL
WA, B, C, D) = EmC 12,13)
XA, B, C, D) = Em(7, 8, 9, 10, 11, 12, 13, 14, 15)
Y (A, B, C, D) = Em (0, 2,3,4, 5, 6,7,8, 10, 11, 15)
Z A, B, C, D) = Zm(1, 2, 8, 12, 13)

AKTU 2016-17, Marks 15

AnswerT
1. to a minimum number of terms results
Simplifying the four functions
in the following boolean functions:

For W For X
CD
AB 11 B\ 00
00 01 10 01 11 10

00 00

01 01|
6

11 11 1
12 12
10 10 1 |11
11 10

For Y For2
CD CD
AB 00 01 11 10 AB 00 01 10
0

o1 01

12
1

Fig. 4.22.1

W= ABC+ ABCD

X = A+ BCD
 4-27B (EC-Sem-3)
Digital System Design

BD
Y = AB+CD+
Z= ABC + ABCD+ ACD+ ABCD

W+ACD + ABCD
table for the four boolean
2 Table 4.22.1 lists the PAL programming
sections with three
functions. The table 4.22.1 is divided into four
product terms in each section.

The first two sections need only two product

terms to implement the
3.
boolean function. The last section for output needs four product
the output from W, we can reduce the function to three
terms. Using
terms.
4.22.1
The fuse map for the PAL as specified in the programming Table
is shown in Fig. 4.22.2 for each l or 0 in the Table 4.22.1.
We mark the corresponding intersection in the diagram with the symbol
5.
for an intact fuse. For each dash, we mark the diagram with blown
fuses in both the true and complement inputs.
If the AND gate is not used we leave all its input fuse intact. Since the
b.
corresponding input receives both the true value and the complement

of each input variable, we have AA = 0 and the output of the AND

gate is always 0.
Table 4.22.1. PAL programming

Product Term AND Input Outputs

A
C
1 W ABC+ ABCD

2 0

3
X = A+ BCD

Y= AB+ CD BD
8

10 1 Z =W+ ACD+ ABCD

11 0

12 0 0 0
 4-28 B (EC-Sem-3) Logic Families & Semiconductor Memories

Product
term
A A B BCC D D WW

All fuses intact

B (always = 0)

C
10-

11-

12-
xFuse intact
D +Fuseblown
TL
A A B BCC D D WW
Fig 4.22.2. Fuse map for PAL as specified in Table. 4.22.1.

Que 4.28,A combinational circuit is defined by the functions

F,A, B, C) Em(3,5, 6)
=

FA,B, C) Zm(0,2, 7)
=

Implement the cireuit with a PLA.

Answer
Simplify the given boolean expression

F A, B, C)= Em(3, 5, 6)
FA,B, C)= Em(0, 2, 7)
 4-29 B (EC-Sem-3)
Digital System Design
For F:
BC For F BC
A 00 01 11 10 A 00 01 11 10

AC ABC
F ABC+ ABC+ ABC F2 = +

Fig. 4.23.1.
PLA program table:

Produet term Inputs Outputs

ABC
ABC
ABC
AC 0

ABC
Implementation:
A

Product
erm

ABC ABC ABC AC ABC

Sum
term
Fig 4.33.2

Que 424. Design a 3-bit binary to Gruy code converter using PLA.

AKTU 2016-16, Marko10

4-30 B (EC-Sem-3) Logic Families & Semiconductor Memories

Answer
Truth table:

Binary input Gray output

B B B G G G
0 0 0
0 0 1
1
1 0
0
1 111
1 0 1
0

Simplification using K-map:

The K-maps for the Gray outputs are as shown in Fig. 4.24.1.

ForG2 For G
B,Bo BB
B2 00 0111 10 B 00 01 11 10
0

(a) (6)
For Go
Ba00 01 11

(c)
Fig. 4.24.1.
G, = B,

G= B,8,+B,B
G B,B,+ B,,
Implementation:
Fig. 4.24.2 shows the implementation using PLA.
Digital System Design 4-31 B (EC-Sem-3)

Bo
B
Binary
inputs
B B AND matrix

B
B2
BgB B,B BB,B,B G

G ay
ooutput

OR matrix
Fig 424.2

VERY IMPORTANT QUESTIONS

Following questions are very important. These questions
may be asked in your SESSIONALS as well as
UNIVERSITY EXAMINATION.

1 . Describe the circuit and performance of CMOS inverter and

state the characteristics of CMOS.
A Refer Q. 4.10, Page 4-11B, Unit-4.

Q2. Discuss the concept of field programmable gate array

(FPGA). Describe the various structures ofFPGA.
A Refer Q. 4.16, Page 4-18B, Unit-4.

3 . What is the basic architecture of a PLA ? How is the capacity

of a PLA specified ? How is it programmed ? Explain.
An Refer Q. 4.18, Page 4-21B, Unit-4.

4 . Differentiate between PLA and PAL. Realize the full adder

circuit using PAL.
Ans Refer Q. 4.21, Page 4-26B, Unit-4.
4-32 B (EC-Sem-3) Logic Families & Semiconductor Memories
Q5. Implement the following four boolean functions with a
PAL
W A, B, C, D) = Em(2, 12, 13)
XA, B, C, D) =
Em (7, 8, 9, 10, 11, 12, 13, 14, 15)
Y (A, B, C, D) = Em(0, 2, 3, 4,5,6, 7,8, 10, 11, 15)
Z (A, B, C, D) = Em(1, 2, 8, 12, 13)
Ans Refer Q. 4.22, Page 4-26B, Unit-4.

using PLA.
Q.6. Design a 3-bit binary to Gray code converter

Ans Refer Q. 4.24, Page 4-29B, Unit-4.

NAND gate.
Q.7. Describe the construction and operation of TIL
Ans Refer Q. 4.1, Page 4-2B, Unit-4.

PLDs.
Q.8. Draw the basic configuration of three
AnE 4-20B, Unit-4.
Refer Q. 4.17, Page
 5
UNIT
D/A and A/D Converter

CONTENTS
Part-1 Weighted Resistor, R-2 R Ladder . 5-2B to 5-7B

*********************************
6 - 7 B to 5-8B
Part-2 : Resistor String ..
Part-3: Analog to Digital Converters: . . . 5-88 to 5-10B
Single Slope

Part-4 Dual Slope, Successive ********** ..5-10B to 5-15B

Approximation, Flash

Switched Capacitor to 5-17B

Part-5
Basic Concepts,
Cireuits..
Practical
168B

Configurations
Part-6 .-17B
Application in Amplifier.************************) to 5-18B

5-18B
Part-7: Integrator, ADC.****** ************************* to 5-20B

5-1B (EC-Sem-3)
5-2 B (EC-Sem-3) D/A and AD Converter

PART1
Weighted Resistor, R-2 R Ladder.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 5.1.Explain working of weighted resistor D/A converter.

Answer
In a weighted resistor D/A converter every resistor has a definite weight
assigned to it.
One of the simplest circuit shown in Fig. 5.1.1, is a summing amplifier
with a binary weighted resistor network. It has n-electronic switches
D,, D, .D, D, controlled by binary input word.
Ifthe binary input to a particular switch is 1, it connects the resistor to
the reference voltage (-V,). And if the input bit is 0, the switch connects
the resistor to the ground.

R
W-
lo

'R 2'R

(LSB) D D3 D (MSB)

-VR
Fig5.11Aaimple weighted renistor Di/A eonverter
4. From Fig. 5.1.1, the output currentI, for an ideal op-amp can be written
as

=(D2' +D,2 *+D,2..+D,2")

Digital System Design 5-3 B (EC-Sem-3)

5. The output voltage,

V = IR

= VR(D,21 + D,22+ D,23 + ... + D,2 )

R
Que 5.2.Draw a 4-bit binary weighted D/A converter, find the
value of step size ifR = 10 K and R, = 1.2 K. What is the output
voltage when all binary inputs are at 5 V?

Answer
A Weighted resistor D/A converter:
R
wW

oVo
2'R 2'R 2'R

LSBD, D2 Di (MSB)

-VR
Fig, 5.2.1.4-bit bínary weighted resistor D/A converter.

B. Numerical:
Given:R- 10 K, R,= 1.2 K, V = 5 V, N=4
To Find :Step size, Output voltage

5 = 0.333 V
Stepsize=-12-1 15

Output voltage =Va2'.2 *,2'+2 '

51.2 1 1
10

= 0.5625 V

Que 6.. What is a DAC ? Describe the weighted resistor DAC.

Give mathematical expressions in support of your answer.
 5-4B (EC-Sem-3) D/A and A/D Converter

OR
Explain different types of DAC.

Answer
DAC:
1. It is the process of taking a value represented in digital code and
converting it into a voltage or current which is proportional to digital
value. It is accomplished by the use of DAC or D/A converter.
2. The analog voltage output V. of an N-bit straight binary D/A converter
is related to the digital input by the relation.
V.=K(2*- b. +2*bxat.26,+ 26, +b,)
K= Proportionality factor
by 1, ifMh bit of digital input is 1
0,if N bit of digital input is 0.
There are two types of D/A converters:
Weighted resistor D/A converter: Refer Q. 5.1, Page 5-2B, Unit-6.
ii R-2R Ladder D/A converter :
1. This network uses resistors of only two values R and 2R. The inputs to
the resistor network are applied through digitally controlled switches.

Rp

R R 2R
-
Vo
2R 2R 2R 2 2R

LSB
MSB

Pig. 6.3.1.
2. Consider a 3 bit R-2R Ladder D/A network. Let us assume a digital input
of001. The equivalent circuit becomes as shown in Fig. 5.3.2.
Digital System Design 5-5B (EC-Sem-3)

R 2R
ww ww-o

2R 2R 2R 2R
Z

Fig. 5.3.2.
3 Applying Thevenin's theorem at point X*', we get
2R
w-

2R 2R

Fig. 5.3.3.
4. Applying Thevenin's theorem at YY, we get

RY R 2R
ww-oMW WWWO
R

Y
Fig. 6.8.4.

5. Applying Thevenin's theorem at ZZ', we get

2R
www W

Fig. 5.3.6.
6. The equivalent resistance is 3R in each case. The circuit reduces to
 5-6B (EC-Sem-3)
D/A and A/D Converter

3R Rp

3R

3R
0 W-
Fig 5.8.6.
7. The output voltage is given as

V= -3R
3R 2 RVRb* Rb
3R 2
3R 2 " 3R 2
14b,+2b, +b,1
3R
8. The number of resistors
required for N-bit D/A converter is 2N in the
case of R-2R ladder D/A
converter
Que 54 Explain the performance characteristics of D/A
converters.

Answer
1. Resolution:

It is the smallest
possible change in output voltage as a fraction or
percentages of the full-scale output range.
Example for
a 8-bit converter there are 25
or 256 values of
voltage, hence the smallest change in the output voltage isanalog
1/255thoutput
of full
scale output range.
2 Linearity:
The input-output relationship should be linear for a D/A converter. But
sometimes the relation is non-linear. This is due to
error in resistor
values and voltage across the switches.
ii. If converter was ideal the dots will fall
it is indicated
on
straight line. But if it has
errors by
shown in Fig. 6.4.1.
e as

3. Accuracy: It is the meas ure of the difference between the actual

output voltage and expected output voltage. It is specified as percentage
of full scale maximum output voltage.
or

4. Settling time : When a digital input to a D/A converter changes, the

output voltage does not change abruptly because of the delay in the
circuit. The time required for the analog output voltage to settle within
t (1/2) LSB of the final value after a
change in digital input is called
settling time.
 Digital System Design 5-7B (EC-Sem-3)

000 001 010011100 101 110 111

Fig.54.1.

PART-2
Resistor String.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 55. Write a short note on resistor string

Answer

1. A simple DAC that in inherently monotonie is the resistor string DAC,

as shown in Fig. 5.5.1.

2. In this circuit, a reference voltage (VREp) is connected across a resistor

string of equal value resistance.

3. For an n-bit DAC, this requires 2" resistors and the taps between the
resistors are connected to switches controlled by the digital logic input
values (and their complement).

4. At the output node, an output voltage (Vorr) is generated, the value set
by the positions of the switches.
5. The output would need to be suitably buffered in order to prevent
electrical loading of the converter output.
5-8 B (EC-Sem-3) D/A and A/D Converter
=

R
REF R
|R

B) b2 b2 b1 b+ (MSB)
Fig.5.5.1. Resistor atring DAC

PART-3
Analog to Disital Converters: Single Slope.

Questions-Answers
Long Answer Type and Medium Ansiyer Type Questions

Que 5.6.Write short note on analog to digital converter (ADC).

Answer
1. The block schematic of ADC in Fig. 5.6.1 provides the function just
opposite to that of a DAC.

Start EOC

d MSB
Analog ADC F-. Digital
input V output

VReference)
Fig. 64.1. Punctional diagram of ADC.
2. It accepts an analog input V, and produces an output binary word
d, da.., d,of functional value D, so that
D =
d,2-'+d,2-2 + . . .

+d,2- ..5.6.1)
where d, is the most significant bit and d, is the least significant bit.
 Digital System Design 5-9B (EC-Sem-3)

3. An ADC usually has two additional control lines, the START input to tell
the ADC when to start the conversion and the EOC (end of conversion)
output to announce when the conversion is complete.
Depending upon the type of application, ADCs are designed for
microprocessor interfacing or to directly drive LCD or LED displays.
5. ADCs are classified broadly into two groups according to their conversion
technique.
6. These are Direct type ADCs and Integrating type ADCs. Direct type
ADCs compares a given analog signal with the internally generated
equivalent signal.
7. Integrating type ADCs perform conversion in an indirect manner by
first changing the analog input signal to a linear function of time or
frequency and then to a digital code. The two most widely used integratingg
typeconverters are:
Charge balancing ADC.
Dual slope ADC.
8. The most commonly used ADCs are successive approximation and the
integrator type. The successive approximation ADCs are used in
applications such as data loggers and instrumentation where conversion
speed is important.
9.The suecessive approximation and comparator types are faster but
generally less accurate than integrating type converters. The flash
comparator) type is expensive for high degree of accuracy.
10. The integrating type converter is used in applications such as digital
meter, panel meter and monitoring systems where the conversion
accuracy is critical.

Que 5.7, Explain the working of single slope ADC.

Anawer
1. It consists of a ramp generator and BCD or binary counters. The
Fig. 5.7.1 shows the single slope ADC.
2. At the start, the reset signal is provided to the ramp generator and the
counters. Thus counters are reset to O's.
3. The analog input voltage Vin is applied to the positive terminal of the
comparator
4. As this is more positive than the negative input, the comparator output
goes high.
5. The output of ramp generator is applied to the negative terminal of the
comparator.
6. The high output of the comparator enables the AND gate which allows
clock to reach to the counters and also this high output starts the
ramp
5-10B (EC-Sem-3) D/A and AD Converter

7 The ramp voltage goes positive until it exceeds the input voltage. When
it exceeds Vin, comparator output goes low.
8. This disables AND gate which in turn stops the clock to the counters.
The control circuitry provides the latch signal which is used to latch the
counter data.
The reset signal resets the counters to 0's and also resets the ramp
generator. The latched data is then displayed using decoder and a display
device.

Analog
input Clock
i n o
IN

AND gate
omparator BCD or Binary counters
Ramp Timing and ResetD II
generator Ramp control
Latches
reset Latch
IIIL
Decoder or drivers

B Display
Fig. 5.7.1. Single slope ADC

PART-4
Dual Slope, Successive Approximation,
Flash
Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 5.8 Explain the working of dual slope integrating ADC with
the help of circuit diagrum.

Answer
1.Fig.5.8.1(a)shows the dual slop ADC funetional diagram. The cireuit
consists ofahigh input impedance bufier A,. precision integrator A, and
a voltage comparator.
2 The converter first integrates the analog input signal V, for a fixed
duration of 2"clock periods as shown in Fig. 5.8.1(b).
3. Then it integrates an internal reference voltage Vz of opposite polarity
until the integrator output is zero.
Digital System Design 5-11 B (EC-Sem-3)

4. The number N of clock cycles required to return the integrator to zero

is proportional to the value of V, averaged over the integration period.
Hence, N represents the desired output code.
R

WA CM
SW

C
Start Control n-stage
EOC logic counter

(a)

Integrator
output voltage

Autozero T = 2T_ N-cycles Autozero

Time

i Integrate Integrate
Va -VR
(b)

Fig. 5.8.1. (a) Functional diagram of the dual slope ADC

(b) Integrated output waverform for the dual slope ADC.
Operation
1. Before the START command arrives, the switch SW, is connected to
gTOund and SW, is closed.
2. Any offset voltage present in the A,, Ag, comparator loop after
integration, appears across the capacitor Caz till the threshold of the
comparator is achieved.
3. The capacitor Caz thus provides automatic compensation for the
input-offset voltages ofall the three amplifiers
4. Later, when SW, opens, Caz acts as a memory to hold the voltage required
to keep the offset nulled.
5. At the arrival of the START command at t =
t,, the control logic opens
SW, and connects SW, to V, and enables the counter starting from zero.
6. The analog voltage V, is integrated for a fixed number 2" counts of clock
pulses after which the counter resets to zero.
5-12 B (EC-Sem-3) D/A and A/D Converter

7. If the clock period is T, the integration takes place for a time

T, = 2" x T and the output is a ramp going downwards as shown in

Fig.5.8.1b).
8. The counter resets itself to zero at the end of the interval 7, and the
switch SW, is connected to the reference voltage (-VR
9 The output voltage v, will now have a positive slope. However, when v,
becomes just zero at time t = ta, the control logic issues an end of
conversion (EOC) command and no further clock pulses enter the
counter.

2" counts
T Clock rate
Digital count N
and
t-t Clock rate
10. For an
integrator,
Av, = (-1/RC) V (2)
11. The voltage v. will be equal to u, at the instant t, and can be written as
v = (-VRC) V,-4,
12. The voltage u, is also given by

So,
(1/RC)-V)t-t5)
V t - t ) = Vpl's-12)
Putting the value of(t, -t)=2" and (t-t) =N, we get
V2) = (VRN
or, V. = (Vp) (N/2")

ue 5.9. Write a short note on successive approximation A/D

converter.

Answer
1. The Buccessive approximation technique uses a very efficient code
strategy to provide n-bit conversion in n-clock periods.
Start o- EOC

V.c SAR
CLK
d da ds
d(MSB)
d

DAC

Fig 6..4. Pusetional disgren of the sacoesive aprozimatioaADC

Digital System Design 5-13B (EC-Sem-3)

Working
1. With the arrival of the START command, the SAR sets the MSBd, = 1
with all other bits to zero so that the trial code is 10000000.

The output V of the DAC is now compared with analog input V,. If V,
2.
is greater than the DAC output V then 10000000 is less than the correct
digital representation.
3. The MSB is left at '1' and the next lower significant bit is made '1' and
further tested.
4 However, if V. is less than the DAC output, then 10000000 is greater
than the correct digital representation.
5. So reset MSB to 0 and go on to the next lower significant bit. This
procedure is repeated for all subsequent bits, one at a time, until all bit
positions have been tested.

Whenever the DAC output crosses Va, the comparator changes state
and this can be taken as the end of conversion (EOC) command.

Que 510 Draw and explain the fnash type A/D converter. Also
discuss the corresponding digital output with respect to input signal
voltage.
OR
Design a parallel-flash ADC and explain its working.

Answer

The commonly used A/D converter is parallel orflash converter. A 3-bit

parallel comparator A/D converter is shown in Fig. 5.10.1.
Working
1 Let V, is the input analog voltage to be converted into digital form. The
reference voltage like V, V . are generated using resistor network.
V, is compared simultaneously with the reference voltage by using
2
comparators.
 5-14B (EC-Sem-3) D/A and A/D Converter

V
R/2

VPT= 13/14 V
R C
V6=11/14V
6
Vrs 9/14 V L
Cs A DB
Vr47/14 V Digital
output
V5/14 V Bo
S

V2 3/14 V
C2
V= 1/14 V
R/2

Fig. 5.10.1
3. A 7-bit output is obtained from the comparator is converted to a 3-bit
output using decoder cireuit.
4. The process adopted here is the simplest and it works quite fast.
5. Thedemerits rapidly increase in the number of comparators with the
number of bits and the corresponding complications of the decoder circuit.
6. The analog input, comparator outputs and digital output are shown in
Table 5.10.1
Table 5.10.1.

Analog input | Comparator outputs Digital output

Ba B, B
0V.<V, 0 0 0 0 00 o

V,V.<Va 0 0000 0 1 0 0 1

Va.Va 0 0000 1 1 0 1 0

VaV,V 000 0 111 0 1 1

Vr<V V 0 0 0 1 1 l 1 10 0