Department of Computer Engineering

LAB MANUAL

DIGITAL ELECTRONICS
LABORATORY

Subject Code: 210248

Sem- First

2022 - 23
 Page Date of Date of Grade / Signature
Sr. No. Title
No. Conduction Submission Marks Staff

GROUP A
1. Realize Full Adder using
Basic gates

Design and implement Code

2.
converters-Binary to Gray and
BCD to Excess-3
3. Design and Realization of
BCD Adder using 4-bit
Binary Adder (IC 7483).

4. Realization of Boolean
Expression for suitable
combination logic using
MUX 74151 / DMUX 74154
5. Verify the truth table of two
bit comparators using logic
gates.
6. Design & Implement Parity
Generator using EX-OR.

GROUP B
7. Flip Flop Conversion: Design
and Realization

8. Design of Ripple Counter

using suitable Flip Flops

9. Realization of 3 bit Up/Down

Counter using MS JK Flip
Flop / D-FF

10. Realization of Mod -N

counter using ( 7490 and
74193 )
11. Design and implement Sequence
generator using JK flip-flop
 GROUP C
12. Learn ASM using multiplexer
controller method

This is to Certified that Mr/Miss ________________of

class __ Sem __ Roll no. __has completed the term work

satisfactorily in the subject of the Computer

Engineering Department. During the academic year _________________

Mr. S. D. Jondhale Dr. M. R. Bendre

Subject Teacher Head of Dept.
GROUP - A

0
 Assignment: 1

● Title: Design and verify truth table of full Adder using basic gates
● Objective:

1. To study combinational circuit like full adder.

2. To know about basic gates.
● Problem Statement:
To realize full adder using Basic gates

● Hardware & software requirements:

Digital Trainer Kit, IC7432, IC 7408, IC 7404, Patch Cord, + 5V Power Supply

Theory:
1. Combinational circuit.
2. Half Adder.
3. Half Subtractor.
4. Full Adder.
5. Full subtractor.

1. Combinational Circuit:- Realization steps for combinational circuit

a) Truth Table
b) K-Map.
c) MSI Circuits.

1
2. Half Adder:-

● Truth Table:-

Input Output
X Y Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

● K-Map:-

● Logic Diagram:-

2
3. Full Adder:-

● Truth Table:-

X Y Z Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

● K-Map:-

● Logic Gates:-

3
Outcomes:-

Successfully designed and implemented full Adder.

4
 Assignment No: 2

​ Title: Code Converter (Write only i and iii)

​ Objective: To learn various code & its conversion

​ Problem Statement: To Design and implement the circuit for the following 4-bit Code conversion.

i) Binary to Gray Code

ii) Gray to Binary Code
iii) BCD to Excess – 3 Code
iv) Excess-3 to BCD Code

​ Hardware & software requirements:

Digital Trainer Kit, IC 7404, IC 7432, IC 7408, IC 7486, Patch Cord, + 5V Power Supply

Theory:
There is a wide variety of binary codes used in digital systems. Some of these codes are binary-
coded- decimal (BCD), Excess-3, Gray, octal, hexadecimal, etc. Often it is required to convert from
one code to another. For example the input to a digital system may be in natural BCD and output may
be 7-segment LEDs. The digital system used may be capable of processing the data in straight binary
format. Therefore, the data has to be converted from one type of code to another type for different
purpose. The various code converters can be designed using gates.

1) Binary Code:

It is straight binary code. The binary number system (with base 2) represents values using two
symbols, typically 0 and 1.Computers call these bits as either off (0) or on (1). The binary code are
made up of only zeros and ones, and used in computers to stand for letters and digits. It is used to
represent numbers using natural or straight binary form.

It is a weighted code since a weight is assigned to every position. Various arithmetic operations can be
performed in this form. Binary code is weighted and sequential code.

2) Gray Code:

It is a modified binary code in which a decimal number is represented in binary form in such a way
that each Gray- Code number differs from the preceding and the succeeding number by a single bit.
(E.g. for decimal number 5 the equivalent Gray code is 0111 and for 6 it is 0101. These two codes
differ by only one bit position i. e. third from the left.) Whereas by using binary code there is a
possibility of change of

5
all bits if we move from one number to other in sequence (e.g. binary code for 7 is 0111 and for 8 it
is 1000). Therefore it is more useful to use Gray code in some applications than binary code.

The Gray code is a nonweighted code i.e. there are no specific weights assigned to the bit positions.

Like binary numbers, the Gray code can have any no. of bits. It is also known as reflected code.

Applications:

1. Important feature of Gray code is it exhibits only a single bit change from one code word to
the next in sequence. This property is important in many applications such as Shaft encoders where
error susceptibility increases with number of bit changes between adjacent numbers in sequence.

2. It is sometimes convenient to use the Gray code to represent the digital data converted from the
analog data (Outputs of ADC).

3. Gray codes are used in angle-measuring devices in preference to straight forward binary encoding.

4. Gray codes are widely used in K-map

The disadvantage of Gray code is that it is not good for arithmetic operation

Binary to Gray Conversion

In this conversion, the input straight binary number can easily be converted to its Gray code equivalent.

1. Record the most significant bit as it is.

2. EX-OR this bit to the next position bit, record the resultant bit.
3. Record successive EX-ORed bits until completed.
4. Convert 0011 binary to Gray.

6
Gray to Binary Conversion

1. The Gray code can be converted to binary by a reverse process.

2. Record the most significant bit as it is.
3. EX-OR binary MSB to the next bit of Gray code and record the resultant bit.
4. Continue the process until the LSB is recorded.
5. Convert 1011 Gray to Binary code.

1 0 1 1 Gray code

1 1 0 1 Binary code
(MSB) (LSB)
Fig. 2 Gray to Binary Conversion

3) BCD Code:

Binary Coded Decimal (BCD) is used to represent each of decimal digits (0 to 9) with a 4-bit binary
code. For example (23)10 is represented by 0010 0011 using BCD code rather than(10111)2 This code
is also known as 8-4-2-1 code as 8421 indicates the binary weights of four bits(23, 22, 21, 20). It is easy
to convert between BCD code numbers and the familiar decimal numbers. It is the main advantage of
this code. With four bits, sixteen numbers (0000 to 1111) can be represented, but in BCD code only 10
of these are used. The six code combinations (1010 to 1111) are not used and are invalid.

Applications: Some early computers processed BCD numbers. Arithmetic operations can be
performed using this code. Input to a digital system may be in natural BCD and output may be
7-segment LEDs.

It is observed that more number of bits are required to code a decimal number using BCD code than
using the straight binary code. However in spite of this disadvantage it is very convenient and useful
code for input and output operations in digital systems.

7
4) EXCESS-3 Code:

Excess-3, also called XS3, is a non weighted code used to express decimal numbers. It can be used for
the representation of multi-digit decimal numbers as can BCD.The code for each decimal number is
obtained by adding decimal 3 and then converting it to a 4-bit binary number. For e.g. decimal 2 is
coded as 0010
+ 0011 = 0101 in Excess-3 code.

This is self complementing code which means 1‘s complement of the coded number yields
9‘s complement of the number itself. Self complementing property of this helps considerably
in performing subtraction operation in digital systems, so this code is used for certain
arithmetic operations.

BCD To Excess – 3 Code Conversions:

Convert BCD 2 i. e. 0010 to Excess – 3 codes

For converting 4 bit BCD code to Excess – 3, add 0011 i. e. decimal 3 to the respective code using
rules of binary addition.

0010 + 0011 = 0101 – Excess – 3 code for BCD 2

Excess – 3 Code To BCD Conversion:

The 4 bit Excess-3 coded digit can be converted into BCD code by subtracting decimal value 3 i.e.
0011 from 4 bit Excess-3 digit.

e.g. Convert 4-bit Excess-3 value 0101 to equivalent BCD code.

0101-0011= 0010- BCD for 2

Design:

A) Binary to Gray Code Conversion:

1) Truth Table:

8
 Table 1 Binary to Gray Code Conversion

INPUT (BINARY CODE) OUTPUT (GRAY CODE)

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

9
2) K-Map for Reduced Boolean Expressions of Each Output:

Fig. 4 K-Map for Reduced Boolean Expressions of Each Output (Gray Code)

10
3) Circuit Diagram:

Fig. 5 Logical Circuit Diagram for Binary to Gray Code Conversion

B) Gray to Binary Code Conversion:

1) Truth Table:

Table 2 Gray to Binary Code Conversion

INPUT (GRAY CODE) OUTPUT (BINARY CODE)

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

11
0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

12
 2) K-Map for Reduced Boolean Expressions of Each Output:

Fig. 6 K-Map for Reduced Boolean Expressions of Each Output (Binary Code)

G1G0G2G3 00 01 11 10

0 0
1 1
0 0
1 1
0 0
1 1
0 0
1 1
00

01

11

10

13
B0 = G3 X-OR G2 X-OR G1 X-OR G0

14
3) Circuit Diagram:

Fig. 7
Logical Circuit Diagram for Gray to Binary Code Conversion

15
C) BCD to Excess-3 Code Conversion:

1) Truth Table:

Table 3 BCD to Excess-3 Code Conversion

INPUT (BCD CODE) OUTPUT (EXCESS-3 CODE)

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x x

16
2) K-Map for Reduced Boolean Expressions of Each Output:

Fig. 8 K-Map for Reduced Boolean Expressions Of Each Output (Excess-3 Code)

3) Circuit Diagram:

BCD TO EXCESS-3 CONVERTER

17
Fig.9 Logical Circuit Diagram for BCD to Excess-3 Code Conversion

18
D) Excess-3 to BCD Conversion:

1) Truth Table:

Table 4 Excess-3 To BCD Conversion

INPUT (EXCESS-3 CODE) OUTPUT (BCD CODE)

E3 E2 E1 E0 B3 B2 B1 B0

0 0 0 0 X X X X

0 0 0 1 X X X X

0 0 1 0 X X X X

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

1 1 0 1 X X X X

1 1 1 0 X X X X

1 1 1 1 X X X X

19
2) K-Map for Reduced Boolean Expressions of Each Output:

Fig 10 K-Map For Reduced Boolean Expressions of Each Output (BCD Code)

20
3) Circuit Diagram:

EXCESS-3 TO BCD CONVERTER

Fig.11 Logical Circuit Diagram for Excess-3 to BCD Conversion

Outcome:

Thus, we studied different codes and their conversions including

applications. The truth tables have been verified using IC 7486, 7432,

7408, and 7404.

Enhancements/modifications:

21
FAQ’s with answers:

Q.1) What is the need of code converters?

There is a wide variety of binary codes used in digital systems. Often it is required to convert from
one code to another. For example the input to a digital system may be in natural BCD and output may
be 7- segment LEDs. The digital system used may be capable of processing the data in straight binary
format. Therefore, the data has to be converted from one type of code to another type for different
purpose.

Q.2) What is Gray code?

It is a modified binary code in which a decimal number is represented in binary form in such a way
that each Gray- Code number differs from the preceding and the succeeding number by a single bit.

(e.g. for decimal number 5 the equivalent Gray code is 0111 and for 6 it is 0101. These two codes
differ by only one bit position i. e. third from the left.) It is non weighted code.

Q.3) What is the significance of Gray code?

Important feature of Gray code is it exhibits only a single bit change from one code word to the next
in sequence. Whereas by using binary code there is a possibility of change of all bits if we move from
one number to other in sequence (e.g. binary code for 7 is 0111 and for 8 it is 1000). Therefore it is
more useful to use Gray code in some applications than binary code.

Q.4) What are applications of Gray code?

1. Important feature of Gray code is it exhibits only a single bit change from one code word to
the next in sequence. This property is important in many applications such as Shaft encoders where
error susceptibility increases with number of bit changes between adjacent numbers in sequence.

22
2. It is sometimes convenient to use the Gray code to represent the digital data converted from
the analog data (Outputs of ADC).

3. Gray codes are used in angle-measuring devices in preference to straight forward binary encoding.

4. Gray codes are widely used in K-map

Q.5) What are weighted codes and non-weighted codes?

In weighted codes each digit position of number represents a specific weight. The codes 8421, 2421,
and 5211 are weighted codes.

Non weighted codes are not assigned with any weight to each digit position i.e. each digit position
within the number is not assigned a fixed value. Gray code, Excess-3 code are non-weighted code.

Q.6) Why is Excess-3 code called as self-complementing code?

Excess-3 code is called self-complementing code because 9‘s complement of a coded number can be
obtained by just complementing each bit.

Q.7) What is invalid BCD?

With four bits, sixteen numbers (0000 to 1111) can be represented, but in BCD code only 10 of these
are used as decimal numbers have only 10 digits fro 0 to 9. The six code combinations (1010 to 1111)
are not used and are invalid.

23
 Assignment No: 3

● Title: BCD Adder

● Objective: To learn different types of adder
● Problem Statement: Design and Realization of BCD Adder using 4-bit Binary Adder (IC
7483).
● Hardware and software requirement:
Digital Trainer Kit, IC 7483,7432 7408, Patch Cord ,+ 5V Power Supply

Theory:
● Carry Save Adder:

A carry save adder is just a set of one bit full adder, without any carry chaining. Therefore
n-bit CSA receivers three n-bit operands, namely A(n-1),A(0) and CIN(n-1) CIN(0)
and
Generate two n-bit result values, sum (n-1)-----------sum(0) and count(n-1) count(0).

● Carry Propagation Adder:

The parallel adder is ripple carry type in which the carry output of each full adder

stage is connected to the carry input of the next highest order stage.

Therefore, the sum and carry outputs of any stage cannot be produced until the carry occurs.
This leads to a time delay in addition process.

This is known as Carry Propagation Delay.

● BCD Adder: It is a circuit that adds two BCD digits & produces a sum of digits also in BCD.

✔ Rules for BCD addition:

1. Add two numbers using rules of Binary addition.

2. If the 4 bit sum is greater than 9 or if carry is generated then the sum is invalid. To correct the
sum add 0110 i.e. (6)10 to sum. If carry is generated from this addition add it to next higher
order BCD digit.

24
3. If the 4 bit sum is less than 9 or equal to 9 then sum is in proper form.

✔ The BCD addition can be explained with the help of following 3

cases - CASE I: Sum <= 9 & carry = 0.

Add BCD digits 3 & 4

1. 0011

+ 0100

0111

Answer is valid BCD number = (7) BCD & so 0110 is not added.

CASE II: Sum > 9 & carry = 0.

Add BCD digits 6 & 5

1. 0110

+ 0101

1011

Invalid BCD (since sum > 9) so 0110 is to be added

25
 2. 1011

+ 0110

1 0001

(1 1)BCD

Valid BCD result = (11) BCD

CASE III: Sum < = 9 & carry = 1.

Add BCD digits 9 & 9

1. 1001

+1001

10010

Invalid BCD (since Carry = 1) so 0110 is to be added

2. 1 0010
+0110

11000

(1 8)BCD
Valid BCD result = (18) BCD

26
Design of BCD adder :
1. 4 bit binary adder is used for initial addition. i.e. binary addition of two 4 bit numbers.(
with Cin = 0 ),
2. Logic circuit to sense if sum exceeds 9 or carry = 1, this digital circuit will produce
high output otherwise its output will be zero.
3. One more 4-bit adder to add (0110)2 in the sum is greater than 9 or carry is 1.

27
 INPUT OUTPUT

S3 S2 S1 S0 Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

28
K-map:-

For reduced Boolean expressions of output

Y= S3S2+S3S1

Circuit diagram:

For invalid BCD detection

29
iv) Circuit diagram for BCD adder :

30
 INPUT OUTPUT

1st Operand 2nd Operand MSD LSD

A3 A2 A1 A0 B3 B2 B1 B0 Cout S3 S2 S1 S0
(MSB) (LSB) (MSB) (LSB) (MSB) (LSB)

Thus, we studied single bit BCD adder using 4 bit parallel binary adder / 4 bit full adder the
observation table has been verified have been verified using IC 7483 & some logic gates.

Assignments Questions:

31
 Assignment No.-4

● Title: Realization of Boolean expression using 8:1 Multiplexer 74151

● Objective: To learn different techniques of designing multiplexer
● Problem Statement:
1. Verification of Functional table.
2. Verification of Sum of Product (SOP) and Product of Sum (POS) with the
help of given Boolean expression.
3. Verify the functional table using cascading of two multiplexers
4. Realization of Boolean expression using hardware reduction method for the
given equation.

● Hardware & software requirements:

Digital trainer board, IC 74151, IC 7404, IC 7432, patch cords, + 5V Power supply

Theory:
1 .What is multiplexer?
● Multiplexer is a digital switch which allows digital information
from several sources to be routed onto a single output line. Basic
multiplexer has several data inputs and a single output line.
● The selection of a particular input line is controlled by a
set of selection line.
● There are 2n input lines & n is the number of selection line whose
bit combinations determines which input is selected .It is ―Many
into One‖.
● Strobe: - It is used to enable/ disable the logic circuit OR ‗E‘ is
called as enable I/P which is generally active LOW. It is used for
cascading
● MUX is a single pole multiple way switch.
2. Necessity of multiplexer
o In most of the electronic systems, digital data is available on more
than one lines. It is necessary to route this data over a single line.
o It select one of the many I/P at a time.
o Multiplexer improves the reliability of digital system
because it reduces the number of external wire connection.

32
3. Enlist significance and advantages of Multiplexer

● It doesn‘t need K-map & logic simplification.

● The IC package count is minimized.
● It simplifies the logic design.
● In designing the combinational circuit
● It reduces the complexity & cost.
● To minimize number of connections in communication system
were we need to handle thousands of connections. Ex. Telephone
exchange.

4.Applications of MUX
● Data selector to select one out of many data I/P.
● In Data Acquisition system.
● In the D/A converter.

Multiplexer Tree
● It is nothing but construction of more number of line using
less number of lines.
● It is possible to expand the range of inputs for multiplexers beyond
the available Range in the integrated circuits. This can be
accomplished by interconnecting several multiplexers.

8:1 MUX:
The block diagram of 8:1 MUX & its TT is shown. It has eight
data I/P & one enable input, three select lines and one O/P.

Operating principle:
When the Strobe or Enable input is active low, we can select any
one of eight data I/P and connect to O/P.

Design:

33
Draw the connection diagram of multiplexer to verify the functional table.

SELECTION STROBE
LINES OUTPUTS

C B A E Y Y
X X X 1 0 1
0 0 0 0 D0 D0
0 0 1 0 D1 D1
0 1 0 0 D2 D2
0 1 1 0 D3 D3
1 0 0 0 D4 D4
1 0 1 0 D5 D5
1 1 0 0 D6 D6
1 1 1 0 D7 D7

X = don’t care condition.

Part 1: MUX as a function generator.

Convert the given Boolean expression into standard SOP / POS format if required and
complete the logic diagram design accordingly for realization of the same.

i) As an example:

34
 Function = Sum of Product
(SOP) Y = ∑m (1, 2, 3, 4, 5, 6,
7)

SELECTION STROBE
LINES OUTPUTS

C B A Y Y
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 0 1 0
1 0 0 0 1 0
1 0 1 0 1 0
1 1 0 0 1 0
1 1 1 0 1 0

SOP realization Diagram

SOP Y = ∑m (1, 2, 3, 4, 5, 6, 7)

Solution:-Since there are 3 variable, the multiplexer have 3 select I/P should be
used. Hence one 8:1 mux should be used.
Ste p 1:-Identify the number decimal corresponding to each minterm.
Here 1,2,3,4,5,6,7
Step 2:-Connect the data input lines 1,2,3,4,5,6,7 to logic 1(+Vcc) & remaining input
line 0 to logic 0(GND)
Step 3:-Connect variables A, B & C to select input.

35
 ii) As an example
Function = Product of Sum
(POS)
Y = ∏ M (0, 5, 6, 7)

SELECTION STROBE
LINES OUTPUTS

C B A Y Y
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 0 1 0
1 0 0 0 1 0
1 0 1 0 0 1
1 1 0 0 0 1
1 1 1 0 0 1

POS realization exp:

1. As there are 3 i/p so use 8:1 MUX
2. Connect the given min terms to GND and else decimal numbers to logic1(+VCC).

36
POS realization Diagram

POS Y = ∏ M (0, 5, 6, 7)

Part -2: Implementation of 16:1 MUX using 8:1 MUX

Use hardware reduction method and implement the given Boolean expression with the
help of neat logic diagram. (N-circle Method)

First Method: F(A,B,C,D) = ∑m ( 2, 4, 5, 7, 10, 14 )

i. *Bold and red marks represent the minterms

ii. Consider B,C,D as a select line
iii. Use NOT gate to obtain A and complement of it.

37
 Solution:-
Step 1:- Apply B, C, D to select I/P & design table(Implementation
table). Step 2: Encircle those min terms which are present in output.
Step 3: If the min terms in a column are not circled then apply
logic 0. Step 4: If the min terms in a column are circled then apply
logic 1.
Step 5: If only min term in 2nd row is encircled then ‗A‘ should be
applied to that data input. Hence apply ‗A‘ to D6.

Step 6: If only min term in 1st row is encircled then ‗ ‘ should be

applied to that data input. Hence apply ‗ ‘ to D4, D5, D7.

16:1 MUX using 8:1 MUX Diagram

38
39
Part-3 Implementation of 16:1 MUX using two 8:1 MUX (Cascading Method)

F(A,B,C,D)= ∑m(2, 4, 5, 7, 10, 14)

Solution:-

Step 1: Connect S2, S1, S0 select lines of two 8:1 MUX parallel where as
MSB select input is used for enabling MUX.

Step 2: S3 is connected directly to the enable (E) to mux-2 where as is

connect to enable input of mux-1
Step 3: The output of two MUX are OR to get final output.

40
Truth table: - PART_3

Final
Select line Output Output

S3 S2 S1 S0 Y1 Y2 Y
0 0 0 0 D0 -- D0
0 0 0 1 D1 -- D1
0 0 1 0 D2 -- D2
0 0 1 1 D3 -- D3
0 1 0 0 D4 -- D4
0 1 0 1 D5 -- D5
0 1 1 0 D6 -- D6
1 1 1 1 D7 -- D7
1 0 0 0 -- D8 D8
1 0 0 1 -- D9 D9
1 0 1 0 -- D10 D10
1 0 1 1 -- D11 D11
1 1 0 0 -- D12 D12
1 1 0 1 -- D13 D13
1 1 1 0 -- D14 D14
1 1 1 1 -- D15 D15

Truth Table for 16:1 MUX using two 8:1 MUX

P
in
Diagra
mIC
74151

8:1 mux

41
Multiplexer Tree according to given equation:-

Outcome:

Multiplexer is used as a data selector to select one out of many data inputs.
It is used for simplification of logic design.
It is used to design combinational circuit.
Use of multiplexer minimizes no. of connections.
FAQ:
.
1. Enlist applications of MUX

🡺1. MUX is used as data selector.

2. It is used to design combinational circuit.

42
 3. Less number of wires required which reduces complexity
4. There is no need to design k-map
5. We design equation using truth table.

2. Define the terms Encoder and Decoder

🡺Encoders are used to encode given digital number into different numbering
format .like decimal to BCD Encoder, Octal to Binary.

🡺Decoders are used to decode a coded binary word like BCD to seven segment decoder. Thus
encoder and decoder are application specific logic develop, we cannot use any type of input
for any encoder and decoder.

Assignments Questions:

43
 Assignment No: 5

​ Title: - Comparators

​ Objective: - 1 bit, 2 bit Comparator.

​ Problem Statement: To verify truth table of 1 bit and 2 bit comparator using logic

gate and comparator IC.

​ Hardware & Software Requirement’s :

Digital Trainer Kit, Comparator IC-7485, patch cords, +5V power supply.

Theory:

Another common and very useful combinational logic circuit is that of the Digital
Comparator circuit. Digital or Binary Comparators are made up from standard AND, NOR
and NOT gates that compare the digital signals present at their input terminals and produce
an output depending upon the condition of those inputs.

For example, along with being able to add and subtract binary numbers we need to be able to
compare them and determine whether the value of input A is greater than, smaller than or
equal to the value at input B etc. The digital comparator accomplishes this using several logic
gates that operate on the principles of Boolean algebra. There are two main types of Digital
Comparator available and these are

1. Identity Comparator – an Identity Comparator is a digital comparator that has only

one output terminal for when A = B either ―HIGH‖ A = B = 1 or ―LOW‖ A = B = 0

​ 2. Magnitude Comparator – a Magnitude Comparator is a digital comparator which

has three output terminals, one each for equality, A = B greater than, A > B and less
than A < B.

The purpose of a Digital Comparator is to compare a set of variables or unknown numbers,

for example A (A1, A2, A3… An, etc) against that of a constant or unknown value such as B
(B1, B2, B3… Bn, etc) and produce an output condition or flag depending upon the result of
the comparison. For example, a magnitude comparator of two 1-bits, (A and B) inputs would
produce the following three output conditions when compared to each other. Which means: A
is greater than B, A is equal to B, and A is less than B

44
This is useful if we want to compare two variables and want to produce an output when any
of the above three conditions are achieved. For example, produce an output from a counter
when a certain count number is reached. Consider the simple 1-bit comparator below

1. 1-bit comparator

​ Truth Table:-
Inputs Outputs
B A A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
​ K-Map

45
 ​ Logic Diagram of 1 bit Comparator

2 Bit Comparator:-

● Truth Table:-

46
● K-map :-

1. For A>B:

2. For A=B

3. For A<B :-

47
● Circuit Diagram:-

48
 ● For n bit Comparator :-

Digital comparators actually use Exclusive-NOR gates within their design for comparing
their respective pairs of bits. When we are comparing two binary or BCD values or variables
against each other, we are comparing the ―magnitude‖ of these values, a logic ―0‖ against a
logic ―1‖ which is where the term Magnitude Comparator comes from.

As well as comparing individual bits, we can design larger bit comparators by cascading
together n of these and produce a n-bit comparator just as we did for the n-bit adder in the
previous tutorial. Multi-bit comparators can be constructed to compare whole binary or BCD
words to produce an output if one word is larger, equal to or less than the other.

Outcome:
Up and down counters are successfully implemented, the comparators are studied &
o/p are checked. The truth table is verified.

Assignments Questions:

49
 Assignment: 6

● Title: Parity Generator and Parity Checker.

● Objective: Learn Even/Odd parity Generator/Checker using logic gates
● Problem Statement: Design & Implement Parity Generator using EX-OR
● Hardware & software requirement: Digital Trainer Kit, IC 7486 (Ex-OR), IC
7404 (NOT), IC 74180, Patch Cord ,+ 5V Power Supply

Theory:
In digital communication, the digital data is sent over the telephone lines using
different binary codes.

During the transmission, because of ―noise‖(i.e: Unwanted voltage fluctuation)

, signal 0 may become 1 or 1 may become 0 and wrong information (i.e: corrupted data ) may
be received at the destination and must be resent.

This problem of communication is overcome by using Error-detecting code.

To detect these errors, Parity Bit is usually transmitted along with the data bits.

At the receiving end, parity will be checked.

Parity: A term used to specify the number of one‘s in a digital word as odd or even.

There are two types of Parity - even and odd.

Even Parity Generator will produce a logic 1 at its output if the data word contains an odd
number of ones. If the data word contains an even number of ones then the output of the
parity generator will be low. By concatenating the Parity bit to the data word, a word will be
formed which always has an even number of ones i.e. has even parity.

Parity bit: An extra bit attached to a binary word to make the parity of resultant word even
or odd. Parity bits are extra signals which are added to a data word to enable error checking.

Definition:- 2 A check bit appended to an array of binary digit to make the sum of all binary
digits.

Parity generator: A logic circuit that generates an additional bit which when appended to a
digital word makes its parity as desired (odd or even).

o Parity generators calculate the parity of data packets and add a parity amount to them.

50
o Parity is used on communication links (e.g. Modem lines) and is often included in
memory systems.

Parity checker: At the receiving end a logic circuit is used to check the parity of received
information, and determines whether the error is included in the message or not.

Even bit Parity Code: The total number of ones in parity code word is even.

Odd bit Parity Code: The total number of ones in parity code word is odd.

The single parity bit code can detect the single bit error. If error is more than 1 bit, it is not
possible to detect the error.

Eg:- 1) Assume the even parity code word is sent by the transmitter is 10111, the
code word received by the receiver is 10011.

The parity of received code word is odd, it shows that one bit error is introduced over
the channel.

Eg:- 2) But if the received code word is 10001, the parity of received code is even and
shows that there is no error introduced over the channel.

Actually two bits are changed over the path.

Limitations: -

1) The one bit parity code word can detect one bit error.

2) It cannot detect the location of error and hence error cannot be corrected

A) Even Parity Generator:

1) Truth Table:

51
 INPUT OUTPUT
B2 B1 B0 P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

2) K-Map For Reduced Boolean Expressions Of Output:

B1B0 00 01 11 10

0 0
1 11

0 0
1 11

B2

P = B2 (EX-OR) B1 (EX-OR) B0

52
3) Circuit Diagram:

Even parity generator:

Even parity generator O/p P = B2 (EX-OR) B1 (EX-OR) B0

B) Odd Parity Generator:

1) Truth Table:

INPUT OUTPUT
B2 B1 B0 P
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

53
 2) K-Map For Reduced Boolean Expressions Of Output:

00 01 11 10
B1B0

0 0
1 1

0 0
1 1
B2

P = B2 (EX-NOR) B1 (EX-NOR) B0

3) Circuit Diagram:
Odd parity generator:

54
Odd parity generator O/p P = B2 (EX-NOR) B1 (EX-NOR) B0

55
C) Even Parity Detector:
1) Truth Table:

0– Error
1– No Error

INPUT OUTPUT
P
Parit B2 B1 B0 PEC
y Bit

0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

56
 2) K-Map For Reduced Boolean Expressions Of Output:

1 0 1 0

0 1 0 1

1 0 1 0

0 0
1 1
B1B0
PB 00 01 11 10

00

01

11

10

PEC = P (EX- NOR) B2 (EX- NOR) B1 (EX- NOR) B0

3) Circuit Diagram:
Even parity detector:

57
Even parity detector O/p: PEC = P (EX- NOR) B2 (EX- NOR) B1 (EX- NOR) B0

58
d) Odd Parity Detector:
1) Truth Table:
0– Error
1– No Error

INPUT OUTPUT
P
Parit B2 B1 B0 PEC
y Bit

0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

59
 2) K-Map For Reduced Boolean Expressions Of Output:

B1B0
PB 00 01 11 10

00

01

11

10

PEC = P (EX- OR) B2 (EX- OR) B1 (EX- OR) B0

3) Circuit Diagram:
Odd parity detector:
P
(MS
B)

B2

B1

B0 7486N

Odd parity detector O/p:

PEC = P (EX- OR) B2
(EX- OR) B1 (EX- OR)
B0
Outcome: Thus, we
studied parity generator /
checker and their working
& limitation
60
(O/P)

61
62
GROUP – B

63
 Assignment No: 7

​ Title: Flip-flop.--- Write any two Flip Flop conversions others for study purpose

​ Objective: Conversion of Flip-flop.

​ Problem Statement: Conversion from one type of flip-flop to another type of flip-flop.
.
​ Hardware & Software Requirement’s :

Digital Trainer Kit, IC 7476, IC 7474, IC 7408, IC 7432 & IC 7404.patch cords, +5V
power supply.

Theory:

A Flip – flop is an electronic device which is having two stable states and a feedback
path which is used to store 1 – bit of information by using the clock signal as input. Latches
are also used to do the same task except that they do not use a clock signal. Hence to say it
simply, ―Flip
– flops are clocked latches‖. They are used to store only 1 – bit of information and it
can remain in the same state until the clock signal affects the state of the input.

There are four types of flip – flops

● SR flip – flop
● D flip – flop
● JK flip – flop
● T flip-flop

Generally, JK flip – flops and D flip – flops are the most widely used flip – flops. And so
their availability in the form of integrated circuits (IC‘s) is abundant. Numerous varieties of
JK flip – flop and D flip – flop are available in the semiconductor market. The less popular
SR flip – flop and T flip – flop are not available in the market as integrated circuits (IC‘s)
(even though a very few number of SR flip – flops are available as IC‘s, they are not
frequently used).

There might be a situation where the less popular flip – flops are required in order to
implement a logic circuit. In order use the less popular flip – flops, we will convert one type
of flip – flop into another. Some of the most common flip – flop conversions are:-

1. SR Flip – flop to JK Flip – flop

2. SR Flip – flop to D Flip – flop
3. SR Flip – flop to T Flip – flop
4. JK Flip – flop to SR Flip – flop
5. JK Flip – flop to D Flip – flop

64
 6. JK Flip – flop to T Flip – flop
7. D Flip – flop to SR Flip – flop
8. D Flip – flop to JK Flip – flop
9. D Flip-flop to T Flip-flop

​ General model used to convert one type of FF to other

In order to convert one flip – flop to other type of flip – flop, we should design a
combinational circuit that is connected to the actual flip – flop. Inputs to combinational
circuit are same as the inputs of the desired flip – flop. Outputs of combinational circuit are
same as the inputs of the available flip – flop. So the output of combinational circuit is
connected to the input of our available flip – flop. The pictorial representation of the same
is shown below.

1. SR Flip – flop to JK Flip – flop

Here we are required to convert the SR flip – flop to JK flip – flop. So first we design a
combinational circuit with J and K as its inputs and we connect its output to the input of
our available flip flop i.e. an SR flip – flop. So its outputs are same as that of JK flip – flop.

Let‘s write a truth table for the two inputs, J and K. For two inputs along with the QP, we get
8 possible combinations in truth table. Consider that when the two inputs are applied, QP is
the present state and QN is the next state. For every combination of J, K , QP , we find the
corresponding QN state. Here QN will give the state values that to which the output of the JK
flip
– flop will jump after the present state, on applying the inputs. Now we write all the
combinations of S and R in the truth table to get each QN value from corresponding QP.
Hence these are the values of S and R that are used to change the state of flip flop from QP
to QN.

65
The conversion table:-

From SR flip – flop to JK flip – flop is shown below.

F/F PRESENT NEXT OUTPUTS

INPUTS STATE STATE

J K Qn Qn+1 S R

0 0 0 0 0 X

0 1 0 0 0 X

1 0 0 1 1 0

1 1 0 1 1 0

0 1 1 0 0 1

1 1 1 0 0 1

0 0 1 1 X 0

1 0 1 1 X 0

In order to deduce the Boolean equations of S and R in terms of J and K, we use Karnaugh
maps from the above table.

The K – map:-

The Boolean equation for S is S = JQP

66
.K map :-

The Boolean equation for R is R = KQP.

The Boolean equations of S and R in terms of J, K and QP are: S = JQ‘P and R = KQP

The logic diagram:-

JK flip – flop implemented from SR flip – flop is shown below. Here J and K are external
inputs to the circuit. S and R are the outputs of the designed combinational outputs.

2. SR Flip – flop to D Flip – flop

Converting the SR flip – flop to D flip – flop involves connecting the Data input (D) to the
SR flip – flop. Here the Data input is connected directly to the S input and the inverted D
input (using a NOT gate) is connected to R input. The same can be derived from truth table
and corresponding K – maps. S and R are the inputs of the flip – flop while QP and QP‘ are the
present state and its complementary outputs of the flip – flop. We should design a
combinational circuit such that its input is D and outputs are S and R. Outputs from the
combinational circuit S and R are connected as inputs to the SR flip – flop.

The truth table for conversion of SR flip – flop to D flip – flop is shown below. The truth
table is drawn for the D input and QP output to find the corresponding QN output.

67
The conversion table:-

F/F PRESENT NEXT OUTPUTS

INPUTS STATE STATE

D Qn Qn+1 S R

0 0 0 0 X

1 0 1 1 0

0 1 0 0 1

1 1 1 X 0

The K – map:-

The Boolean equation of S is S = D.

The K – map:-

The Boolean equation of R is R = D.

68
The Boolean equation for S and R in terms of D are: S = D and R = D. The logic diagram of
implementation of D flip – flop from SR flip – flop is shown below.

The logic diagram:-

3. SR Flip – flop to T Flip – flop

The combinational circuit required in order to convert an SR flip – flop to T flip – flop can be
constructed from the truth table. The input to the combinational circuit is T (Toggle input)
and the outputs of the combinational circuit are S and R. Here S and R are the inputs of the
actual flip
– flop. The output and the complement output of the flip – flop are QP and Q‘P. The
truth table consists of combinations of T and QP in order to get QN where QN is the next state
output of the flip – flop. The combinations of S and R which results in QN are also tabulated
in the same table.

The conversion table:-

F/F PRESENT NEXT OUTPUT

STATE STATE
INPUT

T Qn Qn+1 S R

0 0 0 0 X

1 0 1 1 0

1 1 0 1 0

0 1 1 X 0

69
The K – map:-

The Boolean equation of S is S = TQP.

The K – map:-

The Boolean equation for R is R = TQP.

The Boolean equations of S and R are: S = TQP and R = TQP. The logic circuit for the
implementation of T flip – flop from SR flip – flop is shown below.

The logic diagram:-

70
JK Flip – flop to other Flip – flops

4. JK Flip – flop to SR Flip – flop

To convert the JK flip – flop into SR flip – flop, we design a combinational circuit with S and
R as its inputs and J and K as its outputs. Here J and K are the inputs of actual flip – flop. So
for making this conversion, we should obtain the J &amp, K values in terms of S, R and QP.
Consider that when the two inputs S and R are applied, QP is the present state output and QN is
the next state output. For each combination of S, R and QP, we find the corresponding QN
state. Now, we prepare a truth table for the possible combination of the inputs S, R and QP.
We can make 8 possible combinations for the two S and R inputs along with QP. For each
combination of S and R inputs and QP we find the corresponding value of QN. Now we write
all the values of J and K in the truth table to get each QN value from corresponding QP. In SR
flip – flop, when the 2 inputs are high i.e. S = 1 & R = 1,

The conversion table:-

F/F INPUTS PRESENT NEXT OUT PUT

STATE STATE

S R Qn Qn+1 J K

0 0 0 0 0 X

0 1 0 0 0 X

1 0 0 1 1 X

1 0 0 1 1 X

0 1 1 0 X 1

0 1 1 0 X 1

0 0 1 1 X 0

1 0 1 1 X 0

71
 The K – map:-

The Boolean equation for J is J = S.

The K – map:-

The Boolean equation for K is K = R.

The Boolean equations for J and K in terms of S and R are: J = S and K = R. Hence, there is
no requirement of any additional combinational circuit as S and R inputs are same as J and K
inputs. The logic circuit of implementing SR flip – flop from JK flip – flop is shown below.

The logic diagram:-

72
 5. JK Flip – flop to D Flip – flop

Converting the JK flip – flop to D flip – flop, involves in connecting the Data input (D) to the
JK flip – flop through a combinational circuit. Here the Data input is connected directly to
the J input and the inverted D input (using a NOT gate) is connected to K input.

The design of the combinational circuit should be in such a way that D is its input and J & K
are its outputs. The outputs of the combinational circuit J & K are connected as inputs to the
flip – flop. QP is the present state output of the flip – flop. Q‘P is its complementary and QN
is the next state output. The truth table for converting JK flip – flop to D flip – flop is shown
below.

The conversion table:-

The K – maps in order to solve for J and K in terms of D and QP are shown below.

F/F PRESENT NEXT OUTPUTS

INPUTS STATE STATE

D Qn Qn+1 J K

0 0 0 X 0

1 0 1 X 1

0 1 0 0 X

1 1 1 1 X

K – Map:-

The Boolean equation for J is J = D.

73
K – Map:-

The Boolean equation for K is K = D.

The Boolean equations for J and K are J = D and K = D‘. The logic diagram that represents the
implementation of D flip – flop from JK flip – flop is shown below.

The logic diagram:-

6. JK Flip – flop to T Flip – flop

Converting the JK flip – flop to T flip flop, involves in connecting the Toggle input (T)
directly to the J and K inputs. So toggle (T) will be the external input to the combinational
circuit. Its output is connected to the Input of actual flip – flop (JK flip – flop).

We prepare a truth table by considering 4 possible combinations of the Toggle input (T) along
with QP. QP and QP‘ are the present state output and its complement output of the flip – flop.
QN is the next state output. The truth table is drawn for the T input and QP output to find the
corresponding QN output. The truth table is shown below.

74
The conversion table:-

F/F PRESENT NEXT OUTPUT

STATE STATE
INPUT

T Qn Qn+1 J K

0 0 0 0 X

1 0 1 1 X

1 1 0 X 1

0 1 1 X 0

The K – map:-

The Boolean equation for J is J = T.

The K – map:-

The Boolean equation for K is K = T.

75
The logic circuit for converting JK flip – flop to T flip – flop is shown below.

The logic diagram:-

D Flip – flop to other Flip – flops

I). D Flip – flop to SR Flip – flop

To convert the D flip – flop into SR flip – flop, a combinational circuit should be constructed
where its inputs are S and R and its output is D. Here Data (D) is the input of actual flip –
flop. The truth table is drawn with the 8 possible combinations of the two inputs S & R and
QP. QP and QP‘ are the present state and its complement outputs of the flip – flop.

When the two inputs of SR flip – flop are high i.e. S = 1 and R = 1, then the QP value is
invalid and hence the Data (D) inputs for the corresponding QP‘s are considered as ‗Don‘t
cares‘.
The truth table for S, R and QP in order to get QN is shown below. It also consists of D inputs
in order to get the same QN.

76
The Conversion Tabel:-

F/F INPUT PRESENT NEXT OUT

STATE STATE PUT

S R Qn Qn+1 D

0 0 0 0 0

0 1 0 0 0

1 0 0 1 1

0 1 1 0 0

0 0 1 1 1

1 0 1 1 1

The K – map for solving the equation of D in terms of S, R and QP.

K MAP:-

The Boolean equation of D is D = S + RQP.

The logic diagram using this equation to implement an SR flip – flop from D flip – flop is
shown below.

77
The logic diagram:-

II). D Flip – flop to JK Flip – flop

When we need to convert the D flip – flop into JK flip – flop, J and K are the inputs of the
combinational circuit with D as its output. Here Data (D) is the input of actual flip – flop.
The truth table is drawn with the 8 possible combinations of the two inputs J & K along with
QP. QP and QP‘ are the present state and its complement outputs of the flip – flop.The truth
table consists of combinations of J, K and QP in order to get QN. Here QN is the next state
output of the flip – flop. The truth table also consists of D inputs that lead to QN output.

The conversion table:-

78
 F/F INPUT PRESENT STATE NEXT STATE OUT PUT

J K Qn Qn+1 D

0 0 0 0 0

0 1 0 0 0

1 0 0 1 1

1 1 0 1 1

0 1 1 0 0

1 1 1 0 0

0 0 1 1 1

1 0 1 1 1

The K – map:-

D = JQ‘P + K‘QP.

The Boolean equation of D deduced from the above K – map is the logical
representation of implementing JK flip – flop from D flip – flop is shown below.

79
The logic diagram:-

III). D Flip – flop to T Flip – flop

When we need to convert the D flip – flop into T flip – flop, T (Toggle input) is the input of
the combinational circuit with D as its output. Here Data (D) is the input of actual flip – flop.
The truth table is drawn with the 4 possible combinations of the input T along with QP. QP and
QP‘ are the present state and its complement outputs of the flip – flop.

The truth table consists of combinations of T and QP in order to get QN. Here QN is the next
state output of the flip – flop. The truth table also consists of D inputs that lead to QN output.

The conversion table is shown below.

The Conversion Table:-

80
 F/F PRESENT NEXT OUTPUT
STATE STATE
INPUT

T Qn Qn+1 D

0 0 0 0

1 0 1 1

1 1 0 0

0 1 1 1

The K – map:-

D = TQP + TQP.

The Boolean equation of D in terms of T and QP is The logic circuit for implementing T
flip – flop with D flip – flop is shown below.

The logic diagram:-

81
Application of Flip-flop: 1. Elimination of keyboard de-bounce.
2. As a memory element.
3. In a various types of Registers.
4. In counters/timers.
5. As a delay element.

Outcomes: Successfully implement the conversion of flip-flop.

University Asked Conversions:

1. SR Flip – flop to JK Flip – flop
2. SR Flip – flop to D Flip – flop
3. SR Flip – flop to T Flip – flop
4. JK Flip – flop to SR Flip – flop
5. JK Flip – flop to D Flip – flop
6. JK Flip – flop to T Flip – flop

82
 Assignment No: 8

​ Title: Ripple Counter

​ Objective: Ripple up and down counter using IC 7476

​ Problem statement: To design and implement 3 bit UP, Down, Ripple Counter using

JK Flip-flop.
​ Hardware & software requirements:
IC 7476 (MS-JK Flip-flop), Digital Trainer Kit, patch cords, +5V power supply.

Theory:

1) Asynchronous counter:

A digital counter is a set of flip flop. An Asynchronous counter uses T flip flop
to perform a counting function. The actual hardware used is usually J-K flip-flop connected
to logic 1.
In ripple counter, the first flip-flop is clocked by the external clock pulse &
then each successive flip-flop is clocked by the Q or /Q‘ output the previous flip-flop.
Therefore in an asynchronous counter the flip-flop are not clocked simultaneously. The input
of MS-JK is connected to VCC because when both inputs are one output is toggled. As MS-JK
is negative edge triggered at each high to low transition the next flip-flop is triggered. On
this basis the design is done for MOD-8 counter.

2) Up Counter:

Fig 1 shows 3 bit Asynchronous Up Counter. Here Flip-flop A act as a

MSB Flip-flop and Flip-flop C can act as a LSB Flip-flop. Clock pulse is connected to the
Clock of flip-flop C. Output of Flip-flop C (Qc) is connected to clock of next flip-flop(i.e.
Flip-flop B) and so on. As soon as clock pulse changes out put is going to -change(at the
negative edge of clock pulse) as a Up count sequence. For 3 bit Up counter Truth table is as
shown below.

3) Down Counter:

Fig 2 shows 3 bit Asynchronous Down Counter. Here Flip-flop a act

as a MSB Flip-flop and Flip-flop C can act as a LSB Flip-flop. Clock pulse is connected to
the Clock of flip-flop C. Output of Flip-flop C (Qc‘) is connected to clock of next flip- flop
(i.e. Flip-flop B) and so on. As soon as clock pulse changes output is going to change (at
the negative edge of clock pulse) as a down count sequence. For 3 bit down counter Truth
table is as shown below.

83
 In both the counters Inputs J and K are connected to Vcc, hence J-K Flip flop can work in
toggle mode. Preset and Clear both are connected to logic 1.

⮚ Truth Table:

Counter States F/F Output

QA QB QC
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Up Counter Down Counter
Counter States F/F Output
QA QB QC
7 1 1 1
6 1 1 0
5 1 0 1
4 1 0 1
3 0 1 1
2 0 1 0
1 0 0 1
0 0 0 0
⮚ Logic diagram:

84
 Fig 1:
3 Bit Asynchronous Up Counter

85
 Fig 2: 3 Bit Asynchronous Down Counter

Timing Diagram:

1. 3 Bit Asynchronous Up Counter

2. 3 Bit Asynchronous Down Counter:

86
 ⮚ Uses:

Outcomes: Thus, we implemented up and down ripple counter. Using IC 7476

Enhancements/modifications:
As the design part is done for the 3 bit Counter, we can implement the same for 4 bit counter.

FAQ’s with answers:

​ What do you mean by Counter?

A Counter is a register capable of counting the no. of clock pulses arriving at Its clock-
inputs. Count represents the no. of clock pulses arrived. A specified sequence of states
appears as the counter output.

​ What are the types of Counters? Explain each.

There are two types of counters as Asynchronous Counter and Synchronous Counter.

87
Asynchronous Counter: In this counter, the first flip-flop is clocked by the external clock
pulse and then each successive flip-flop is clocked by the Q or Q‘ o/p of the previous
flip-flop. Hence in Asynchronous Counter flip-flops are not clocked simultaneously and
hence called as Ripple Counter.
Synchronous Counter: In this counter, the common clock input is connected to all the flip-
flops simultaneously.

​ What are the problems involved in Ripple Counter?

There are two problems in Ripple Counter as

i. Glitch
ii. Propagation delay of flip-flop.

​ Why asynchronous counters are called as ripple counters?

In asynchronous counter the first flip-flop is clocked by the external clock pulse & then
each successive flip-flop is clocked by the Q or /Q‘ output of the previous flip-flop i.e. clock
(pulses) applied ripple from stage to stage to stage (LSB to MSB) hence asynchronous
counters are called as ripple counters.

​ What do you mean by pre-settable counters?

A counter in which starting state is not zero can be designed by making use of the
Preset inputs of the flip flops. This is referred to as loading the counter asynchronously.
This is referred to as pre-settable counter.

​ What are the applications of asynchronous counters?

Digital clock
Frequency divider circuits

​ Whether frequency division takes place in asynchronous counters?

Yes. In counter, the signal at the output of last flip flop (i.e. MSB) will have a
frequency equal to the input clock frequency divided by the MOD number of the
counter.

​ Can n- bit up asynchronous counter will act as n- bit down asynchronous

counter without changing the position of the clock?

Yes. Instead of taking output of a counter from uncomplimentary output (Q), if we take
it from complimentary output (Q bar), the same counter circuit will work as down counter.

Assignments Questions:
88
 Assignment No: 09(a)

​ Title: Synchronous counter

​ Objective: 3 Bit up/down synchronous Counter

​ Problem Statement: To design and implement 3 bit UP and Down, Controlled

UP/Down Synchronous Counter using MS-JK Flip-flop.

​ Hardware & Software Requirement’s :

Digital Trainer Kit, IC 7476, IC 7408, IC 7432 & IC 7404.patch cords, +5V power supply.

Theory:

Counters: counters are logical device or registers capable of counting the no of states or no
of clock pulse arriving at its clock input where clock is a timing parameter arriving at regular
intervals of time, so counters can be also used to measure time & frequencies. They are made
up of flip flops. Where the pulse are counted to be made of it goes up step by step & the o/p
of counter in the flip flop is decoded to read the count to its starting step after counting n
pulse incase of module & counters.

⮚ Synchronous Counter:

In this counter, all the flip flops receive the external clock pulse simultaneously.

Ex:- Ring counter & Johnson counter

The gates propagation delay at reset time will not be present or we

may say will not occur.

⮚ Classification of synchronous counter:

Depending on the way in which counting processes, the

synchronous counter is classified is :-

1) Up counter.
2) Down counter.
3) Up down counter.

● Up Counter:

89
 The up counter counts binary form 0 to7 i.e.(000 to 111).It counts from small
to large number. It‘s O/P goes on increasing as they receive clock pulse

● Down Counter:
This down counter counts binary from 7-0 i.e.(111-000).It counts from large
to small number. It‘s O/P goes on increasing as they receive clock pulse

▪ Excitation Table:- The tabular representation of the

operation of flip flop (i.e: Operational Characteristic)

Present State Next State J K

0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

For M = 0, it acts as an Up counter and for M =1 as an Down counter.

State Table for 3 bit Up-Down Synchronous Counter:

Control Present State Next State Input for Flip-flop

input M QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA
0 0 0 0 0 0 1 0 X 0 X 1 X
0 0 0 1 0 1 0 0 X 1 X X 1
0 0 1 0 0 1 1 0 X X 0 1 X
0 0 1 1 1 0 0 1 X X 1 X 1
0 1 0 0 1 0 1 X 0 0 X 1 X
0 1 0 1 1 1 0 X 0 1 X X 1
0 1 1 0 1 1 1 X 0 X 0 1 X
0 1 1 1 0 0 0 X 1 X 1 X 1
1 0 0 0 1 1 1 1 X 1 X X 1
1 0 0 1 0 0 0 0 X 0 X 1 X
1 0 1 0 0 0 1 0 X X 1 X 1
1 0 1 1 0 1 0 0 X X 0 1 X
1 1 0 0 0 1 1 X 1 1 X X 1
1 1 0 1 1 0 0 X 0 0 X 1 X
1 1 1 0 1 0 1 X 0 X 1 X 1
1 1 1 1 1 1 0 X 0 X 0 1 X

K- map Simplification:

90
 QBQA
MQC 00 01 11 10
00 1 X X 1
01 1 X X 1
11 1 X X 1
10 1 X X 1

QBQA 00 01 11 10
MQC
00 X 1 1 X
01 X 1 1 X
11 X 1 1 X
10 X 1 1 X

JA = 1 KA = 1

QBQA 00 01 11 10
MQC
00 0 1 X X
01 0 1 X X
11 1 0 X X
10 1 0 X X

QBQA
MQC 00 01 11 10
00 X X 1 0
01 X X 1 0
11 X X 0 1
10 X X 0 1

JB = M QA + M QA KB = M QA + M QA

QBQA
MQC 00 01 11 10
00 0 0 1 0
 01 X X X X
11 X X X X
10 1 X 0 0

QBQA
MQC 00 01 11 10
00 X X X X
01 0 0 1 0
11 1 0 0 0
10 X X X X

JC = M QA QB + M QA QB KC = M QA QB + M QA QB

QA QB QC

Fig : Logical Diagram of Up down counter using JK Flip Flop

Uses:
2) The synchronous counter is specially used as the counting devices.
3) They are also used as counter to count the no of clock pulses applied.
4) It also works for counting frequency & is used in frequency divider circuit.
5) It is used in digital voltmeter.
6) It is also used in counter type A to D converter.
7) It is also used for time measurement.
8) It is also used in digital triangular wave generator.
 9) It helps in counting the no of product coming out from machinery where product
is coming out at equal interval of time.

Outcome:
Up and down counters are successfully implemented, the counters are studied & o/p
are checked. The truth table is verified.

Enhancements/modifications:
As the design part is done for the 3 bit Counter, we can implement the same for 4 bit counter.
Assignments Questions:

FAQ’s with answers:

● What do you mean by Counter?
A Counter is a register capable of counting the no. of clock pulses arriving at its
 clock inputs. Count represents the no. of clock pulses arrived. A specified
sequence of states appears as the counter output.
● What are the types of Counters? Explain each.
There are two types of counters as Asynchronous Counter and Synchronous
Counter. Asynchronous Counter: In this counter, the first flip-flop is clocked by the
external clock pulse and then each successive flip-flop is clocked by the Q or Q‘
o/p of the previous flip-flop. Hence in Asynchronous Counter flip-flops are not
clocked simultaneously and hence called as Ripple Counter.
Synchronous Counter: In this counter, the common clock input is connected to
all the flip-flops simultaneously.

​ What do you mean by pre-settable counters?

A counter in which starting state is not zero can be designed by making use of the
preset inputs of the flip flops. This is referred to as loading the counter
asynchronously. This is referred to as pre-settable counter.

​ What are the applications of synchronous counters?

Digital clock
Frequency divider
circuits Frequency
counters
Used in analog to digital converters

​ What are the advantages of synchronous counters over asynchronous counters?

Propagation delay time is reduced

Can operate at a much higher frequency than the asynchronous counters.

​ Ring counter is an example of synchronous counters or asynchronous counter?

Synchronous counter. Since all the flip flops are clocked simultaneously.

​ Twisted Ring (Johnson’s) counter is an example of synchronous

counters or asynchronous counter?

Synchronous counter. Since all the flip flops are clocked simultaneously.

​ What is the difference between ring counter and twisted ring counter?

In ring counter pulses to be counted are applied to a counter , it goes from state to state
and the output of the flip flop s in the counter is decoded to read the count. Here the
 uncomplimentary output (Q) of last flip flop is fed back as an input to first flip flop.
Ring counters are referred as MOD ‗N‘ counters.
But in Twisted ring counter the complimentary output (Q bar) of last flip flop is fed
back as an input to first flip flop. Twisted Ring counters are referred as MOD ‗2N‘
counters.

​ What are the applications of ring counters?

Ring counter outputs are sequential non-overlapping pulses which are useful for control
state counters,
Used in stepper motor, which requires pulses to rotate it from one position to the
next. Used as divide by ‗N‘ ((MOD ‗N‘) counters.

​ What are the applications of ring counter twisted ring counters?

Used as divide by ‗2N‘ ((MOD ‗2N‘)

counters. Used for control state counters.
Used for generation of multiphase clock.

​ List the Synchronous Counter ICs.

IC 74160 : Decade Up Counter

IC 74161 : 4 bit binary Up
Counter IC 74162 : Decade Up
Counter
IC 74163 : 4 bit binary Up
Counter IC 74168 : Decade Up/Down
Counter
IC 74169 : 4 bit Binary Up/Down
Counter IC 74190 : Decade Up/Down
Counter
IC 74191 : 4 bit Binary Up/Down
Counter IC 74192 : Decade Up/Down
Counter
IC 74193 : 4 bit Binary Up/Down Counter
 Assignment: 10

● Title: Ripple Counter

● Objective: Modulo N counter using 7490(N>10).

● Problem Statement: Realization of mod N counter using IC 7490.
● Hardware & software requirements:
Digital Trainer Kit, 7490 (Decade Counter IC), Patch Cord, + 5V Power Supply
Theory:
Ripple counter IC-7490 (decade counter): i.e .having various name like
mod-n counter, decade counter ,BCD counter.
IC-7490 is a TTL MSI decade counter. It contains four master slave flip flops
and additional gating to provide a divide-by-two counter and a three stage
binary counter which provides a divide by 5 counter.

Fig.1 The Basic internal structure of IC 7490

Conclusion:

1. If both the reset input Ro(1) & Ro(2) are at logic 1 then all the flip-flop will be reset and
the output is given by
QD QC QB QA = 0000
 2. If both the reset input R9(1) & R9(2) are at logic 1 then the counter output is set to
decimal 9.
QD QC QB QA = 1001
3. If any one pin of Ro(1) & Ro(2) and one of R9(1) & R9(2) are at low, then the
counter will be in counting mode.
The reset/count function table of IC7490 is shown in table 1.

Table 1:-Reset/count truth table

Reset inputs Output
R0(1) R0(2) R9(0) R9(1) QD QC QB QA
1 1 0 X 0 0 0 0
1 1 X 0 0 0 0 0
X X 1 1 1 0 0 1
X 0 X 0 COUNTER
0 X 0 X COUNTER
0 X X 0 COUNTER
X 0 0 x COUNTER

IC 7490 is MOD-10 or decade counter. It is a 14 pin IC with the pin configuration as

shown in fig:
 Fig. 2 Pin configuration of IC7490.

Table 2:-Pin name and description of IC 7490

Pin name Description

Input B This is clock input to the internal MOD-5 ripple counter, which is negative
edge triggered.
R0(1),R0(2) Gated zero reset inputs
R9(1),R9(2) These are gated set to nine inputs
QD,QC,QB Output of internal MOD-5 counter with QD as MSB.
QA Output of internal MOD-2 counter with QA as LSB.
Input A Clock input to FF-A which is negative edge triggered.
Decade Counter Operation :
1. The output of MOD-2 is externally connected to the input B which is the clock
input of the internal MOD-5 counter.
2. Hence QA toggles on every falling edge of clock input whereas the output
QD,QC,QB of the MOD-5 counter will increment from 000 to 100 on low going change of
QA output.
3. Due to cascading of MOD-2 and MOD-5 counter, the overall configuration becomes
a MOD- 10 i.e. decade counter.
4. The reset inputs Ro(1), Ro(2) and preset inputs R9(1), R9(2) are connected to
ground so as to make them inactive.

Table: Summarizes the opération of the 7490 as décade counter

O/p of MOD-5 O/p of MOD-2 CLK Count
QD QC QB QA
0 0 0 0 0 0
0 0 0 1 1 1
0 0 1 0 2 2
0 0 1 1 3 3
0 1 0 0 4 4
0 1 0 1 5 5
0 1 1 0 6 6
0 1 1 1 7 7
1 0 0 0 8 8
1 0 0 1 9 9
Implémentations:
Realization of MOD 10 counter using IC 7490
 Fig 3.MOD-10 counter using IC 7490

Timing diagram of mod10:

Application Of IC 7490:
 1. Symmetrical Bi- quinary divide by ten counter.

Outcomes:
Thus, we implemented divide by two (MOD-2) and divide by 5 (MOD-5) counter.
Using IC7490.

Assignments Questions:
1. Design using counter using 7490.
1) MOD-27
2) MOD-17
3) MOD-24
4) MOD-20
5) MOD-7
6) MOD- 98
7) MOD -97
8) MOD -45
9) MOD-56
 Assignment N0. – 11

AIM : To design and implement sequence generator with and without bushing

using IC 7476.

OBJECTIVE : To understand sequence generator, one of the sequential circuit.

IC’s USED : IC 7476(Dual JK), 7408 (AND-gate), 7432 (OR-gate).

THEORY :
A sequential circuit which generates a prescribed sequence of bits in synchronism
with a clock is referred to as a sequence generator. These pulse trains or sequence of bits can
be used to open valves, close gates, turn on lights, and turn off machines and other variety of
jobs.

For the design of sequence generator, we first determine the required no. of flip flops
and the logic circuit for the next state decoder.

No. of flip flops required to generate particular sequence can be determined as follows.

1) Find the no. of 1‘s in the sequence.

2) Find the no. of 0‘s in the sequence.
3) Take the maximum out of two.
4) If N is the required no. of flip flops, choose minimum value of ‗n‘ to satisfy equation
given below.
Max (0‘s , 1‘s) ≤ 2n-1

The sequence generator can be

classified as

1) sequence generator without bushing

2) sequence generator with bushing

The aim in this experiment is to design a sequence generator to generate a sequence of bit
i.e. 10101.

For finding the no. of flip flops we use the formula

m≤2n-1

where m= maximum count and

n= no. of flip flops required.

 For the given sequence no. of 1‘s=3 no. of 0‘s=2, so minimum value of n which satisfies
above relation is 3. Once the no. of flip flops are decided we have to assign unique states
corresponding to each bit in the given sequence such that flip flop representing least
significant bit generates the given sequence ( usually the o/p of flip flop representing the least
significant bit is used to generate the given sequence)

Design -

For the sequence of bits 10101 we require three flip flops as calculated above. The State
Diagram, state assignment for this problem is shown below. Where we will use the o/p FF 0
i.e. o/p of first flip flop Q0 as a sequence of bits & assign unique states corresponding to each
bit in the sequence as shown in state assignment table.

1. Sequence Generator Without Bushing: State

assignment table :

Q2 Q1 Q0 STATES

0 0 1 1

0 0 0 0

0 1 1 3

0 1 0 2

1 0 1 5

State Diagram :-

State table :
 Present states Next states Flip flop input

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 1 1 0 X 1 X 1 X

0 0 1 0 0 0 0 X 0 X X 1

0 1 0 1 0 1 1 X X 1 1 X

0 1 1 0 1 0 0 X X 0 X 1

1 0 0 X X X X X X X X X

1 0 1 0 0 1 X 1 0 X X 0

1 1 0 X X X X X X X X X

1 1 1 X X X X X X X X X

K-Map simplification:

1) For J0 –

00 01 11 10

1 X X 1

X X X X

J0 = 1
2) For K0 –
00 01 11 10

X 1 1 X

X 0 X X

K0 = Q2

3) For J1 –
00 01 11 10

1 0 X X

X 0 X X

J1 = Q0

3) For K1 –
00 01 11 10

X X 0 1

X X X X

K1 = Q0
3) For J2–
00 01 11 10

0 0 0 1

X X X X

J2 = Q1Q0

3) For J1 –
00 01 11 10

X X X X

X 1 X X

K2 = 1
 Logic Diagram-

Clk

Q0(LSB) Q1 Q2(MSB)

Hardware requirements:

GATE ICs Quantity

JK F/F 7476 2

AND 7408 1
 1. Sequence Generator with Bushing :-

The state assignment for this is shown below as we have seen during designing of sequence
generator without using bushing we will have the output ‗C‘ i.e. the output of first Flip-Flop is a
sequence generator of bits and assign unique states corresponding to each bit in the sequence out
with bushing means we have to use unassigned states also that is 4,6,7.

State – Assignment Table :-

Q2 Q1 Q0 STATES

0 0 1 1

0 0 0 0

0 1 1 3

0 1 0 2

1 0 1 5

State Diagram-
State Table :-

Present state Next state Flip flop inputs

Q2 Q1 Q0 Q2 Q1 Q0 J0 K0 J1 K1 J2 K2

0 0 0 0 1 1 1 X 1 X 0 X

0 0 1 0 0 0 X 1 0 X 0 X

0 1 0 1 0 1 1 X X 1 1 X

0 1 1 0 1 0 X 1 X 0 0 X

1 0 0 0 0 0 0 X 0 X X 1

1 0 1 0 0 1 X 0 0 X X 1

1 1 0 0 0 0 0 X X 1 X 1

1 1 1 0 0 0 X 1 X 1 X 1

K Map Simplification :

For J0 –
00 01 11 1
0

1 X X 1

0 X X 0

J0 = Q2
 3) For K0 –

00 01 11 10
0
X 1 1 X

X 0 1 X

K
0
3) For J1 – =
Q
2
+
Q
1

00 01 11 10

1 0 X X
3) For K1 –
0 0 X X

J
1
=
Q
2
3) For J2– Q
0

00 01 11 10

X X 0 1

X X 1 1

3) For J1 – K
1
=
Q
2
+
Q
0
 00 01 11 10

0 0 0 1

X X X X

J
2
=
Q
1
Q
0
 00 01 11 10

X X X X

1 1 1 1

K2 = 1

Logic Diagram

vcc

Q0 (LSB) Q1 Q2 (MSB)
4) Hardware requirements:

GATE ICs Quantity

JK F/F 7476 2

AND 7408 1

OR 7432 1

Conclusion: In this way sequence generator with & without bushing is studied and implemented.

Enhancements / Modifications – Sequence generator can also be implemented with shift

register instead of flip flops. Use IC 7495 universal shift register IC and try to implement
sequence generator.

FAQs :

1. What is sequential logic circuit?

A sequential logic circuit consists of a memory elements in

addition to combinational circuit. Its output at any instant of time

depends upon the present input as well as present state of memory

element.

2. What is meant by delay line?

It is used to introduce time delays in digital signals.

3. What is meant by following terms

a) Synchronous preset b) Asynchronous preset

c) Synchronous clear d) Asynchronous clear

● a)Preset operation is synchronised with the clock

 ● b)Preset operation is independent of the clock
● c) clear is performed in synchronous with clock
● d) clear is performed independent with clock
4. Is asynchronous counter faster than synchronous counter ?
In a synchronous counter the time required for change of any state is same and is
equal to delay time of one flip flop where as in asynchronous counter all flip flops
are not clocked simultaneously, hence time required is not same.

5. What is mean by lockout in counter?

In a counter design for a fewer state than the maximum possible state some time it
may so happen that counter enters in unused state and goes from one unused state
to another unused state and never comes to used state.

6. What is mean by state table?

It consists of complete information about present state and next state and outputs
of a sequential system.

7. What is mean by state diagram?

The information available in a state table can be represented as graphically. the
graphical representation is known as state diagram.

8. What is the advantage of state reduction in the design of sequential

circuit? It reduces the number of flip flops

9. What is meant by excitation table?

This gives information about what should be the flip flop inputs if outputs are
specified before and after the clock pulse.

10. How many flip flops are required to design sequence generator using
Counters: max (0‘S,1‘S) in a given sequence <= 2(N - 1)

Where, N = Number of flip flops

11. How many flip flops are required to design sequence generator using shift
registers: S<= 2N - 1
 Where, N=Number of flip

flops S= Length of

sequence

12. What is Lock out condition? How it is avoided?

When counter enters into one of the invalid state and after application of

pulses remains in invalid states only i. e. counter gets locked into invalid

state & this is called as lock out. Lock out can be avoided by providing

bushing to all the invalid states in such a way that after application of one

or more clock pulses counter will fall into one of the valid state.
GROUP - C
 Assignment No - 12

● Title: Simple ASM using

● Objective: Learn multiplexer controller method
● Problem Statement : Design of 2 bit Up counter using multiplexer controller method
1. 2 bit counter has 4 states i.e. 00,01,10,11.
2. In the state diagram if mode control M =0, counter will be latched in the same state
and will start incrementing to the next state if M=1.
3. By referring the state diagram, ASM chart is drawn.

● Hardware & software requirements: Digital Trainer Kit, 74151(8:1 MUX), 7474
(D Flip-flop), Power supply, Patch Cord.

Theory:
1. ASM chart means algorithmic state machine chart.
2. It is a type of flowchart that can be used to represent the state transitions and
generated outputs for finite state machine(FSM)
3. ASM charts are similar to traditional flowcharts.
4. Unlike a traditional flowchart, this includes timing information. This chart specifies
that the FSM flows from one state to another only after each active clock edge.

● Elements used in ASM Chart

1. State Box- A rectangle represents a state of the FSM. It is equivalent to node in the
state diagram or row in the state table. The name of the state should be indicated
outside the box in left top corner. Moore type of outputs is listed inside the box.

2. Decision Box- A diamond indicates that the stated condition expression has to be
tested and an exit path has to be chosen accordingly. The condition expression
consists of one or many inputs.

3. Conditional output Box- The oval denotes the output signals that are of Mealy type.
These output depend on the values of state variables and the Inputs of FSM .the
condition that determines whether such Outputs are generated is specified in a
decision box.

These are shown in the figure given below.

State Name

Conditional output box

Decision Box
State Box

Significance : It is an aid to design the complex circuits.ASM charts are used to describe
complex circuits that include one or more FSM‘s and another circuitry such as
registers,counters,adders,multipliers,etc.

ASM Block

1. It is a structure which consists of single state box and any decision and conditional
output boxes that the state box may be connected to.
2. It has one entrance and any number of exit paths.

Each block describes the state of the system during the interval of one clock pulse.
Multiplexer controller method of design has three levels of components as shown in the
figure below:

ASM using Multiplexer controller Method:-

1. The multiplexer outputs are applied to the input of the flip-flop forming the register at
the second level to hold the present state inputs.
2. The multiplexers decide the next state of the register as outputs of MUX has been
connected to flip-flop inputs.
3. Third level is the decoder which provides separate output for each control state. The
decoder can be replaced by the combinational circuit.
 First level (Multiplexers)
S
e
c
o
n
d
l
e
v
e
l
(
R
e
g
i
s
t
e
r
)

MUX Output Third

level
(Decod
er)

O
MUX
u
Inputs
t
p
u
t

MUX Output

Holds the
present
binary
state

Fig. Block schematic for a 3-level scheme for multiplexer design

State diagram:- for 2 bit Up counter:

0 0
 0

Fig. 1 State Diagram for 2 bit Up Counter

ASM chart of the above state diagram is as shown below in Fig.2
 Fig.2 ASM Chart for 2-bit Up Counter

State transition table:

Mode control Present state (Qn) Next state (Q n+1)
i/p
M Qb Qa Qb+1 Q a+1
0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
0 1 1 1 1
1 0 0 0 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 0

Excitation table for D Flip-flop:

Present State Next state Input

Qn Qn+1 Dn
0 0 0
0 1 1
1 0 0
1 1 1

State Table :

Mode Present Next state (Qn+1) Input

control state (Qn)
i/p
M Qb Qa Qb+1 Q a+1 Db Da
0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 1 0 1 0
0 1 1 1 1 1 1
1 0 0 0 1 0 1
1 0 1 1 0 1 0
1 1 0 1 1 1 1
1 1 1 0 0 0 0

Logic Diagram:
 ASM Using MUX

+VCC

Y1

Mode (M)

+VCC

Y2

Clock

Fig. Logic Diagram

Outcome: ASM chart is drawn as per the state diagram and verified the
functionality of given FSM using multiplexer controller method.

FAQ’s:
 1. What is meaning of ASM and FSM

ASM is algorithmic state machine chart.It is a method to implement FSM. It is a type of

flowchart that can be used to represent the state transitions and generated outputs for finite
state machine (FSM).

A finite state machine (FSM) or finite state automaton (plural: automata) or simply a state
machine, is a model of behavior composed of a finite number of states, transitions between
those states, and actions. A finite state machine is an abstract model of a machine with a
primitive internal memory.

2. What is the major difference between ASM chart and traditional flowchart?

ASM charts are similar to traditional flowcharts. Unlike a traditional flowchart, this includes
timing information. This chart specifies that the FSM flows from one state to another only
after each active clock edge.

3. Write the significance of ASM chart in the design of FSM.

It is an aid to design the complex circuits. ASM charts are used to describe complex circuits
that include one or more FSM‘s and another circuitary such as registers, counters, adders,
multipliers etc.

Assignments Questions: