TRIBHUVAN UNIVERSITY

INSTITUTE OF ENGINEERING
THAPATHALI CAMPUS

Basic Electronics Engineering-EX451

Chapter 6: Digital Electronics
Presented By
Er. Ganesh Kumal
Department of Electronics & Computer Engineering
IOE ,Thapathali Campus

January 14, 2024

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 Contents
6.1 Number system: Binary arithmetic
6.2 Logic gates: OR, NOT, AND, NAND, XOR, XNOR
gate, Truth tables
6.3 Multiplexer, Demux, Encoder, Decoder
6.4 Logic function representation
6.5 Combinational circuits: SOP, POS form, K-map
6.6 Latch, flip-flop, S-R flip-flop, JK master slave
flip-flop, D-flip-flop
6.7 Sequential circuits, Generic block diagram,
shift registers, counters

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 Number System
• If base or radix of a number system is ‘r’, then the digits
present in that number system are ranging from zero to
r-1.
• The total digits present in that number system is ‘r’. So,
we will get various number systems, by choosing the
values of radix as greater than or equal to two.
• The following number systems are the most commonly
used.
1. Decimal Number system
2. Binary Number system
3. Octal Number system
4. Hexadecimal Number system
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 Decimal Number
• The decimal number system has 10 digits
• These are : 0, 1, 2, 3, 4, 5, 6, 7, 8, 9.
• Decimal number system has the base = 10
102 101 100.10 -1 10 -2 10 -3……
Decimal point
Example 1: 47= 4 x 101 + 7 x 100
= 40 + 7 = 47
Example 2: (568.23)10
= 5 x 102 + 6 x 101 + 8 x 100.2 x 10-1 + 3 x 10-2
= 500 + 60 +8 + 0.2 + 0.3
= 568.23
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 Binary Number
• The binary number system has two digits
(bits). ‘0’ or ‘1’ = bit
Group of 4-bits = Nibble
• These are: 0, 1. Group of 8-bits = Byte

• The binary number system has the base = 2

22 21 20.2 -1 2 -2 2 -3……
binary point
The weights of a bit
(1101.011)2 = (1 × 23) + (1 × 22) + (0 × 21) + (1 × 20)
increases from right to + (0 × 2-1) + (1 × 2-2) + (1 × 2-3)
left in a binary number
system
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 Octal Number System
• The octal number system has 8 digits.
• These are: 0, 1, 2, 3, 4, 5, 6, 7.
• The base of octal system has 8.
82 81 80.8 -1 8 -2 8 -3……
Octal point
Mathematically, we can write it as
(1457.236)8= (1 × 83) + (4 × 82) + (5 × 81) + (7 × 80) + (2 × 8-1)
+ (3 × 8-2) + (6 × 8-3)

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 Hexadecimal Number System
• The hexadecimal system has 16 digits.
• These are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and F.
• The base of hexadecimal system has 16.

162 161 160. 16 -1 16 -2 16 -3……

hexadecimal point
Mathematically, we can write it as
(1A05.2C4)16= (1 × 163) + (10 × 162) + (0 × 161) + (5 × 160)
+ (2 × 16-1) + (12 × 16-2) + (4 × 16-3)

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Decimal Binary Octal Hexadecimal
0 0000 0 0
1 0001 1 1
Decimal Binary
2 0010 2 2
0 0 0 0
3 0011 3 3
1 0 0 1
4 0100 4 4
2 0 1 0
5 0101 5 5
3 0 1 1
6 0110 6 6
4 1 0 0
7 0111 7 7
5 1 0 1
8 1000 10 8
6 1 1 0
9 1001 11 9
7 1 1 1
10 1010 12 A
11 1011 13 B
12 1100 14 C Table: 3-bit binary system

13 1101 15 D
14 1110 16 E
15 1111 17 F
Table: NumberPrepared
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 Number Conversion System
1. Decimal to Other Base System
i. Divide the decimal number to be converted by the value
of the new base.
ii. Get the remainder from step (i) as the rightmost digit
(least significant digit) of new base number.
iii. Divide the quotient by the base.
iv. Record the remainder from step (iii) as the next digit (to
the left) of the new base.
 Repeat step (iii) and (iv) getting remainders from right
to left until the quotient becomes zero in step (iii).
The last remainder obtained will be the MSD of the
new base.

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 Decimal to Binary Conversion
Example
Decimal to Binary Conversion: (25.692)10  (?)2

(25.692)10 = (11001.1011)2

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Decimal to Octal Conversion:
(239.513)10  (?)8

0.513 X 8 = 4.104 4
7 0.104 X 8 = 0.832 0
0. 832 X 8 = 6.656 6
0. 656 X 8 = 5.248 5
0.248 X 8 = 1.984 1
Read down

(239.513)10 = (357.40651)8

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Decimal to Hexadecimal Conversion
(3479.342)10 = ( ? )16
0.342 x 16 = 5.472 5
0.472 x 16 = 7.552 7
0.552 x 16 = 8.832 8
0.832 x 16 = 13.312 D
Read down

(3479.342)10 = (D97.578D)16

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 2. Other Base System to Decimal
System
i. Determine the column (positional) value of
each digit. This depends on the position of
the digit and the base of the number system.
ii. Multiply the obtained column value (in step i)
by the digits in the corresponding column.
iii. Sum the products calculated in step (ii). The
total is the equivalent value in decimal.

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 Example
Binary to Decimal: (11011001.1011)2  (?)10

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 Hexadecimal to Decimal

Convert base 5 to decimal system

(234)5 = (…?…)10
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 3.Other Base System to Non-decimal
System
i. Convert the original number to a decimal
number (base 10).
ii. Convert the decimal number so obtained to
the new base number.
Example:
• Binary to Octal and vice-versa.
• Binary to Hexadecimal and vice-versa.

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Octal to Hex Conversion

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 Binary Arithmetic
• Binary arithmetic is essential part of all the digital computers and many
other digital systems.
Binary Addition
• It is a key for binary subtraction, multiplication and division. There are
four rules of binary addition:
Table 2.2 : Truth Table of Binary Addition
Example:

• In fourth case, a binary addition is creating a sum of (1 + 1= 10), i.e. 0 is

written in the given column and a carry of 1 over to the next column.

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 Binary Subtraction
• Difference and borrow, these two Example:
terms will be used very
frequently in the binary
subtraction. There are four rules
of binary subtraction:
Table 6.5: truth Table of Binary
Subtraction

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 Binary Multiplication
• Binary multiplication is similar to
decimal multiplication. It is simpler
than decimal multiplication because
only 0s and 1s are involved. There are
four rules for binary multiplication.
Table 6.6: Truth Table of Binary
Multiplication

Binary Division: Binary division is similar to

decimal division.

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 Octal Addition
• Following octal addition table will help you to
handle octal addition: Example:
Octal Addition

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Hexa-decimal Addition/Subtraction
Addition Subtraction

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Hexadecimal Addition/Subtraction
Addition Subtraction

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 Complements
• Complements are used in the digital
computers in order to simplify the subtraction
operation and for the logical manipulation.
• There are two types of complements:
– Radix complement (r’s complement)
– Diminished complement ( r-1)’s complement

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 Binary Complement
1’s Complement 2’s Complement
• The 2’s complement of binary number
• 1’s complement of a
is obtained by adding 1 to the least
number is found by significant bit (LSB) of the 1’s
changing all 1’s to 0’s and complement.
0’s to 1’s. • 2’s complement = 1’s complement + 1

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 1’s complement subtraction

• Subtracting smaller
number from larger one,
the method is as follows:
– Determine 1’s complement
of the smaller one.
– Add 1’s complement of the
smaller one to the larger
one.
– Remove the carry and add When subtracting larger number from
it to the result. The carry is smaller one, there is no carry and the
called end around carry. result is in 1’s complement form and
opposite sign (negative).

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 2’s Complement Subtraction
• For subtracting a smaller • Example:
number from larger one, • Subtract (1001)2 from (1100)2,
the method is as follows: by 2’s complement method.
– Find the 2’s complement of 1100
the smaller number.
– Add 2’s complement to the 2’s comp. of 1001 + 0111
larger one. End around carry 10011
– Discard carry. Result= 11
When subtracting larger discard carry
number from smaller one,
there is no carry and the Class work: Subtract by 2’s complement
result is in 2’s complement method.
form and opposite sign i. (111)2 from (1000)2
(negative).
ii. (1110)2 from (1000)2

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 Binary Codes
• Classification of Binary codes
– Weighted code
– Non-weighted code
Weighted Code
 Weighted binary codes obey the positional weight
principle.
 Each position of the number represents specific
weight. Several systems of the codes are used to
express the decimal digit 0 through 9. In these codes,
each decimal digit is represented by a group of 4 bits.
 Example: BCD Code,

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 Non-weighted Code
Non-weighted Code
• In this type of binary codes, the positional
weights are not assigned.
• The examples of non-weighted codes are: Excess-
3 code and Gray code.
Excess-3 code
• Non -weighted code to express decimal number.
• The Excess-3 code words are derived from the
8421 (BCD) code words adding (011)2 to each
code word in 8421.
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 Binary Coded Decimal (BCD) or 8421
Code
• Each decimal digit is represented by a 4-bit binary
number.
• In the BCD, with 4-bits we can represent 16 numbers
(0000 to 1111).
• But in BCD code only first 10 numbers of these are
used (0000 to 1001).
• The remaining six code combinations (1010 to 1111)
are invalid in BCD.

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Decimal number Binary number Binary Coded Decimal(BCD)

0 0000 0000
1 0001 0001
2 0010 0010
3 0011 0011
4 0100 0100 Valid in Binary
5 0101 0101
6 0110 0110
7 0111 0111
8 1000 1000
9 1001 1001
10 1010 0001 0000
11 1011 0001 0001
12 1100 Invalid in BCD 0001 0010 Invalid in Binary
13 1101 0001 0011
14 1110 0001 0100
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15 1111 0001 0101
BCD Addition

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 Excess-3 Code
The Excess-3 code is obtained as follows:
Decimal number  8421 code + (011)2  Ex-3 code

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 Decimal to Ex-3 and vice-versa
• Decimal to Ex-3 • Excess-3 to Decimal
i. Convert each decimal i. Subtract 3 from each
digit to equivalent BCD 4-bit of Ex-3 to get BCD
ii. Add 3 (0011) to each ii. Convert each BCD to
BCD code. equivalent decimal.

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 Gray Code (Reflected Code)
• It is non-weighted code, so no specific weight assigned to the bit position.
• It has very special feature that, only one bit will change each time the
decimal number is incremented.

Table 2.3:Binary and Gray Code

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 Gray to Binary and Binary to Gray
Conversion
Gray to Binary Conversion Binary to Gray Conversion

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 Basic Gates and Equivalent
• Logic gates are the basic building blocks of any
digital system.
• It is an electronic circuit having one or more
than one input and only one output.
• The relationship between the input and the
output is based on a certain logic.
• Based on this, logic gates are named as AND
gate, OR gate, NOT gate etc.

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 Types of Logic Gates
• Basic gates
o AND Gates
o OR gates
o NOT gates
• Derived Gates
o NAND : AND+NOT
o NOR: OR+NOT
o EX-OR: for input A and B, the Ex-OR is A’B + AB’ which can
be derived from AND, OR and NOT gates
o EX-NOR: EX-OR + NOT = A’B’ + AB

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 Logic Gates

Y= A Y=A’

Y=A.B Y= A + B Y= A  B

Y =(A + B)’ Y= (A  B)’

Y = (A . B)’

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 X-OR and X-NOR Implemented by
Basic Gates
X-NOR = A  B = A’B’ +AB

X-OR = A  B = A’B + AB’

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3-Inputs Logic Gates

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Waveform Representation of Logic
Gates

Task for student: Try for other gates

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 Positive and Negative Logic
+ve logic
Higher voltage correspond to logic ‘1’
• + 5V  logic ‘1’ Example:
Logic ‘0’  -5V
• 0 V  logic ‘0’ Logic ‘1’  0 V
-ve logic
Higher voltage correspond to logic ‘0’
• + 5V  logic ‘0’ Example:
Logic ‘1’  -5V
• 0 V  logic ‘1’ Logic ‘0’  0 V

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 Example
+ve logic AND gate -ve logic AND gate
0 0 0 1 1 1
0 1 0 1 0 1
1 0 0 0 1 1
1 1 1 0 0 0

-ve logic OR gate +ve logic OR gate

1 1 1 0 0 0
0 1 1
1 0 0
1 0 1
0 1 0
1 1 1
0 0 0

+ve logic AND gate = -ve OR gate +ve logic OR gate = -ve logic AND gate
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 74XX series IC for digital logic
Number Description
7400 Quad two-input NAND gate (four NAND
gates)

7402 Quad two-input NOR gate (four NOR

gates)
7404 Hex inverter (six NOT gates)

7408 Quad two-input AND gate (four AND

gates)
7432 Quad two-input OR gate (four OR gates)

7486 Quad two-input XOR gate (four XOR

gates)

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 De-morgan’s Theorem
• ( X + Y + …..)’ = X’ . Y’ . …….
The complement of sum of variables is equal
to product of complement of each variables.
• (X.Y….)’ = X’ + Y’ + ….
The complement of product of variables is
equal to sum of each variables complement.

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 Cont…

Figure 2.1: Circuit diagram of de-morgan’s law

(A + B)’ = A’.B’ (A .B)’ = A’ + B’

Table 2.1: Truth table of De-morgan’s law
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 Laws of Boolean Algebra
Some of important Boolean laws are:
1. Commutative law
a) A+B=B+A b) A.B = B.A
2. Associative law
a) A.(B.C) = (A.B).C b) A + (B + C) = (A + B) + C
3. Distributive law
a) A.(B + C)= AB + AC
4. AND law
a) A.0 = 0 b) A.1= A c) A.A = A d) A.A’= 0
5. OR law
a) A+0=A b) A + 1 = 1 c) A + A = A d) A+ A’ = 1
6. Inversion law
a) A’’ = A

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 Verification of Laws
Commutative law Distributive law

A.(B + C)= AB + AC

A B A.B B.A A+B B+A A B C A.B A.C B+C AB+AC A(B+C)

0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 1 1 0 0 1 0 0 1 0 0
1 0 0 0 1 1 0 1 0 0 0 1 0 0
1 1 1 1 1 1 0 1 1 0 0 1 0 0
1 0 0 0 0 0 0 0
1 0 1 0 1 0 0 0
1 1 0 1 0 0 0 0
1 1 1 1 1 1 1 1

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Basic Rules of Boolean Algebra

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 Universal Gates (NAND and NOR)
Universal Gates
• NOR and NAND gates are referred to as
universal gates. This is so because by making a
combination of only NANDs, all other logic
gates (NOT, OR, AND, NOR, X-OR and X-NOR)
can be realized. Similarly, by utilizing a
combination of only NORs, all other logic
gates (NOT, AND, OR NAND, X-OR and X-NOR)
can be realized.

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Realization of NOT Gate by NAND only
Steps:
• Write equation of gate to be realized i.e. NOT
gate.
Y=A
• Use different laws to make the equation
derivable to universal gate equation i.e. NAND
Y = A.A = A ; AND law
• Now draw the circuit.

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 OR Gate Realized by NAND
Steps:
• First write equation of gate to be realized
i.e. OR
Y=A+B
• Make the equation comparable to NAND gate
using inversion and De morgan’s law
• Y=A+B A
A
• Y=A.B A.B

B
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B 56
 AND Gate Realized by NAND
• Implementing AND Using only NAND Gates: The AND is replaced by a
NAND gate with its output complemented by a NAND gate inverter.

X.Y X.Y

Implementing NOR Using only NAND Gates: The NOR gate is replaced by a NAND
gate by complemented output of NOR gate implemented by NAND gates.

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 Implementing X-OR and X-NOR Using
NAND Gates
• Implementing X-OR Using only • Implementing X-NOR Using only
NAND Gates: NAND Gates
• F = A’B + AB’ • F = A’B’ + AB
• F” = (A’B + AB’)” • F” = (A’B’ + AB)”
• F = [(A’B)’ . (AB’)’]’ • F = [(A’B’)’ . (AB)’]’

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 NOR Gate as Universal Gate
• Implementing an Inverter Using only NOR Gate: All NOR input pins
connect to the input signal A gives an output A’.

• Implementing OR Using only NOR Gates: The OR is replaced by a NOR

gate with its output complemented by a NORS gate inverter.

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AND and NAND Gates implemented by
NOR Gates
• Implementing AND Using only • Implementing NAND Using only NOR
NOR Gates: The AND gate is Gates: The NAND gate is replaced by a
replaced by a NOR gates with all NOR gates by complemented output
its inputs complemented by NOR of AND gate implemented by NOR
gate inverters. gates.

Assignment: Implement X-OR and X-NOR gate by NOR Gate

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Boolean Expression Representation
• Any logic expression may be expressed in two
standard forms:
1) Sum of Products (SOP) Form
Sum ( Logical OR )

Y = AB + BC + CA
Product terms ( ANDing of variables)

2) Product of Sum (POS) Form

Product
Y = ( A + B) . ( B + C) . ( A + C)
Sum Terms
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 Sum of Products (SOP)
• SOP is a group of product terms summed together.
• A standard product term is only product expression that
contains all input variables.
• Input variable is complemented when its value is 0 and
uncomplemented when its value is 1.
• Standard product terms are known as “min-terms” and
designated by a small m.

F = ABC + ABC + ABC

F= AB + BCD + AC
Figure 3.1: Prepared
Sum of By:products
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 Product of Sum (POS)
• When two or more sum terms are ANDing, the resulting
expression is a product of sum (POS).
• A standard sum term is only sum expression that contains all
input variables.
• Input variable is complemented when its value is 1 and
uncomplemented when its value is 0.
• Standard sum terms are known as “max-terms” and
designated by a capital M.
F = (B + C + D’) (A + C + D’) (C’ + D)

Figure 3.2: POS

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 Min-terms and Max-terms
Min-terms
• Each individual term in
standard SOP
expression is called as
min-term.
Max-term
• Each individual term in
standard POS
expression is called as
Table 3.1: Max-term and Min-term
max-term. representation

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 How to write SOP and POS forms for a
given truth table
The procedure to be followed for writing the standard SOP expression is as under:
1) first, we consider only those combinations of inputs which correspond to Y = 1
2) Then we write a product term for each such combination.
3) Lastly, we OR all these product terms to get the standard SOP form.

The procedure to be followed for writing the standard POS expression is as under:
1) first, we consider only those combinations of inputs which correspond to Y = 0
2) Then we write the Maxterms for each such combination.
3) Lastly, we AND all these Maxterms to get the standard POS form.

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 Min-term and Max-term
Inputs Output
A B C Y
0 0 0 0 Y (A, B, C) = m (1, 3, 5, 7)
0 0 1 1 F = A’B’C + A’BC + AB’C + ABC
0 1 0 0
Y (A, B, C) = M (0, 2, 4, 6)
0 1 1 1 F = (A+ B + C) (A + B’ +C) ( A’ + B +C)
1 0 0 0 ( A’ + B’ +C)

1 0 1 1
1 1 0 0
1 1 1 1
Table 3.2: Truth table of 3-bit standard min-terms and max-terms
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 Standard SOP Form
• Standard SOP expression means all the
variables appear in each product term.
 F = ABCD + ABCD + ABCD
• Standard SOP expression are important in:
 Constructing truth table
 The Karnaugh map simplification method

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 D + D’ = 1

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 Converting POS to Standard POS Form
Given ,
F(A, B, C)=

A.A’ = 0
A + BC = (A + B) (A + C)
( A + B + C.C’) (A.A’ + B + C)

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 Simplification of SOP and POS Using
Boolean Algebra
• Boolean function (SOP or POS form) can be simplified
by using two methods:
i. Boolean Algebra
ii. Karnaugh map method
• By using Boolean algebra
 Use postulates, theorems, boolean laws and some
relationship : A + A’B = A + B
A + AB = A
A + BC = ( A + B) (A +C)
 This method relies on your algebraic skill.

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 Three points remember for
Simplification
1. Grouping
2. Multiplication by redundant variables
3. Application of Demorgan’s law
Example 1: A + AB + BC Example 3: F= [(AB’C)’ + (ACD)’ + BC’ ]’
= A (1 + B) + BC = [(A’+B+C’) + (A’+C’+D’) + BC’]’
=[( A’ + B + C’ +D’) + BC’ ]’
= A + BC
= (A’ +B+C’+D’)’. (BC’)’
Example 2: AB + AC’ + BC = ( A’’.B’.C’’.D’’). (B’ + C’’)
= AB (C + C’) + AC’ + BC = ( A.B’.C.D).(B’ +C)
= ABC + ABC’ + AC’ + BC = AB’CD + AB’CD
= BC + AC’ = AB’CD

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Example 4: F = AB’ + A’B + A’B’ + AB
= B’ ( A + A’) + B ( A ‘+ A )
= B + B’
= 1 Ans. Example 6: F = ( A + B’ + AB ) ( A + B’ ) ( A’B)
= ( A + B’ ) ( A + B’ ) ( A’B )
= ( A + B’ ) ( A’B)
= A.A’B + A’ B.B’
= 0 Ans.

Example 5: F = ( AB + C ) ( AB + D)
= AB.AB + ABD + ABC + CD
= AB + ABD + ABC + CD
= AB ( 1 + D + C ) + CD
= AB + CD Ans.
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 Simplify the following Boolean
Expression
a) F = (A’ + B) (A + B)
b) F = A’B’C’ +A’B’C +AB’C’ + AB’C
c) F = AC’ + ABC + A(C + AC’)
d) F = 1 + [A’B + (CD)’ + (BC)” ]’
e) F = AC’ + ABC + A(C +AC’)
f) F = ( AB + A + AB )

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 Karnaugh Map (K-Map)
Karnaugh Map
• We have simplified the Boolean function using Boolean
postulates and theorems. It is time consuming process
and we have to re-write the simplified expressions
after each step.
• To overcome this difficulty, Karnaugh introduced a
method for simplification of Boolean functions in an
easy way. This method is known as K-map method,
• It is a graphical method, which consists of 2n cells for
‘n’ variables. The adjacent cells are differed only in
single bit position.

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Simplification of SOP (2- Variables)

Adjacent Cells

For n variables K-map, each cell

is adjacent to the other n cells

Non-adjacent cell
Prepared By: Er. Ganesh Kumal 76
 3- Variables
3 variable K-map =Total 8 cells

Each cell is adjacent to the other 3 cells

Prepared By: Er. Ganesh Kumal 77

4-Variables K-map

Prepared By: Er. Ganesh Kumal 78

 K-Map Simplification Procedure
1. Plotting
 Draw the K-map according to the number of variables.
 We have to plot 1, if the given expression is SOP (0’s elsewhere).
 We have to plot 0, if the given expression is POS (1’s elsewhere).
2. Grouping SOP
 The 1’s in adjacent cells (immediately above, below, left or right) must be
combined in groups of 1, 2, 4, 8, ……and so on.
 Each group of 1’s should be maximized to include the largest no of adjacent
cells as possible.
 Every 1’s on the map must be included in at least one group. They can be
overlapping groups if they include non-common cells.
 The top/bottom and left/right edges of the map are considered to be
continuous as shown in Fig. 3.3, so larger groups can be made by grouping
cells across the top and bottom or left and right edges of the map.
3. Simplification
 Each group within a cell is written in product form.
 The groups outside a cell are written in summation form.

Prepared By: Er. Ganesh Kumal 79

 Octet

Pair

Quad

F = m (0, 1, 2, 3, 6, 7) Cell

Figure 3.3: Typical K-Map Groups

Prepared By: Er. Ganesh Kumal 80
Elimination of Redundant Groups

This group is redundant

and can be ignored
Prepared By: Er. Ganesh Kumal 81
 2-Variables K-Map Simplification

F= x’y’ + xy’

Prepared By: Er. Ganesh Kumal 82

 2-Variables K-Map Simplification

F= x’y’ + xy’

Prepared By: Er. Ganesh Kumal 83

 3-Variables K-map
F (A, B, C)=  m ( 0, 2, 3, 4, 5)

Prepared By: Er. Ganesh Kumal 84

 3- Variables K-Map Simplification

XY’
F = C ‘+ A F = XY’ + X’Z
Prepared By: Er. Ganesh Kumal 85
F (A, B, C) = A’B + BC’ + AC’
Solution:
Expressing the given function as a min-terms ( standard SOP).
F = A’B + BC’ + AC’
= A’B (C + C’) + BC’(A + A’) + AC’ (B + B’)
= A’BC + A’BC’ + ABC’ + A’BC’ +ABC’ + AB’C’
= A’BC + A’BC’ + ABC’ + AB’C’

Prepared By: Er. Ganesh Kumal 86

4-Variables K-Map

Prepared By: Er. Ganesh Kumal 87

Prepared By: Er. Ganesh Kumal 88
Prepared By: Er. Ganesh Kumal 89
 Don’t Care Conditions
• Real circuits don’t always need to have an output
defined for every possible input.
• For example, some calculator displays consist of 7-
segment LEDs. These LEDs can display 2n - 1 patterns,
but only 10 of them are useful.
• If a circuit is designed so that a particular set of inputs
can never happen, we call this set of inputs a don’t care
condition.
• Don’t care condition marked by ‘X’ in the truth table,
indicates the design doesn’t care if the output is ‘0’ or 1.
• Can be treated as ‘0’ if you don’t need to group it.
• Treated as ‘1’ if you make group larger.
Prepared By: Er. Ganesh Kumal 90
W X Y Z F
0 0 0 0 m0 = X
0 0 0 1 m1 = 1
0 0 1 0 m2 = X
0 0 1 1 m3 = 1
0 1 0 0 m4 = 0
0 1 0 1 m5 = X
0 1 1 0 m6 = 0
0 1 1 1 m7 = 1
1 0 0 0 m8 = 0
1 0 0 1 m9 = 0
1 0 1 0 m10 = 0
1 0 1 1 m11 = 1
1 1 0 0 m12 = 0
1 1 0 1 m13 = 0
1 1 1 0 m14 = 0
1 1 1 1 m15 = 1

Prepared By: Er. Ganesh Kumal 91

Prepared By: Er. Ganesh Kumal 92
 Product of Sum (POS) Simplification
• The 1’s placed in the cells of the map represent
the min-terms of the function.
• The min-terms not included in the function
denote the complement of the function.
• From this we see that the complement of a
function is represented in the map by the squares
not marked by 1’s.
• If we mark the empty squares by 0’s and combine
them into valid adjacent squares, we obtain a
simplified expression of the complement of the
function. i.e. of F’.
Prepared By: Er. Ganesh Kumal 93
Simplify the following
boolean function in A B C D F
(a) SOP and (b) POS. 0 0 0 0 1
0 0 0 1 1
F ( A, B, C, D)=  ( 0, 1, 2, 5, 8, 9,
0 0 1 0 1
10)
0 0 1 1 0
F (A, B, C, D)= M ( 3, 4 , 6,7, 11, 0 1 0 0 0
12, 13, 14, 15) 0 1 0 1 1
0 1 1 0 0 SOP
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
F = (A’ + B’) (C’ + D’) (B’ + D) Prepared By: Er. Ganesh Kumal 94
Logic diagram of Simplified Form

Prepared By: Er. Ganesh Kumal 95

Simplify the following Expression using
K-map and draw the simplified circuit.
1. F = m ( 0, 2, 5, 6)
2. F = A’BC’ + ABC’ + ABC
3. F = X’YZ + X’Y’Z + XYZ
4. F = m ( 1, 3, 7, 9, 11, 14, 15)
5. F = m (1, 3, 10) + d (0, 2, 8, 12)
6. F = πM (0, 2, 4, 8, 9, 12)

Prepared By: Er. Ganesh Kumal 96

 Combinational Circuit
• The output of combinational circuit at any instant of time
depends only on the present input terminals.
• It does not use any memory. The previous state of input does
not have any effect on the present state of the circuit.
• A combinational circuit can have ‘n’ number of inputs, logic
gates and ‘m’ number of outputs.
• The logic gates accept signal from input variables and
generate output signals.
Examples:
•Adders/Subtractors
•Encoders/Decoders
•Multiplexer/ Demultiplexer

Figure: Combinational Circuit

Prepared By: Er. Ganesh Kumal 97
 Design Procedure
The design procedure involves the following
steps:
1) The problem is stated.
2) The number of available input variables and required
output variables is determined.
3) The input and output variables are assigned letter
symbols.
4) The truth table that defines the required relationship
between inputs and outputs is derived.
5) The logic diagram is drawn.

Prepared By: Er. Ganesh Kumal 98

 Half-Adder
• A combinational circuit that performs addition of two single bit numbers.
• The circuit has two input variables A and B and two outputs: sum(S) and
carry(C). From truth table,
S = A’B + AB’
C = AB

Figure : Block diagram, truth table and circuit diagram of half adder.
Prepared By: Er. Ganesh Kumal 99
 Full-Adder
• A combinational circuit that performs the addition of three bits (two
significant bits and a previous carry) is called a full adder.
• Two of the inputs, denoted by A and B, represent the two bits to be added
and third input Cin represent the carry from the previous lower significant
position.

Sum(S) = A’B’C + A’BC’ + AB’C’ + ABC

= A’(B’C + BC’) + A(B’C’ + BC)
= A’( B  C) + A( B  C)’
=ABC

Carry Out(Co)= A’BC + AB’C + ABC’ + ABC

= C( A’B + AB’) + AB ( C + C’)
= ( A  B)C + AB

Figure 6.10: (a) Block diagram (b) Truth table

Prepared By: Er. Ganesh Kumal 100
 CONT…
ABC

( A  B)C + AB

Figure: Circuit diagram of full adder

Prepared By: Er. Ganesh Kumal 101

Implementation of Full-adder with Two
Half-adder

Prepared By: Er. Ganesh Kumal 102

 Half-Subtractor
• Combinational circuit that subtracts two bits and produces
their difference.
• It has two outputs; difference and borrow.
Difference (D) = A’B + AB’

Borrow (Bo) = A’B

Prepared By: Er. Ganesh Kumal 103

 Full-Subtractor
• A full subtractor is a combinational circuit that performs a
subtraction between two bits, taking into account that a 1
may have been borrowed by a lower significant stage.
• This circuit has three inputs and two outputs. The three inputs
A, B and Bin denote the minuend, subtrahend and previous
borrow. The two outputs, D and Bo, represent difference and
borrow out.

Prepared By: Er. Ganesh Kumal 104

 CONT…
From truth table, we can
simplify the Difference ( D) and
Borrow out (Bout).

Table: Truth table of full subtractor

Bin = Previous Borrow

D = ( A – B - Bin)
Prepared By: Er. Ganesh Kumal 105
Figure: Circuit diagram of full subtractor

Prepared By: Er. Ganesh Kumal 106

 Multiplexer (Data Selector)
• Many into one and also called data selector.
• A combinational circuit that has maximum of 2n data inputs,
‘n’ selection lines and single output line.
• One of these data inputs will be connected to the output
based on the values of selection lines.
D1
D2 Example
D3 2n : 1 2 to 1 Multiplexer
. Y (Output)
Multiplexer 4 to 1 Multiplexer
.
8 to 1 Multiplexer
.
. 16 to 1 Multiplexer
D2n

Sn-1 S1 S0
Prepared By: Er. Ganesh Kumal 107
 4:1 Multiplexer

Figure: Truth table of 4 : 1 multiplexer

From the truth table, output of 4 to 1 multiplexer is:
Y = D0S1’S0’ + D1 S1’S0 + D2 S1S0’ + D3S1S0
Prepared By: Er. Ganesh Kumal 108
 Y = D0S1’S0’ + D1 S1’S0 + D2 S1S0’ + D3S1S0

(a) (b)

Figure: 4:1 Multiplexer (a) Block diagram (b) Circuit diagram

Prepared By: Er. Ganesh Kumal 109

 8 : 1 Multiplexer
• In 8 to 1 line multiplexer, 8 input lines D0, D1, …….., D6, D7
and single output from OR gate.
• Among the 8 inputs only one input is selected at single time
by selection lines ( A, B, C).
Selection Inputs Output
A B C F
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

Figure: Truth table ofPrepared

8 : 1 By:
multiplexer
Er. Ganesh Kumal 110
 Figure: Circuit diagram of 8 to 1 multiplexer

Similarly you can draw 16 : 1 multiplexer

Prepared By: Er. Ganesh Kumal 111
 De-multiplexer (Data Distributor)
• One into many and also called data distributor.
• A combinational circuit that receives information from a single
line and directs it to one of 2n possible output lines.
• It has ‘n’ selection lines, single input and maximum 2n output
lines.
• The input will be connected one of these outputs based on
the values of selection lines.
Example:
1 : 2n
1 to 2 De-multiplexer D 2n outputs
De-multiplexer
1 to 4 De-multiplexer
1 to 8 De-multiplexer
1 to 16 De-multiplexer

N selection lines
Prepared By: Er. Ganesh Kumal 112
 1 : 4 De-multiplexer
• There are four possible outputs Y0, Y1, Y2, Y3 and a single input D.
• The single data input is sent to one of the four outputs as per the selection
line input.

Data Selection Inputs Outputs

input S1 S0 Y3 Y2 Y1 Y0
D 0 0 0 0 0 D
D 0 1 0 0 D 0
D 1 0 0 D 0 0
D 1 1 D 0 0 0

Table: Truth table of 1 : 4 De-multiplexer

From truth table,

Y0 = DS’1S’0 Y1 = DS’1S0 Y2 = DS1S’0 Y3 = DS1S0

Prepared By: Er. Ganesh Kumal 113

 Y0 = DS’1S’0

Y1 = DS’1S0

Y2 = DS1S’0

Y3 = DS1S0

Figure: 1 : 4 De-multiplexer (a) Block diagram (b) Circuit diagram

Prepared By: Er. Ganesh Kumal 114

 1 : 8 De-multiplexer
• There are eight possible outputs Y0, Y1, ……..,Y7 and a single
input D.
• The single data input is sent to one of the eight outputs as per
the selection line input.

Prepared By: Er. Ganesh Kumal 115

 Figure : 1 to 8 line De-Multiplexer Circuit diagram
Similarly, you can draw 1 to 16 line De-Multiplexer.
Prepared By: Er. Ganesh Kumal 116
 Encoder
Encoder
• It is a combinational circuit that performs the reverse
operation of decoder.
• It has maximum of 2n input lines and ‘n’ output lines.
• It will produce a binary code equivalent to the input,
which is active high.
Example:
• 4 to 2 line encoder
• 8 to 3 line encoder
• 16 to 4 line encoder
• Decimal to BCD encoder (10 to 4 line)
 4 to 2 Line Encoder

Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

(a) (b)

Figure: 4 to 2 encoder (a)Block diagram (b) Truth Table

From the truth table,
A1 = Y2 + Y3 A0 = Y1 + Y3
 4 to 2 Line Encoder Cont…
A1 = Y2 + Y3
•4 to 2 line Encoder has four
inputs Y3, Y2, Y1 & Y0 and two
outputs A1 & A0.
•At any time, only one of these
4 inputs can be ‘1’ in order to A0 = Y 1 + Y 3
get the respective binary code
at the output.

Figure: Circuit diagram of 4 to 2 line encoder

 8 to 3 Line Encoder
Octal to binary Encoder has OUTPUTS INPUTS
eight inputs, D7 to D0 and D7 D6 D5 D4 D3 D2 D1 D0 A B C
three outputs A, B & C.
0 0 0 0 0 0 0 1 0 0 0

At any time, only one of 0 0 0 0 0 0 1 0 0 0 1

these eight inputs can be 0 0 0 0 0 1 0 0 0 1 0

‘1’ in order to get the 0 0 0 0 1 0 0 0 0 1 1

respective binary code.
0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

From the truth table,

A = D4 + D5 + D6 + D7 Table: Truth table of 8 to 3 line encoder
B = D2 + D3 + D6 + D7
C = D1 + D3 + D5 + D7
Figure: 8 to 3 Line Encoder
 Decimal to BCD Encoder
• The decimal to binary encoder usually consists of 10 input lines and 4
output lines.
• Each input line corresponds to the each decimal digit and 4 outputs
correspond to the BCD code.
• This encoder accepts the decoded decimal data as an input and encodes it
to the BCD output which is available on the output lines.
• The figure below shows the logic symbol of decimal to BCD encoder :
 Truth Table for Decimal to BCD Encoder

Logical expression for A3,

A2, A1 and A0:

A3 = Y8 + Y9
A2 = Y4 + Y5 + Y6 + Y7 We made use of the fact that only
A1 = Y2 + Y3 +Y6 + Y7 one input can be ‘ 1’ at one time.
A0 = Y1 + Y3 + Y5 + Y7 + Y9
Circuit diagram for decimal to BCD encoder
 Encoder and Decoder
Decoder
• A combinational circuit that converts binary information from
n input lines to maximum of 2n unique output lines.
• One of these outputs will be selected based on the
combination of input present, when the decoder is enabled.
• If the n-bit coded information has unused combinations, the
decoder may have fewer than 2n outputs.
Example
• 2 to 4 Line Decoder
• 3 to 8 Line (Binary to Octal) Decoder
• 4 to 16 Line Decoder Figure: Block of Decoder
• BCD to Decimal (4 to 10 line) Decoder

Prepared By: Er. Ganesh Kumal 126

 2 to 4 Line Decoder
Enable Inputs Outputs

E A B Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

(a) ( b)

Figure: 2 to 4 line decoder (a) Block Diagram (b) Truth Table

From truth table,

Y0= E.A’.B’ Y1= E.A’.B Y2= E.A.B’ Y3= E.A.B
Prepared By: Er. Ganesh Kumal 127
Circuit Diagram of 2 to 4 Decoder

Figure: 2 to 4 line decoder

Prepared By: Er. Ganesh Kumal 128
 3 to 8 Line Decoder
• In a 3-to-8 decoder, three inputs are decoded into eight outputs. It has
three inputs as A, B, and C and eight output from Y0 through Y7.
• Based on the combinations of the three inputs, only one of the eight
outputs is selected.

(a) ( b) Truth table

Figure: 3 to 8 line decoder (a) Block diagram (b) Truth diagram

Prepared By: Er. Ganesh Kumal 129
Circuit Diagram of 3 to 8 Line Decoder
Y0= A’B’C’
Y1 = A’B’C
Y2 = A’B C’
Y3 = A’BC
Y4 = AB’C’
Y5 = AB’C
Y6 = ABC’
Y7 = ABC

Figure: Circuit diagram of 3 X 8 line decoder

Draw circuit diagram of 4 X 16 decoder

Prepared By: Er. Ganesh Kumal 130
 BCD to Decimal Decoder
• Four input lines (A, B, C, D) for BCD input.
• 10 output lines (Y0, Y1, Y2, ……..,Y9 ).
• 6 invalid conditions ( 1010, 1011, 1100, 1101,
1110 and 1111) for BCD input.
• For 6 invalid conditions all outputs become
low.

Prepared By: Er. Ganesh Kumal 131

 BCD Inputs Decimal Outputs
A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0 0
Design circuit
1 0 0 0 0 0 0 0 0 0 0 0 1 0 diagram yourself
1 0 0 1 0 0 0 0 0 0 0 0 0 1
1 0 1 0
I
N 1 0 1 1
V 1 1 0 0
A 1 1 0 1 All 0’s
L
I 1 1 1 0
D 1 1 1 1 Prepared By: Er. Ganesh Kumal 132
Table: Truth table of BCD to Decimal decoder
 BCD to Seven Segment Decoder

BCD to seven segment

decoder has four input lines
(A, B, C and D) and 7 output
lines (a, b, c, d, e, f and g).

These outputs are given

to seven segment LED
display which displays the
decimal number depending
upon inputs.

Prepared By: Er. Ganesh Kumal 133

Table: Truth table of BCD to Seven Segment Decoder
Prepared By: Er. Ganesh Kumal 134
Prepared By: Er. Ganesh Kumal 135
Prepared By: Er. Ganesh Kumal 136
Circuit diagram of BCD to Seven Segment decoder
Prepared By: Er. Ganesh Kumal 137
 Sequential circuit
• Combinational circuit with feedback element
(memory).
• Outputs depend upon present inputs and
previous outputs (present states).
Memory elements are
devices capable of storing
binary information. The
binary information stored
in the memory elements at
any given time defines the
Figure 6.1: Block diagram of sequential circuit. state of the sequential
circuit.
Prepared By: Er. Ganesh Kumal 138
 Basic Flip-Flop (Latch)
• Single bit storage device (memory unit).
• It latches ‘0’ or ‘1’.
• Basic Flip-flop circuit can be constructed from two
NAND gates or two NOR gates.
• The cross-coupled connection from the output of one
gate to the input of the other gate constitutes a
feedback path.
• Each flip-flop has two outputs ( Q and Q’ ) and two
inputs Set (S) and Reset (R).
• This type of flip-flop is sometimes called a direct-
coupled RS flip-flop, or RS latch.

Prepared By: Er. Ganesh Kumal 139

Basic Flip-Flop with NOR Gates

When,
S=0, R=0 ; No change state
S=0, R=1 ; Reset
S=1, R=0 ; Set
Figure 6.2: NOR Latch S=1, R=1; Invalid

Prepared By: Er. Ganesh Kumal 140

Basic Flip-Flop with NAND Gates

Figure 6.3: NAND latch

Prepared By: Er. Ganesh Kumal 141

 Clock Pulse
• In the latches and flip-flips, we use the additional
signal called clock.
• Digital circuits are invariably controlled by
a clock and events take place at discrete points in
time.
• The clock is a circuit that provides a sequence of
pulses to trigger each internal operation.

Figure 6.11: Perfect idealized clock

Prepared By: Er. Ganesh Kumal 142
 Positive and Negative Edge Triggering
• Depending on which portion of the clock
signal the latch or flip-flop responds to, we
can classify them into two types:
1. Level Triggering
i. Positive level triggering
ii. Negative level triggering
2. Edge triggering
i. Positive (rising) edge triggering
ii. Negative (falling) edge triggering

Prepared By: Er. Ganesh Kumal 143

 CONT…

Edge Triggering

Level Triggering
Prepared By: Er. Ganesh Kumal 144
 Flip-Flop
• Sequential circuit.
• Single bit memory element (storage device).
• Bi-stable device (either ‘1’ or ‘0’).
• Example: S-R flip-flop, D-flip-flop, J-K flip-flop,
T-flip-flop.

Prepared By: Er. Ganesh Kumal 145

 Clocked RS Flip-Flop
Inputs Outputs

CP S R Q Q’
CP
X 0 0 No change

1 0 1 0 1
(a) Block diagram
1 1 0 1 0

1 1 1 Invalid

(c) Truth table

(b) Logic diagram

FigurePrepared
6.4: RS Flip-Flop
By: Er. Ganesh Kumal 146
Operation of S-R flip-flop
S R Q(t) Q (t +1)
•When CP=0, flip-flop 0 0 0 0
remains in previous state 0 0 1 1
•When CP=1 and 0 1 0 0
i. S = 0, R = 0 ; flip-flop 0 1 1 0
holds the data (No 1 0 0 1
change). 1 0 1 1
ii. S = 0, R = 1 ; flip-flop 1 1 0 X (Indeterminate)
reset irrespective of 1 1 1 X (Indeterminate)
Q Figure: Characteristic table
iii. S = 1, R = 0; flip-flop
set irrespective of
Q.
iv. S =1, R =1; flip-flop is
invalid state
Characteristic equation
Prepared By: Er. Ganesh Kumal 147
Clocked RS Flip-Flop

Indeterminate

Indeterminate

Figure 6.5: RS flip-flop by NOR latch

Prepared By: Er. Ganesh Kumal 148
 Timing diagram of S-R F/F

Figure: Level Triggering

Figure: Edge Triggering

Prepared By: Er. Ganesh Kumal 149
 D Flip-Flop
• One way to eliminate the undesired condition of
the indeterminate state in the RS flip-flop is to
ensure that input S and R are never equal to 1 at
the same time.
• This is done in the D flip-flop as shown in figure
6.6.
• S input is inverted and given to R input to make D
flip-flop from S-R flip-flop.
• Used in registers, shift registers and some of the
counters.
Prepared By: Er. Ganesh Kumal 150
 D Flip-Flop
S Operation:
As long as CP=0, the output
of gate 3 and 4 are high and
the circuit cannot change the
R state regardless of the value
of D.
When CP=1, next state of D
flip-flop is always equal to
data input, D.
Invalid state is removed in D
flip-flop.
Figure 6.6: D Flip-Flop Advantage: Invalid state is
never happened.
Prepared By: Er. Ganesh Kumal 151
Figure: Timing diagram of D flip-flop (positive edge triggering)

Prepared By: Er. Ganesh Kumal 152

 Clocked J-K Flip-Flop
•J-K flip-flop is a refinement of the R-S flip-flop.
•The indeterminate state of the R-S flip-flop is defined in the J-K
flip-flop (when S=1 and R= 1).
•We consider the inputs of S-R flip-flop as S = JQ’ and R = KQ.
Inputs Outputs

CP J K Q Q’

X 0 0 No change
CP 1 0 1 0 1

1 1 0 1 0

1 1 1 Toggle
(a) Logic diagram (b) Truth table
Figure 6.7: J- K Flip - Flop
Prepared By: Er. Ganesh Kumal 153
 J-K Flip-Flop

Figure 6.8: J-K Flip-Flop

Prepared By: Er. Ganesh Kumal 154
 Race around condition

How to avoid race around condition??

i. Using Master-Slave J-K flip-flop.
ii. Using the Edge triggering flip-
flop
iii. T/2 < propagation delay for
level triggering Prepared By: Er. Ganesh Kumal 155
Figure: Time diagram of Edge triggered J-K flip-flop

Prepared By: Er. Ganesh Kumal 156

 J-K Master Slave F/F
• Master-Slave J-K flip-flop is constructed from two
separate flip-flops. One circuit serves as a master
and the other as a slave and the overall circuit is
referred to as a master slave flip-flop.
• The master section is basically a gated latch and
slave is also the same except that it is clocked an
inverted clock pulse and is controlled by outputs
of master section rather than by external J-K
inputs.
• Characteristic table is same as J-K Flip-flop.
Prepared By: Er. Ganesh Kumal 157
 (a) Block diagram

(b) Logic diagram

Figure 6.9: Master Slave J-K flip-flop.

Prepared By: Er. Ganesh Kumal 158
 T Flip-Flop
• It is obtained by connecting J and K inputs
together; so only one input denoted by ‘T’.
•There is only two input conditions
J=K=1
J=K=0
• T flip-flop is used for counter.
Q(t) T Q(t + 1)
0 0 0 (a) Block diagram
0 1 1 K
1 0 1
1 1 0
(C) Characteristic table

(b) Logic diagram

Figure 6.10: T Flip-Flop
Prepared By: Er. Ganesh Kumal 159
 Asynchronous and Synchronous
Counter
Counter
• Number of flip-flops can be connected together to perform counting
operation: such a group of flip-flops is a counter.
• Counters are classified into two broad categories according to the way
they are clocked:
i. Asynchronous (ripple) counter
ii. Synchronous counter
Asynchronous Counter
In asynchronous counters, commonly called ripple counters, the first flip-
flop is clocked by the external clock pulse and then each successive flip-
flop is clocked by the output of the preceding flip-flop hence the state of
all flip-flops do not change simultaneously.
Synchronous Counter
In a synchronous counter, the clock input is connected to all of the flip-
flops. So they are clocked simultaneously and state changes by flip-flops
occur at the same time.

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 Binary (Ripple) Counter
Binary (ripple) counter
• An asynchronous counter is one in which the flip-flop
within the counter do not change states at exactly
the same time because they do not have a common
clock pulse.
• Ripple counter consists of series of flip-flops (T or J-K
type), with the output of each flip-flop connected to the
CP input of the next higher-order flip-flop.
– 2 Bit asynchronous binary counter
– 3 Bit asynchronous binary counter
– 4 Bit asynchronous binary counter

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 2-Bit Ripple Counter
Q0 (LSB) 00

01 11
Q1(MSB)

10

(b) Circuit diagram (a) State diagram

CLK Q1 Q0
Initially 0 0 CLR=0
 0 1 CLR=1
 1 0 CLR=1
 1 1 CLR=1

(d) waveform (c) Truth table

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Figure: 2-Bit ripple counter
 2-Bit Ripple Counter
• There are 2 flip-flops (T or J-K) connected in series.
• All the flip-flops inputs are connected to logic high
input.
• External clock input (CP) is connected to first flip-flop
and Q output of first flip-flop is connected to next flip-
flop.
Operation:
• Initial state of each flip-flop in the absence of clock signal
is Q1Q0 = 00; by inserting CLR=0. This is incremented by 1
at every clock pulse and reached to maximum, Q1Q0=11,
and repeats when further clock pulse is applied.
• Q0 toggle at every negative edge of clock pulse.
• Q1 toggle for every Q0 that goes from 1 to 0.

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 3-Bit Ripple Counter
• There are three flip-flops (T or J-K at toggle
mode) connected in series.
• All the flip-flops inputs are connected to logic
high.
• External clock input (CLK) is connected to first
flip-flop and Q output of first flip-flop is
connected to next flip-flop and so on (Positive
Edge Triggering) and Q output is connected to
next flip-flop and so on (Negative Edge Triggering)
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3-Bit Ripple Up Counter(Positive Edge Triggering)

Operation:
1. The initial state of each flip-flop in the
absence of clock signal is Q2Q1Q0=000.
2. This is incremented by 1 at every clock
pulse and reached to maximum(111) at
7th clock pulse and repeats when further
clock pulse is applied.
3. Q0 toggle every positive edge of clock
pulse.
4. Q1 toggle for every Q0 that goes from 1
to 0.
5. Q2 toggle when Q0 and Q1 (both) goes
from 1 to 0.

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 3-Bit Down Counter
For up counter: For down counter
+ve edge ( Q0 given to CP input of next flip-flop) +edge ( Q0 given to CP input of next flip-flop)
-ve edge ( Q0 given to CP input of next flip-flop) -edge (Q0 given to CP input of next flip-flop)

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3-Bit Up/Down Counter

Figure:

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Truth table of 3-bit up/down counter

(M=0) (M=1)

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 4-Bit Ripple Up Counter
• It works exactly the same way as a 2-bit or 3 bit asynchronous
binary counter mentioned above, except it has 16 states due to the
fourth flip-flop
• J-K inputs of all flip-flops are connected together and given to high
input
• For negative edge triggering up counter, Q output is given to CLK
input of next flip-flop.
• Initially all flip-flops are reset condition.
• When first clock pulse is given, FF0 is set and other flip-flops remain
previous state(count 0001)
• When second clk pulse is given, FF1 is set and FF0 is reset by
toggling. (count 2)
• Similarly, at each clock pulse counting is increased by 1(binary) and
at 15th clock pulse all flip-flops are in set condition ( i.e. 1111=15).
• At 16th clock pulse all flip-flops are reset and recycles.

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4-Bit Counter (Negative Edge Triggering)

Figure: Circuit diagram and timing waveform

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 Asynchronous BCD (Decade) Counter
• The binary counters previously introduced have 2n states. But counters
with states less than this number are also possible. They are designed to
have the number of states in their sequences, which are called truncated
sequences. These sequences are achieved by forcing the counter to
recycle before going through all of its normal states.
• A counter with ten states in its sequence is called a decade(Modulus 10)
counter.
• Once the counter counts to ten (1010), all the flip-flops are being cleared.
Notice that only Q1 and Q3 are used to decode the count of ten. This is
called partial decoding, as none of the other states (zero to nine) have
both Q1 and Q3 HIGH at the same time.
• Such a counter must have at least four flip-flops to represent each binary
bit.

Figure: State diagram

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 Asynchronous BCD(Decade) Counter
State Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1 (a) Circuit diagram
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10(RESET) 1 0 1 0
(b) Timing diagram
(c) Truth Table
Figure: Decade Counter
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 Synchronous Counter
Design Procedure of sequential
counter:
1. Determine number of flip-
flops & decide type of flip-
flop.
2. Draw the excitation table of
FF.
3. Make the state diagram and (a) Circuit diagram
circuit excitation table.
4. Derive simplified equation
using k-map.
5. Draw the logic diagram.

(b) waveform

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 3-Bit Synchronous Counter
P.S N.S J-K Flip-flop Inputs
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1

From the above excitation table, we can derive the equation of each
FFs input using K-map.
After Simplification we get:
J0 = K0= 1 J1 = K1= Q0 J2=K2= Q0.Q1
From these equations we have to draw circuit diagram.
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4-Bit Synchronous Counter

Note: You have to write excitation

table and find out J and K input of
each flip-flop by mapping.
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 Register
• Flip-flop can be used to store single bit binary
data. To increase the storage capacity in terms
of bits, we have to use a group of flip-flop.
Such a group of flip-flop is known as a register.
• The n-bit register will consists of a n number
of flip-flops and capable of storing an n-bit
word.

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 Shift Register
• The binary data can be moved within the register
from one flip-flop to another.
• The registers that allow such data transfers(either
left or right) are called as shift registers.
Types:
Shift registers are basically of 4 types. These are:
1. Serial In Serial Out (SISO)
2. Serial In Parallel Out (SIPO)
3. Parallel In Serial Out (PISO)
4. Parallel In Parallel Out (PIPO)

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 Types
• Serial In Parallel-out (SIPO) - the register is loaded with serial data, one bit at
a time, with the stored data being available in parallel form.
• Serial In Serial-out (SISO) - the data is shifted serially "IN" and "OUT" of the
register, one bit at a time in either a left or right direction under clock control.
• Parallel In Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time
under clock control.
• Parallel In parallel-out (PIPO) - the parallel data is loaded simultaneously into
the register, and transferred together to their respective outputs by the same
clock pulse.

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 Serial In Parallel Out

Figure: 4-bit Serial In Parallel Out

• In Serial-in Parallel-out shift register, data is entered serially and

taken out in parallel fashion.
• 4 clock cycles are required to load 4-bit data serially.
• At 4th clock pulse, all data bits are out.

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Figure: Truth table and Waveforms of 4-bit SIPO shift register

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 Serial In Serial Out
0101

FF3 FF2 FF1 FF0

• The circuit consists of 4 D flip-flops which are connected in a serial manner.

• All flip-flops are synchronous with each other since the same clock signal is applied
to each flip-flop.
• If the number 0101 is going to enter, LSB should be applied first at FF3.
• So 4 clock pulses is required to enter the 4-bit data (0101) and LSB is out at the same
time 4th clock pulse. So other 3 clock pulses are required to out the other bits serially.

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Truth table of 4-bit serial in serial out shift register

CLK Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 1 0 0 0
Serial In Complete
2 0 1 0 0
3 1 0 1 0
4 0 1 0 1
5 0 0 1 0
Serial out Complete
6 0 0 0 1
7 0 0 0 0

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 4-Bit Parallel In Parallel Out
This type of register also acts as a temporary storage device or as a time delay
device similar to the SISO configuration above. The data is presented in a
parallel format to the parallel input pins PA to PD and then transferred
together directly to their respective output pins QA to QD by the same clock
pulse.

Figure: 4-bit parallel in serial out shift register

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 4-Bit Parallel In Serial Out

Figure: 4-bit parallel in serial out shift register

LOAD Mode:
When the SHIFT/ LOAD =0; the AND gate 1, 2, 3 and 4 become active.
They will pass data D0, D1, D2 and D3 bits to the corresponding flip-
flops.
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• When SHIFT/ LOAD =1; Gate 1, 2, 3 and 4 are inactive. Hence the parallel
loading of the data become impossible.
• But the Gate 5, 6 and 7 are active. Therefore shifting of data from left to
right is possible by application of clock.
• First clock pulse is used for loading parallel data and remaining 3 clock
pulses are required for shifting out the data serially from Q3.

CLK Q0 Q1 Q2 Q3 Out from Q3

Initially 0 0 0 0
1 1 0 1 0 0 (Parallel in complete)
2 0 1 0 1 1
3 0 0 1 0 0
4 0 0 0 1 1 (serial-out complete)

Figure: Truth table of 4-bit parallel in serial out shift register

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Unit 6 End !!

Thank You!!

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