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DDCA Set-1 Insem-1 Key

The document contains questions and answers related to digital logic design. It covers topics such as Boolean algebra, logic gates, flip-flops, registers, multiplexers, decoders, and PROM design. Detailed explanations and circuit diagrams are provided for concepts like full adders, shift registers, and JK flip-flops.

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t.harshiharshitha
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19 views5 pages

DDCA Set-1 Insem-1 Key

The document contains questions and answers related to digital logic design. It covers topics such as Boolean algebra, logic gates, flip-flops, registers, multiplexers, decoders, and PROM design. Detailed explanations and circuit diagrams are provided for concepts like full adders, shift registers, and JK flip-flops.

Uploaded by

t.harshiharshitha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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In Sem -1, Questions & Answers

Q. NO Questions & Answers Marks


SECTION-A
1, A Apply De Morgan's theorems to simplify the expression: F = [(A+B)(C+D)]' 2M
F = [(A+B)(C+D)]'
= (A+B)’ + (C+D)’
= A’.B’ + C’.D’
1, B Develop a truth table that represents the Boolean equation. F = A’B’C + AB’C’ + ABC’ 2M
+ ABC = ∑ m (1,4,6,7).
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
1, C Sketch a basic block diagram for a Programmable Array Logic (PAL) device. 2M

1, D Compare and contrast a Latch and Flipflop in controlling the logic of the system. 2M
Latches Flip-flops
Continuously checks its inputs and
Continuously checks its inputs and
changes output at times determined by
changes output accordingly.
the clock signal.
Level Triggered Edge Triggered
Requires Enable signal to function Requires clock to function
Made up of Logic gate blocks Made up of Latches and Logic gates
1, E Illustrate the modelling diagram of a register using flip-flops. 2M
1, F List the different types of shift registers. 2M
1. Serial In Serial Out (SISO)
2. Serial In Parallel Out (SIPO)
3. Parallel In Serial Out (PISO)
4. Parallel In Parallel Out (PIPO)
SECTION-B
2, A Describe the full adder using a block diagram, list its truth table and output equations. 4M
Block Diagram: Truth Table:

Output Expressions:
SUM = ∑m(1,2,4,7) = A’.B’.C+A’.B.C’+A.B’.C’+A.B.C
CARRY= ∑m(3,5,6,7) = A’.B.C+A.B’.C+A.B.C’+A.B.C
Circuit Diagram:

2, B Design a circuit diagram for a 3-to-8 line decoder. Include input and output labels in your 4M
diagram.
2, C Identify and categorize the various types of triggering mechanisms utilized in digital 4M
circuits.

2, D Compare and contrast the design considerations for synchronous and asynchronous 4M
sequential circuits.

SECTION-B
3, A Optimize the four variable function F ⟮A,B,C,D⟯ = ∑m ⟮0,1,4,5,6,10,13⟯ + d ⟮2,3⟯ using 5M
K-Maps.

F = A’C’ + A’D’ + BC’D + B’CD’


3, B Design the function F(A,B,C) = ∑ m (1,4,5,7) using 4X1 MUX considering A as Input 6M
line and B, C as selection lines.

4, A Design the following Boolean functions using PROM. 5M


i) A (X,Y,Z) = ∑m (5,6,7) ii) B (X,Y,Z) = ∑m (3,5,6,7)

4, B Design a Configurable Logic Block (CLB) for the given Boolean function Y(A,B)= ∑m 6M
(0,1,2).

5, A Describe the working principle of an JK Flip-Flop using a truth table and logic diagram. 5M
5, B A 4-bit register is initially filled with the data "1101". The register is shifted six times to 6M
the right with the serial input being 101101. What is the content of the register after each
shift?

6, A Develop the SR flip-flop characteristics table and excitation table. 5M

6, B Construct a 4-bit shift register configuration that outputs the binary data pattern "1011" 6M
in parallel format after receiving it serially.

**** THE END ***

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