www.ambarella.com VERSION 1.

1 | April 27, 2020

CV2S66 Datasheet - Preliminary

SUMMARY DESCRIPTION CONTENTS

The Ambarella CV2S66 4K Ultra-HD SoC with 1. Overview.................................................................. 1

CVflow® computer vision architecture combines
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image processing, stereo processing, 4K video 2. Interfaces................................................................. 8

encoding, and CVflow computer vision process-
ing technologies to deliver object classification,
and powerful analytic capabilities to profes-
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3. Pins........................................................................ 16
sional IP cameras and consumer cameras with
4Kp30 HEVC + 1080p30 HEVC + 4Kp4 MJPEG
4. Electrical Characteristics..................................... 55
video performance.
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Combining cutting-edge CVflow processing tech- 5. Package................................................................. 80

niques, stereo functionality, and an industry-leading
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ISP, the CV2S66 chip enables customers to develop

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Deep Learning functions such as person detection, 6. Contact and Order Information............................ 83
face detection and recognition, tracking, and object
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classification. 7. Errata..................................................................... 84
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KEY FEATURES 8. Important Notice................................................... 85

• An embedded quad-core Arm® Cortex®-A53

9. Revision History................................................... 86
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1 GHz CPU with 1MB L2 cache

• Multi-channel ISP with up to 720 MPixel/s input
pixel rate
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• Advanced dynamic range (WDR and HDR) ISP

• 3D motion-compensated temporal filtering
(MCTF)
• CVflow processor with convolutional neural
network (CNN) / deep learning support
• Object detection and stereo processing capa-
bilities
• Customers’ existing CNN models can be trans-
lated to the CV2S66 platform
• 716-pin, 0.65-mm pitch HS-BGA package
(19 mm x 19 mm)
• 10-nm CMOS low power (LP) technology
• Operating temperature: -25 C to +85 C

The material in this document is for information only. Ambarella assumes no responsibility for errors or omissions and reserves the right to
change, without notice, product specifications, operating characteristics, packaging, ordering, etc. Ambarella assumes no liability for damage
resulting from the use of information contained in this document. All brands, product names and company names are trademarks of their respec-
tive owners. Further information, including additional disclaimers, appears in the Important Notice at the end of this document.

Proprietary and Confidential Copyright © 2020, Ambarella Inc.

CV2S66 Datasheet - Preliminary

1. OVERVIEW

This preliminary datasheet for the CV2S66 vision processor from Ambarella begins with a brief introduction to the
chip (Section 1.1) and a feature list (Section 1.2). Chapter 2 describes the CV2S66 peripheral interfaces. For pin
details and electrical characteristics refer to Chapter 3 and Chapter 4, respectively. See Chapter 5 for package
information and Chapter 6 for Ambarella contact and ordering details.

Please note that the chip features described in this datasheet are subject to change. Details that have not been
entirely finalized (e.g., encoding specifics) are provided using conservative estimates (i.e., final encoding perfor-
mance is expected to meet or exceed the estimate provided). Please contact an Ambarella representative for
additional information.
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1.1 Introduction
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The Ambarella CV2S66 4K ultra-HD SoC includes an advanced CVflow computer vision processing engine, a
1 GHz quad-core Arm Cortex-A53 CPUs, a 4K ultra HD H.264 / H.265 encoder, and a high-performance digital
signal processor (DSP) subsystem with an Ambarella image sensor processor (ISP). ISP functions such as 3A,
high dynamic range (HDR), dewarping, and 3D noise reduction are provided. The flexible high-definition CV2S66
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H.264/H.265 codec delivers recording up to 4Kp30 HEVC + 1080p30 HEVC + 4Kp4 MJPEG resolution, including
a high-quality, low-latency secondary stream. CV2S66 supports multiple sensor interfaces, enabling a wide range
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of popular CMOS sensors up to 32-MPixel resolution and up to 720 Mpixels/s input rate.
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The Ambarella CV2S66 4K ultra-HD SoC uses a collection of highly developed computer vision technologies to
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deliver stereo processing, and vector-based analytics capabilities to a variety of applications, including IP cam-
eras. Combining cutting-edge vector processing techniques, stereo processing, and an industry-leading ISP, the
CV2S66 chip enables customers to develop deep learning functions such as object classification, target tracking,
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facial recognition, and more.

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CV2S66 Datasheet - Preliminary

CPU CORE COMPUTER VISION IMAGE SIGNAL VIDEO CODEC

PROCESSOR PROCESSOR

Auto Exposure
QUAD-CORE
ARM Gain Control
PROCESSOR AVC / HEVC /
CORTEX-A53 Auto White Balance MJPEG Codec
STEREO Image Stabilization
NEON DSP Extensions
PROCESSOR Dewarp
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32/32 KB L1 Cache HDR Multi-Channel Encode

VMEM
1-MB L2 Cache 3D MCTF VBR Rate Control
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LPDDR4x / LPDDR4 Ambarella Proprietary Memory System

64-bit data bus width
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VIDEO INTERFACES CONNECTIVITY SYSTEM PERIPHERALS

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INP U T UAR T JTA G

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US B 2.0 HOS T/DEV ICE

SLVS / M I PI C SI- 2 / SSI / SPI TIMER S
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LVC M OS
ETHE RNET AVB I2C RTC
RG M I I / RMII
OUTPUT
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I2S PWM
MIPI DSI / M I PI C SI- 2 /
S D / S DIO
PARAL L EL / H D M I ADC GP IO
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SECURITY FEATURES
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OTP, TrustZone, I/O Virtualization

Figure 1-1. CV2S66 Overview: Functional Block Diagram of the CV2S66 Vision Processor.

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Leveraging Ambarella’s proven low-power multi-core architecture, CV2S66 enables customers to develop ad-
vanced computer vision (CV) functionality, including:
• IP Camera CV functions

◦ Object detection / classification (CNN-based)

◦ Stereo depth
◦ Virtual fence
◦ Face detection and recognition
◦ License plate recognition
◦ Behavioral analysis for retail use
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The CV2S66 vision processor includes a 1 GHz quad-core Arm Cortex-A53 CPU and a high-performance
digital signal processing (DSP) subsystem with an Ambarella image sensor pipeline (ISP). ISP functions such
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as 3A, high dynamic range (HDR), dewarping, and 3D noise reduction are provided. CV2S66 supports multiple
sensor interfaces, enabling a wide range of popular CMOS sensors up to 32-MPixel resolution and up to 720
Mpixels/s input rate, as well as 4K stereo pairs, quad 2K stereo pairs, and depth sensor fusion.
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The CV2 chip is fabricated using low-power 10-nm LP silicon technology, minimizing system power requirements.
Total system power consumption is further reduced by a DSP subsystem with on-chip memory, which
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also decreases external memory bandwidth requirements.

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The CV2S66 software development kit (SDK) is designed to facilitate camera, video applications, and DNN al-
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gorithms development for IP security camera products, allowing customers to develop application code and port
their neural networks to utilize the acceleration and computation capability of the CVflow vector processor.
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1.2 Feature List

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Features of the CV2S66 chip include:

• Embedded quad-core Arm Cortex-A53 CPU

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◦ Clock frequency up to 1 GHz

◦ 32 KB data / 32 KB instruction cache
◦ 1 MB L2 cache
◦ NEON SIMD acceleration
◦ Vector floating point (VFP) with hardware floating-point processing

• LPDDR4x / LPDDR4 controller

◦ Up to 1.296 GHz clock rate

◦ 64-bit wide data bus
◦ Up to 4 GB capacity

• Sensor / Video Input (VIN) interfaces

◦ Support for popular CMOS sensors: Sony, ON Semiconductor (Aptina), Panasonic, OmniVision
◦ Six VIN instances: all support serial sensors and two support parallel sensors.

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- Lanes are shared between serial sensor interfaces

- Independent operations when lanes are not shared
◦ CCIR.601 video input with external sync signals
◦ BT.1120/CCIR.656-style video input with embedded sync codes

• Video output (VOUT) interfaces

◦ CV2S66 can drive 2 video output data types in parallel:

- Channel one outputs digital / MIPI DSI / FPD
- Channel two outputs analog / MIPI CSI-2 / HDMI® / SLVS
◦ YUV output with external sync signals (16-bit)
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◦ 4-lane MIPI DSI / CSI-2 output

◦ HDMI v1.4 output including PHY with CEC support
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◦ Flexible OSD with 8- , 16- and 32-bit options

◦ CV2S66 provides flexible graphics and OSD capability, controlled by Arm software. Graphical
overlays can be implemented on recorded video streams, video output to display, or both.
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• Image / video processing

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◦ RGGB / RCCC / RCCB / RGB-IR(4x4) / monochrome sensor

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◦ High dynamic range (HDR) processing

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◦ HDR sensor companding mode support (up to 16 bits)

◦ Motion-compensated temporal filtering (3D noise reduction) for excellent low-light performance
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◦ 360o fisheye lens dewarp and lens optical / geometric distortion correction
◦ ISP virtual channel (virtual multi-channel ISP on single video input)
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◦ 3D LUT color correction and global tone mapping

◦ Adjustable 3A; exposure, white balance and focus control (AE/AWB/AF)
◦ RGB and YUV statistics, histogram, and AF focus value generation
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◦ Luma sharpen and chroma noise filter

◦ Day / night and DC/P Iris control
◦ Four resizers (up to 1/8X ~ 16X scaling) with digital pan, tilt and zoom (PTZ)
◦ Crop, mirror, flip, 90/270 degree rotation
◦ Alpha-blending OSD up to full-frame stream overlay for text, image and privacy mask
◦ 3-axis electronic image stabilization (EIS) with rolling shutter correction support
◦ Flexible APIs and Image-tuning tools
◦ Black level correction
◦ Static and dynamic bad pixel correction
◦ Vignetting compensation
◦ Chromatic aberration correction

• Video encoding engine

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◦ H.265 / HEVC main profile 5.1 encoding

◦ H.264 main profile / high profile Level 5.1 encoding
◦ Encoding performance up to 4Kp30 HEVC + 1080p30 HEVC + 4Kp4 MJPEG
◦ Fisheye encoding performance up to 9MP uncorrected (fisheye) input, 9MP30 + 720p30 encode.
Note that the corrected resolution may be higher than the original uncorrected view.
◦ Flexible encode resolution control including aspect ratio, scan type, and frame rate
◦ JPEG encoding
◦ Advanced compression tools
- I, IP and IBP modes
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- 2 Forward Ref P
- SVCT scalable video coding
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- Advanced GOP structures with fast seek and bi-directional predictions (B-frames)
◦ Dynamic GOP, length up to 65535
◦ Flexible rate control
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- CBR, VBR, and constant QP with max bitrate control

- Macroblock-level adaptive quantization
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◦ Dynamic ROI encoding per frame with up to 32 free-form areas at macroblock boundary
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◦ Smart video compression optimized for surveillance scenes, 4Kp30 as low as 512 Kbits/s
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◦ Encoding frame rate ranging from 1 to 120 frames per second

• Stereo Disparity Engine

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◦ Implements semi-global matching to find disparity between two images

◦ Supports a single 1080p30 4K stereo pair or multiple lower resolution (1080p, 720p) stereo pairs
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◦ Supports multi-scale disparity map and fusion of multi-scale disparity maps

◦ Supports hardware accelerated feature extraction engine
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• AHB bus DMA controller

◦ Memory-to-memory transfers including support for transfers between memory and peripherals
◦ Programmable transfer count up to 4 MB
◦ DMA scatter / gather via chained descriptor list in memory with DMA control information source

• Dedicated DMA coprocessor for graphics and image operations

◦ Linear copy, 2D copy, composite, and alpha-blend image operations

◦ 4- to 32-bit pixel formats

• Two I2S digital audio interface (stereo)

◦ One supports four channel audio and other supports two channel audio.
◦ Audio record / playback

• Ethernet MAC controller

◦ IEEE 802.3 compliant with full- and half-duplex (IEEE 802.3x flow-control) and jumbo frames

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◦ IEEE 802.1Q VLAN tag detection

◦ Checksum off-load for received IP and TCP / UDP packets
◦ Dedicated pins for RGMII and RMII interface
◦ FIFO (4 KB / 4 KB) and DMA support

• USB 2.0 interface

◦ One port configurable as host or device, with built-in PHY

• Flexible storage media input / output (SMIO) interface

◦ NAND flash controller

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- Up to 128 Gb device, 2 KB and 4 KB page sizes

- 8-bit flash chip data bus
- 4-bit and 8-bit SLC with ECC hardware and read-confirm support
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- BCH error correction and increased spare area available

◦ Two SD controllers (SD0, SD1)
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- SD0:
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• SDIO v3.0, SD, SDHC, SDXC, MMC and eMMC operation with boot support and UHS-I speed
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• 1-bit, 4-bit, and 8-bit SD mode

- SD1:
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• SDIO v3.0, SD, SDHC, SDXC, MMC and eMMC operation with UHS-I speed
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• 1-bit, 4-bit, and 8-bit SD mode

- 32 GB maximum capacity for SDHC SD card
- 2 TB maximum capacity for SDXC SD card
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- CRC7 for command and CRC16 for data integrity

• Advanced security features
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◦ Secure boot
◦ One-time-programmable (OTP) memory for authentication keys
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◦ On-chip random number generator

◦ DRAM scrambling
◦ Arm TrustZone®
◦ IO virtualization
◦ eFuse disable for JTAG

• Multiple boot options

◦ SPI NAND, SPI NOR, NAND Flash, USB, and eMMC

◦ Single- / dual- / quad-SPI NOR and SPI NAND supported

• Generic interrupt controller including GIC CPU-offload functionality

• SSI / SPI controller interfaces

◦ Four SSI / SPI masters

- DMA support for up to 11 devices
◦ One dedicated SSI / SPI slave port to connect to an external system master

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• Two-wire serial inter-integrated circuit (I2C / IDC) master interfaces (x4)

◦ Configurable IDC buses

• UART interfaces (x5)

◦ 4 AHB-bus UART interfaces, 1 APB-bus UART interface

- DMA support included in the 4 AHB interfaces with flow control
• Up to 166 general purpose input / output (GPIO) pins with individual pull-up/down control

• ADC (two channels) with high / low threshold interrupt generation and 12-bit resolution

• Built-in power controller for power-up / down sequencing

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• Real time clock (RTC)

• Two timer instances of the chip with each instance supporting 10 counters. The first three counters
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of the first instance could be triggered by an external clock. External clock frequency should be less
than one quarter of the APB clock.

• Watchdog timer
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• Stepper motor interface (three channels)

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• Pulse width modulators (PWM) (x12)

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◦ Three sets of PWM controllers and each controller supports up to 4 PWMs

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• JTAG in-circuit emulator (ICE) interface for debugging

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• 716-pin, 0.65-mm pitch HS-BGA package (19 mm x 19 mm)

• 10 nm CMOS low power technology

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• Operating temperature from -25 C to +85 C

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CV2S66 Datasheet - Preliminary

2. INTERFACES

2.1 Interfaces: Overview

This chapter summarizes the features of the interfaces for the CV2S66 chip and includes the following sections:

• (Section 2.2) Interfaces: SDRAM

• (Section 2.3) Interfaces: Video Input
• (Section 2.4) Interfaces: Video Output
• (Section 2.5) Interfaces: Audio Input and Output
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• (Section 2.6) Interfaces: Gigabit Ethernet

• (Section 2.7) Interfaces: USB
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• (Section 2.8) Interfaces: Smart Media Input / Output (SMIO)

• (Section 2.9) Interfaces: SSI / SPI
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• (Section 2.10) Interfaces: I2C / IDC

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• (Section 2.11) Interfaces: UART

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• (Section 2.12) Interfaces: General Purpose Input / Output (GPIO)

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• (Section 2.13) Interfaces: Analog-to-Digital Converter (ADC)

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• (Section 2.14) Interfaces: Power Control (PWC) and Real Time Clock (RTC)
• (Section 2.15) Interfaces: Stepper and Pulse Width Modulator (PWM)
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• (Section 2.16) Interfaces: JTAG

2.2 Interfaces: SDRAM

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• LPDDR4x / LPDDR4 SDRAM interfaces with a maximum clock frequency of 1.296 GHz
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• Programmable IO strength

• 64-bit data bus width

Contact an Ambarella representative for programming and calibration.

2.3 Interfaces: Video Input

• Six VIN instances: one VIN (Main), five PIPs / VINs (Secondary)

◦ Lanes are shared between VIN, PIP2 / VIN2, and PIP3 / VIN3; and PIP / VIN1, PIP4 / VIN4 and
PIP5 / VIN5
◦ If SLVS and MIPI interfaces are being used in configurations more than 4 lanes certain VINs
might be unavailable
◦ Independent operations when lanes are not shared

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CV2S66 Datasheet - Preliminary

• Operating Modes:

◦ VIN / PIP:
- SLVS
- 2 x SLVS (1-12 lane)
- 6 x SLVS (1-4 lane)
- MIPI
- 2 x MIPI (1-4, 8 lane)
- 6 x MIPI (1-4 lane)
- Parallel LVCMOS
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- 16-bit parallel LVCMOS

- Parallel LVDS
- up to 12-bit parallel LVDS
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Note:

• VIN and PIP are used synonymously

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• The SLVS / MIPI interface can be clocked up to 2.5 Gbps/s

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• The parallel LVCMOS can be clocked up to 150 MHz

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2.4 Interfaces: Video Output

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• Two independent video output channels (as shown in Figure 2-1)

◦ One channel drives the digital parallel interface (LVCMOS), MIPI DSI, or FPD-Link output
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◦ The other channel drives the analog, MIPI CSI-2, HDMI, or SLVS output
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Note:
MIPI DSI and MIPI CSI-2 cannot function simultaneously as they share the same MIPI hardware.

CHANNEL 1 DIGITAL PARALLEL INTERFACE /

MIPI DSI / FPD-Link

CV2
CHANNEL 2
ANALOG / MIPI CSI-2 / HDMI / SLVS

Figure 2-1. CV2S66 Video Output Channels and Ports.

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2.4.1 Analog Output

The CV2S66 video digital-to-analog converter (DAC) can drive standard-definition composite video outputs.

2.4.2 Digital Parallel Interface

The CV2S66 chip supports various digital video output modes including 16-bit {CbY, CrY}, CCIR.601 and CCIR.656
as described in the following tables. Output format 4:2:2 is supported.

Bits Mapped To Signal Notes

VD0_OUT[15:8] Unused
VD0_OUT[7:0] Interleaved R,G,B VD0_OUT[7] is MSB
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Table 2-1. Digital RGB Mode (Video Output Modes 0/1/2 for 3-bit Output to the LCD).
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Bits Mapped To Signal Notes

VD0_OUT[15:11] Upper 5 bits of the Red channel VD0_OUT[15] is the MSB
VD0_OUT[10:5] Upper 6 bits of the Green channel VD0_OUT[10] is the MSB
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VD0_OUT[4:0] Upper 5 bits of the Blue channel VD0_OUT[4] is the MSB

Table 2-2. 5:6:5 RGB Mode (Video Output Mode 3 for 16-bit RGB Output to the LCD).
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Bits Mapped To Signal Notes

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VD0_OUT[15:8] Unused
VD0_OUT[7:0] Interleaved Cb,Y,Cr,Y . . .
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Table 2-3. 8-bit YCbCr Mode (Video Output Mode 7).

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Bits Mapped To Signal Notes

VD0_OUT[15:8] Interleaved Cb,Cr VD0_OUT[15] is the MSB
VD0_OUT[7:0] Y VD0_OUT[7] is the MSB
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Table 2-4. 16-bit 601-YCbCr Mode (Video Output Mode 5).

Notes:
• Mode 0/1/2 all use the 8 lsbs and are all RGB output format.
• Mode 0: The throughput is 1 pixel per cycle, and each pixel only sends out one component. The output se-
quence is : P0_R, P1_G, P2_B, P3_R, P4_G,……..
• Mode 1: The throughput is 1/3 pixel per cycle, and each pixel sends out three components. The output se-
quence is : P0_R, P0_G, P0_B, P1_R, P1_G, P1_B…..
• Mode 2: The throughput is 1/4 pixel per cycle, and each pixel sends out three components and one garbage-
byte. The output sequence is: P0_R, P0_G, P0_B, Garbage_byte , P1_R, P1_G, P1_B, Garbage_byte…..

Note that the sequence of the RGB component in the output sequence can be programmed.

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2.4.3 HDMI

• Embedded HDMI 1.4 transmitter

◦ Three lanes of differential TMDS data

◦ One clock lane

• CEC support

• Additional two-wire bus (IDC2) for secure key transfer (refer to Section 2.10 for more information)

2.4.4 MIPI DSI

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• MIPI DSI transmitter with 1 / 2 / 4 lane MIPI output

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• Data transmission in high-speed mode

• Command transmission in high-speed as well as low-power modes

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• DSI format support

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◦ 16-bits per pixel, YCbCr 4:2:2

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◦ 16-bits per pixel, RGB 565

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◦ 24-bits per pixel, RGB 888

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◦ 18-bits per pixel (loosely packed), RGB 666

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2.4.5 MIPI CSI-2

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• MIPI CSI-2 transmitter with 1 / 2 / 4 lane MIPI output

• Data transmission in high-speed mode

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• Command transmission in high-speed as well as low-power modes

• CSI formats support

◦ 16-bits per pixel, YUV422-8bit

◦ 16-bits per pixel, RGB565
◦ RAW8BIT

2.5 Interfaces: Audio Input and Output

The CV2S66 chip includes two I2S controllers. One is a four-channel I2S controller, and the other is a two-chan-
nel I2S controller.

• The four-channel I2S controller supports two I2S input data lanes: I2S_SI_0 and I2S_SI_1; and two
I2S output data lanes: I2S_SO_0 and I2S_SO_1. Refer to Figure 2-2 for more details. Refer to
Chapter 7 “Errata” for restrictions on the I2S_SI_1.

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• The two-channel I2S controller supports one I2S input data lane: I2S_1CH_SI; and one I2S output
data lane: I2S_1CH_SO. Refer to Figure 2-2 for more details.

• All controllers have their own common word / LR clock and bit clock for the I2S data lanes. The data
lanes are clocked by a common clock signal for the given controller.

• Every controller has an independent master clock to drive an external A/D converter.

• The I2S clocks can be configured to operate in master / slave configuration.

• The sampling frequencies supported by the I2S controller for input and output are 8 KHz, 11.025
KHz, 12 KHz, 16 KHz, 22.05 KHz, 24 KHz, 32 KHz, 44.1 KHz, 48 KHz, and 96 KHz.
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• Each I2S data lane typically supports a stereo channel. However, the I2S input data lanes can also
be configured to operate in time division multiplexing (TDM) mode, enabling multiple channels of
audio to be operated on a single data lane.
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• Audio encode / decode including G.711, G726, ADPCM, and AAC are implemented in on-chip soft-
ware.
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I2S_SO_0 (I2S Data) I2S_1CH_SO (I2S Data)

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I2S_SO_1 (I2S Data)

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I2S_SI_0 (I2S Data) I2S_1CH_SI (I2S Data)

Four- Two-
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channel I2S_SI_1 (I2S Data) channel

controller I2S_WS (Word / LR Clock) controller I2S_1CH_WS (Word / LR Clock)
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I2S_CLK (Bit Clock) I2S_1CH_CLK (Bit Clock)

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CLK_AU (Master Clock) CLK_AU_1CH (Master Clock)

Figure 2-2. Audio Input and Output

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2.6 Interfaces: Gigabit Ethernet

• 10- / 100- / 1000-Mbps data transfer rates with an IEEE 802.3-compliant RGMII or RMII interface

• External Gigabit / fast ethernet PHY for communication

• MDIO master interface (optional) for PHY device configuration and management

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2.7 Interfaces: USB

• One USB 2.0 high-speed interface configurable to perform in host or slave mode

• System clock which serves as the reference clock to derive the PHY clock.

• Backward-compatible to USB 1.1 full-speed.

• USB power-on boot mode.

Note:
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Use power-on configuration bit during power-up to configure the USB interface for host / device operation.

2.8 Interfaces: Smart Media Input / Output (SMIO)

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• Smart media input / output (SMIO) pins for NAND flash and SD controllers

• Power-on NAND Flash and eMMC boot modes

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• NAND flash interface

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◦ Memory systems up to 4 GB and 8 Gb flash chips

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◦ Independent NAND / SD card chip selection

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• Two SD controllers for SD / SDIO / SDHC / SDXC / MMC / eMMC memory cards

◦ 32 GB maximum capacity for SDHC

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◦ 2-TB maximum for SDXC

◦ Functions support for all memory cards
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◦ eMMC boot mode with SD0

• SD mode support (see the following table)

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Capacity SDIO
Controller UHS-1 MMC / eMMC Boot Support
SD SDHC SDXC (1.0 or 3.0)
SD0 √ √ √ √ √ √ 3.0
SD1 √ √ √ √ √ 3.0
Table 2-5. Supported SD Modes; Where √ = Supported.

2.9 Interfaces: SSI / SPI

• Four SSI / SPI masters and one SSI / SPI slave

◦ SSI0 master controls up to eight slave devices

◦ SSI1 master controls up to four slave devices
◦ Additional two SSI masters support one slave device each
◦ Remaining SSI / SPI port acts as a dedicated slave

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◦ One dedicated SPI controller supports SPI NOR and SPI NAND boot. Note that this dedicated
controller supports single- / dual- / quad-SPI NOR and SPI NAND. The quad-SPI interface en-
ables a faster boot sequence from the external flash.

• Default device enabled polarity can be inverted with register programming

2.10 Interfaces: I2C / IDC

• One two-wire, bi-directional bus for data communication between the chip and peripheral devices

• Protocol speeds up to 374 Kbit/s

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• Four I2C / IDC masters and one slave interface

• Single master mode.

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2.11 Interfaces: UART

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• Five UART ports

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◦ 4 AHB-bus UART interfaces, 1 APB-bus UART interface

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• Direct memory access (DMA) and hardware flow control in AHB-based UART ports
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• Maximum baud rate of 115200 (based on per-port software settings)

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2.12 Interfaces: General Purpose Input / Output (GPIO)

• 166 programmable CMOS pins for multi-purpose general purpose input / output (GPIO) functions
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• Mmultiplexing with different functions that can be enabled via software

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2.13 Interfaces: Analog-to-Digital Converter (ADC)

• Two channels for analog-to-digital conversion (ADC)

• High / low threshold interrupt generation

• 12-bit resolution

2.14 Interfaces: Power Control (PWC) and Real Time Clock (RTC)

• Power management module (PWC) relies on the real time clock (RTC) for current time and alarm
set

• One 32-bit embedded RTC on the CV2S66 chip:

◦ Current time, alarm set, and power-on and power-off sequence generation
◦ One dedicated always-on power supply pin (remains active even when the core powers off)

Proprietary and Confidential 14

CV2S66 Datasheet - Preliminary

2.15 Interfaces: Stepper and Pulse Width Modulator (PWM)

2.15.1 Stepper Controller

• Three stepper controller channels: (1) SC_A, (2) SC_B and (3) SC_C

• Steppers can be advanced forwards or backwards

• Stepper pins can be used for motor control inside a group with one channel per motor controlled.
Fo

For example, channel A is used for motor A, and pins from other channels do not connect to the
same motor driver.
rM

2.15.2 Pulse Width Modulator (PWM)

• 12 pulse width modulators (PWMs)

C ii
eg

• Used for motor control and / or driving LCD panels for video output (various functions enabled via
software)
on Be
v

2.16 Interfaces: JTAG

fid iji

• JTAG-ICE interface support

Contact an Ambarella representative for details on JTAG.
en ng

Note:
tia O

JTAG chaining is not supported.

l nly

Proprietary and Confidential 15

CV2S66 Datasheet - Preliminary

3. PINS

3.1 Overview of the CV2S66 Pins

This section provides a list of the 716 external pins according to their location on the CV2S66 chip. The figure
below indicates the orientation of the pins by column (numbers) and row (letters).
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

UART3_A UART_A I2S_1CH_ I2S_1CH_ VD0_OUT SD_LVDS SD_LVDS SPCLK_L SD_LVDS SD_LVDS SPCLK_L SD_LVDS SD_LVDS SD_LVDS SD_LVDS SD_LVDS SD_LVDS SD_LVDS SPCLK_L
A VSSI VSSI I2S_WS I2S_SO_1 IDC1CLK IDCSCLK VD0_CLK VSSI VSSI A
HB_TX PB_RX SO SI _1 _N_10 _P_8 VDS_P_2 _P_2 _P_3 VDS_P_1 _P_5 _P_23 _P_21 _P_20 _P_12 _P_13 _P_15 VDS_P_4

UART2_A UART2_A UART3_A UART_A IDCSDAT VD0_HVL VD0_OUT SD_LVDS SD_LVDS SPCLK_L SD_LVDS SD_LVDS SPCLK_L SD_LVDS SD_LVDS SD_LVDS SD_LVDS SD_LVDS SD_LVDS SD_LVDS SPCLK_L SD_LVDS
B VSSI I2S_SI_0 I2S_SI_1 IDC3CLK IDCCLK VSSI B
HB_TX HB_RX HB_RX PB_TX A D _10 _P_10 _N_8 VDS_N_2 _N_2 _N_3 VDS_N_1 _N_5 _N_23 _N_21 _N_20 _N_12 _N_13 _N_15 VDS_N_4 _P_18

UART2_A UART1_A UART0_A

Fo

UART1_A UART1_A UART0_A UART0_A IDC3DAT TEST_M VD0_OUT VD0_HSY SD_LVDS SD_LVDS SD_LVDS SPCLK_L SD_LVDS SD_LVDS SD_LVDS SD_LVDS SPCLK_L SD_LVDS SPCLK_L SD_LVDS SD_LVDS SD_LVDS SD_LVDS SD_LVDS
C HB_CTS_ HB_CTS_ HB_RTS_ VSSI C
HB_RX HB_TX HB_TX HB_RX A ODE _0 NC _P_11 _N_9 _P_0 VDS_N_0 _P_1 _P_4 _P_6 _P_7 VDS_P_5 _P_22 VDS_N_3 _P_14 _P_16 _P_17 _N_18 _P_19
N N N

UART0_A UART2_A UART3_A UART3_A

SSISMOS IDC2DAT SD_LVDS SD_LVDS SD_LVDS SPCLK_L SD_LVDS SD_LVDS SD_LVDS SD_LVDS SPCLK_L SD_LVDS SPCLK_L SD_LVDS SD_LVDS SD_LVDS SD_LVDS
D SSISEN TIMER0 SSISCLK TIMER2 TIMER1 HB_CTS_ HB_RTS_ HB_RTS_ HB_CTS_ IR_IN VSSI D
I A _N_11 _P_9 _N_0 VDS_P_0 _N_1 _N_4 _N_6 _N_7 VDS_N_5 _N_22 VDS_P_3 _N_14 _N_16 _N_17 _N_19
N N N N

UART1_A
SDXC_HS SD_HS_S SSISMIS I2S_1CH_ VD0_OUT VD0_OUT VD0_OUT VD0_OUT VD0_OUT VD0_OUT VD0_OUT DDR0_DQ DDR0_DQ ADC_CH ADC_CH
E SC_A3 SC_B0 SC_B3 SC_B2 SC_B1 HB_RTS_ I2S_SO_0 IDCDATA VD_PWM VSSI VSSI AVDD33 VSSI E
_SEL EL O WS _13 _14 _4 _6 _3 _7 _9 _2_LP4 _7_LP4 _0 _1
rM

DDR0_DQ
DDR0_DQ DDR0_D DDR0_DQ DDR0_DQ
F PWM0 PWM2 SC_A0 SC_A2 SC_A1 S_BAR_0 F
_1_LP4 M_0_LP4 _0_LP4 _3_LP4
_LP4

DEBOUN
DDR1_DQ DETECT_ P_GPIO1_ P_GPIO1_ VD0_OUT VD0_OUT VD0_OUT VD0_OUT VD0_OUT VD0_OUT VD0_VSY P_M IPI_A DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ DDR0_DQ
G PWM1 CE_GPIO HPD VSSI VSSI VDDI VDDI AVDD AVDD18 G
S_0_LP4 VBUS VDDO VDDO _11 _12 _15 _5 _2 _8 NC VDD18_IO _9_LP4 _4_LP4 _5_LP4 _6_LP4 S_0_LP4
_1

DDR1_DQ DEBOUN
DDR1_DQ DDR1_DQ DDR0_DQ DDR0_DQ DDR0_D DDR0_DQ DDR0_DQ
H S_BAR_0 CE_GPIO VSSI OTP_VPP VSSI VDDP VDDP VDDP VDDI VDDP VSSI VDDI VSSI VDDI VSSI VDDI VDDP AVDD AVDD18 H
C ii
_2_LP4 _0_LP4 _10_LP4 _11_LP4 M_1_LP4 _8_LP4 S_1_LP4
_LP4 _0
eg

DDR0_CA DDR0_DQ
DDR1_DQ DDR1_D DDR1_DQ DDR1_DQ DDR0_DQ DDR0_DQ DDR0_DQ
J VSSI OTP_VPP VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI AVSS VSSI _3_A_LP S_BAR_1 J
_1_LP4 M_0_LP4 _3_LP4 _6_LP4 _15_LP4 _13_LP4 _14_LP4
4 _LP4
on Be
DDR0_CA DDR0_CA DDR0_CA DDR0_CA
DDR1_DQ DDR1_DQ DDR1_DQ DDR0_DQ
K VSSI VSSI AVDD VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI AVSS VSSI _2_A_LP _4_A_LP _1_A_LP _0_A_LP K
_4_LP4 _5_LP4 _7_LP4 _12_LP4
4 4 4 4
v

DDR0_CS DDR0_CA
DDR1_DQ DDR1_DQ DDR1_DQ P_DDR1_ P_DDR1_ P_DDR0_ P_DDR0_ DDR0_CS DDR0_CK
L VSSI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VSSI _2_A_LP _5_A_LP L
S_1_LP4 _11_LP4 _10_LP4 VDDQ VDDQ_X VDDQ_X VDDQ _A_LP4 _A_LP4
4 4

DDR1_DQ DDR0_CA DDR0_CA DDR0_CA DDR0_CK

DDR1_DQ DDR1_DQ P_DDR1_ P_DDR1_ P_DDR0_ P_DDR0_
fid iji
M S_BAR_1 VSSI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VSSI _0_B_LP _2_B_LP _1_B_LP _A_BAR_ M
_8_LP4 _13_LP4 VDDQ VDDQ_X VDDQ_X VDDQ
_LP4 4 4 4 LP4

DDR0_CA DDR0_CA DDR0_CK

DDR1_DQ DDR1_D DDR1_DQ P_DDR1_ P_DDR1_ P_DDR0_ P_DDR0_ DDR0_CS
N VSSI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VSSI _4_B_LP _3_B_LP _B_BAR_ N
_15_LP4 M_1_LP4 _9_LP4 VDDQ VDDQ_X VDDQ_X VDDQ _B_LP4
4 4 LP4

DDR1_CA DDR0_CA
DDR1_CK DDR1_DQ DDR1_DQ P_DDR1_ P_DDR1_ P_DDR0_ P_DDR0_ DDR0_DQ DDR0_DQ DDR0_CK
P _3_A_LP VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VSSI _5_B_LP P
_A_LP4 _14_LP4 _12_LP4 VDDQ VDDQ_X VDDQ_X VDDQ _20_LP4 _23_LP4 _B_LP4
en ng
4 4

DDR1_CK DDR1_CA DDR1_CA DDR1_CS DDR0_CS

P_DDR1_ P_DDR1_ P_DDR0_ P_DDR0_ DDR0_DQ DDR0_D DDR0_DQ
R _A_BAR_ _0_A_LP _4_A_LP _2_A_LP VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VSSI _2_B_LP R
VDDQ VDDQ_X VDDQ_X VDDQ _22_LP4 M_2_LP4 _19_LP4
LP4 4 4 4 4

DDR1_CA DDR1_CA DDR1_CA DDR0_DQ

DDR1_CS P_DDR1_ P_DDR1_ P_DDR0_ P_DDR0_ DDR0_DQ DDR0_DQ DDR0_DQ
T _1_A_LP _2_A_LP _5_A_LP VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VSSI S_BAR_2 T
_A_LP4 VDDQ VDDQ_X VDDQ_X VDDQ _16_LP4 _17_LP4 _21_LP4
4 4 4 _LP4
tia O
DDR1_CK DDR1_CA DDR1_CA DDR1_CA DDR0_RE DDR0_CK
P_DDR1_ P_DDR1_ P_DDR0_ P_DDR0_ DDR0_DQ DDR0_DQ
U _B_BAR_ _2_B_LP _3_B_LP _1_B_LP VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VSSI SET_LP4 E_LP4_L U
VDDQ VDDQ_X VDDQ_X VDDQ _18_LP4 S_2_LP4
LP4 4 4 4 _LP3 P3

DDR1_CS DDR1_CA DDR1_CA P_HDM I_ DDR0_DQ

DDR1_CK P_DDR1_ P_DDR0_ DDR0_DQ DDR0_DQ DDR0_DQ
V _2_B_LP _4_B_LP _0_B_LP AVDD33_ AVSS AVDD33 AVSS VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VSSI VSSI S_BAR_3 V
_B_LP4 VDDQ VDDQ _29_LP4 _28_LP4 _31_LP4
4 4 4 ESD _LP4
l nly
DDR1_CA
DDR1_DQ DDR1_DQ DDR1_CS P_PW C_A P_DDR1_ P_DDR0_ DDR0_DQ DDR0_D DDR0_DQ DDR0_DQ
W _5_B_LP AVSS AVSS AVSS VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VSSI VSSI W
S_2_LP4 _21_LP4 _B_LP4 VDD33 VDDQ VDDQ _30_LP4 M_3_LP4 _27_LP4 S_3_LP4
4

DDR1_DQ DDR0_CK
DDR1_DQ DDR1_DQ DDR1_DQ P_PW C_A P_DDR1_ P_GPIO2_ P_DDR0_ DDR0_DQ DDR0_DQ DDR0_DQ
Y S_BAR_2 AVDD18 AVSS AVDD VDDI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI VDDP VSSI E_2_LP4 Y
_20_LP4 _19_LP4 _22_LP4 VDD18 VDDQ VDDO VDDQ _25_LP4 _24_LP4 _26_LP4
_LP4 _LP3

P_DDR0_ DDR0_CA
DDR1_D DDR1_DQ DDR1_DQ DDR1_DQ P_DDR1_ AVDDH_ P_GPIO2_ P_DDR0_ P_DSI_AV
AA VSSI AVSS AVDD VDDI VDDI VSSI VDDI VSSI VDDI VSSI VDDI VSSI AVDD VSSI VDDQ_CK LIBR_LP AVSS AA
M_2_LP4 _23_LP4 _17_LP4 _16_LP4 VDDQ PLL VDDO VDDQ DD12
E 4

DDR1_CK
DDR1_DQ DDR1_DQ DDR1_DQ I2S_1CH_ DAC_CO P_SENSO P_USB0_ P_USB0_ P_ENET_ P_SD_VD P_SDXC_ MIPI_DSI MIPI_DSI
AB VSSI E_LP4_L CLK_AU XI_RTC VSSI VSSI SMIO_33 SMIO_29 VSSI AVDD AVDD18 SMIO_6 AVSS AB
_18_LP4 _31_LP4 _28_LP4 CLK MP R_VDDO DVDD VDDH0 VDDO DO VDDO _DN_3 _DP_3
P3

DDR1_DQ
DDR1_DQ DDR1_DQ AVDDH_ MIPI_DSI MIPI_DSI
AC S_BAR_3 VSSI XO_RTC SMIO_11 SMIO_10 AC
S_3_LP4 _24_LP4 PLL _DN_2 _DP_2
_LP4

DDR1_DQ DDR1_DQ DDR1_DQ PWC_WK PWC_WK PWC_PS PWC_RS GPIO_ GPIO_ P_USB0_ JTAG_TD ENET_TX ENET_MD MIPI_DSI MIPI_DSI
AD IDC2CLK VSSI 160 SSI2EN0 CLK_SI SMIO_38 SMIO_24 SMIO_9 SMIO_17 SMIO_30 SMIO_8 VSSI SMIO_15 SMIO_0 AD
_29_LP4 _30_LP4 _25_LP4 UP1 UP EQ1 TINB 158 VDD330 O D_2 IO _DN_1 _DP_1

DDR1_CK ENET_EX
DDR1_DQ DDR1_D HDMI_RE CLK_AU_ IDC1DAT SVSYNC SVSYNC SSI2MOS SSI0MIS USB_REX JTAG_RS ENET_TX MIPI_DSI MIPI_DSI
AE E_2_LP4 I2S_CLK POR_L SHSYNC T_OSC_ SMIO_5 SMIO_3 SMIO_21 SMIO_19 SMIO_32 SMIO_26 WP SMIO_13 SMIO_12 AE
_26_LP4 M_3_LP4 XT 1CH A 1 3 I O T T_L EN _DN_0 _DP_0
_LP3 CLK

P_DDR1_ P_HDM I_ DDR1_RE

DDR1_DQ GPIO_ GPIO_ SSI3MIS SVSYNC SSI3MOS SSI0MOS SENSOR_ JTAG_TD ENET_TX ENET_RX ENET_MD ENET_CL MIPI_DSI MIPI_DSI
AF VDDQ_CK AVDD15_ SET_LP4 XX_CEC SSI0EN0 SMIO_23 SMIO_2 SMIO_18 SMIO_35 SMIO_27 AVSS SMIO_1 SMIO_16 AF
_27_LP4 161 159 O 4 I I RST I D_1 DV C K_RX _DN_CLK _DP_CLK
E ESD _LP3

DDR1_CA
HDMI_CL HDMI_CH HDMI_CH HDMI_CH DAC_VR SVSYNC SVSYNC CLK_SI_ JTAG_T JTAG_C ENET_RX ENET_RX ENET_GT P_NAND_
AG VSSI LIBR_LP SSI3EN0 SSI2CLK SSI0EN1 SMIO_4 SMIO_20 SMIO_36 SMIO_37 SMIO_28 VSSI XOUT AVSS VSSI AG
K_M 0_M 1_M 2_M EFIN 2 0 1 MS LK D_2 D_1 X_CLK VDDO
4

HDMI_CL HDMI_CH HDMI_CH HDMI_CH DAC_RSE SSI2MIS ENET_TX ENET_TX ENET_RX ENET_RX ENET_CL
AH VSSI VSSI DAC_IO SSI3CLK SSI0CLK USB_DM USB_DP SMIO_25 SMIO_22 SMIO_39 SMIO_34 SMIO_31 SMIO_7 SMIO_14 XIN VSSI VSSI AH
K_P 0_P 1_P 2_P T O D_3 D_0 D_0 D_3 K_TX

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Figure 3-1. Pin Map for the CV2S66 Chip.

The following table lists all of the external pins on the CV2S66 chip in order by map location. Each entry provides
the pin name as it appears on the ball map, the location of the pin on the map and on schematics, the functional

Proprietary and Confidential 16

CV2S66 Datasheet - Preliminary

class, and multiplexed functionality detail if applicable.

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
A1 VSSI GROUND
A2 VSSI GROUND
UART3_AHB_ uart3_ahb_
A3 TX
UART 155 pwm10
tx
UART_APB_
A4 RX
UART 39 uart_apb_rx
A5 I2S_1CH_SO I2S 46 i2s_1ch_so
Fo

A6 I2S_1CH_SI I2S 45 i2s_1ch_si

A7 I2S_WS I2S 53 i2s_ws
A8 I2S_SO_1 I2S 52 i2s_so_1
rM

A9 IDC1CLK I2C 13 idc1clk

A10 IDCSCLK I2C 19 idcsclk
A11 VD0_CLK VOUT 137 vd0_clk
A12 VD0_OUT_1 VOUT 122 vd0_out[1]
C ii
eg

SD_
A13 LVDS_N_10
VIN
on Be

A14 SD_LVDS_P_8 VIN

v

SPCLK_
A15 LVDS_P_2
VIN
fid iji

A16 SD_LVDS_P_2 VIN

A17 SD_LVDS_P_3 VIN
SPCLK_
en ng

A18 LVDS_P_1
VIN
A19 SD_LVDS_P_5 VIN
SD_
A20 VIN
tia O

LVDS_P_23
SD_
A21 LVDS_P_21
VIN
l nly

SD_
A22 LVDS_P_20
VIN
SD_
A23 LVDS_P_12
VIN
SD_
A24 LVDS_P_13
VIN
SD_
A25 LVDS_P_15
VIN
SPCLK_
A26 LVDS_P_4
VIN
A27 VSSI GROUND
A28 VSSI GROUND
B1 VSSI GROUND
UART2_AHB_ uart2_ahb_
B2 TX
UART 151 pwm10
tx
UART2_AHB_ uart2_ahb_
B3 RX
UART 150
rx
UART3_AHB_ uart3_ahb_
B4 RX
UART 154
rx

Proprietary and Confidential 17

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
UART_APB_
B5 TX
UART 40 uart_apb_tx
B6 I2S_SI_0 I2S 49 i2s_si_0
B7 I2S_SI_1 I2S 51 i2s_si_1
B8 IDC3CLK I2C 17 idc3clk pwm8
B9 IDCCLK I2C 11 idc0clk
B10 IDCSDATA I2C 20 idcsdata
B11 VD0_HVLD VOUT 140 vd0_hvld
B12 VD0_OUT_10 VOUT 131 vd0_out[10]
Fo

SD_
B13 LVDS_P_10
VIN
B14 SD_LVDS_N_8 VIN
rM

SPCLK_
B15 LVDS_N_2
VIN
B16 SD_LVDS_N_2 VIN
B17 SD_LVDS_N_3 VIN
C ii
eg

SPCLK_
B18 LVDS_N_1
VIN
on Be

B19 SD_LVDS_N_5 VIN

v

SD_
B20 LVDS_N_23
VIN
fid iji

SD_
B21 LVDS_N_21
VIN
SD_
B22 VIN
en ng

LVDS_N_20
SD_
B23 LVDS_N_12
VIN
SD_
tia O

B24 LVDS_N_13
VIN
SD_
B25 LVDS_N_15
VIN
l nly

SPCLK_
B26 LVDS_N_4
VIN
SD_
B27 LVDS_P_18
VIN
B28 VSSI GROUND
UART2_AHB_ uart2_ahb_
C1 CTS_N
UART 152
cts_n
UART1_AHB_
C2 RX
UART
UART1_AHB_
C3 TX
UART
UART1_AHB_ uart1_ahb_
C4 CTS_N
UART 148
cts_n
UART0_AHB_ uart0_ahb_
C5 TX
UART 143 ssi1_txd
tx
UART0_AHB_ uart0_ahb_
C6 RX
UART 142 ssi1_sdk
rx
UART0_AHB_ uart0_ahb_
C7 RTS_N
UART 145 ssi1_en0
rts_n

Proprietary and Confidential 18

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
C8 VSSI GROUND
C9 IDC3DATA I2C 18 idc3data pwm9
C10 TEST_MODE GLOBAL
C11 VD0_OUT_0 VOUT 121 vd0_out[0]
C12 VD0_HSYNC VOUT 139 vd0_hsync
SD_
C13 LVDS_P_11
VIN
C14 SD_LVDS_N_9 VIN
C15 SD_LVDS_P_0 VIN
Fo

SPCLK_
C16 LVDS_N_0
VIN
C17 SD_LVDS_P_1 VIN
rM

C18 SD_LVDS_P_4 VIN

C19 SD_LVDS_P_6 VIN
C20 SD_LVDS_P_7 VIN
SPCLK_
C ii

C21 VIN
eg

LVDS_P_5
SD_
on Be

C22 LVDS_P_22
VIN
v

SPCLK_
C23 LVDS_N_3
VIN
fid iji

SD_
C24 LVDS_P_14
VIN
SD_
C25 LVDS_P_16
VIN
en ng

SD_
C26 LVDS_P_17
VIN
SD_
tia O

C27 LVDS_N_18
VIN
SD_
C28 LVDS_P_19
VIN
l nly

ehci_prt_
D1 SSISEN SSI 38 ssis_en ssi1_en0
pwr_1
D2 TIMER0 TIMER 8 tm11_clk pwm7
ehci_app_
D3 SSISCLK SSI 35 ssis_sclk ssi1_sdk
prt_ovcurr0
idsp_pip_io-
D4 TIMER2 TIMER 10 tm13_clk pad_mas-
ter_hsync
ehci_app_
D5 SSISMOSI SSI 36 ssis_rxd ssi1_txd
prt_ovcurr1
idsp_pip_io-
D6 TIMER1 TIMER 9 tm12_clk pad_mas-
ter_vsync
UART0_AHB_ uart0_ahb_
D7 CTS_N
UART 144 ssi1_rxd
cts_n
UART2_AHB_ uart2_ahb_
D8 RTS_N
UART 153 pwm11
rts_n
UART3_AHB_ uart3_ahb_
D9 RTS_N
UART 157 pwm9
rts_n

Proprietary and Confidential 19

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
UART3_AHB_ uart3_ahb_
D10 CTS_N
UART 156
cts_n
D11 IDC2DATA I2C 16 idc2data pwm4
D12 IR_IN IR 21 ir_in wdt_ext_rst_l
SD_
D13 LVDS_N_11
VIN
D14 SD_LVDS_P_9 VIN
D15 SD_LVDS_N_0 VIN
SPCLK_
D16 VIN
Fo

LVDS_P_0
D17 SD_LVDS_N_1 VIN
D18 SD_LVDS_N_4 VIN
rM

D19 SD_LVDS_N_6 VIN

D20 SD_LVDS_N_7 VIN
SPCLK_
D21 LVDS_N_5
VIN
C ii

SD_
eg

D22 LVDS_N_22
VIN
on Be

SPCLK_
D23 LVDS_P_3
VIN
v

SD_
D24 LVDS_N_14
VIN
fid iji

SD_
D25 LVDS_N_16
VIN
SD_
D26 VIN
en ng

LVDS_N_17
D27 VSSI GROUND
SD_
D28 VIN
tia O

LVDS_N_19
E1 SC_A3 MOTOR 3 sc_a3 ssi1_en0 pwm6
E2 SC_B0 MOTOR 4 sc_b0 ssi1_en1 wdt_ext_rst_l
l nly

enet_ptp_ enet_ptp_
E3 SC_B3 MOTOR 7 sc_b3
pps_o pps_o
E4 SC_B2 MOTOR 6 sc_b2 ssi1_en3 vin_strig1
SDXC_HS_
E5 SEL
VIN 163 sdxc_hs_sel

E6 SD_HS_SEL VIN 162 sd_hs_sel

ehci_prt_
E7 SSISMISO SSI 37 ssis_txd ssi_rxd
pwr_0
E8 SC_B1 MOTOR 5 sc_b1 ssi1_en2 vin_strig0
UART1_AHB_ uart1_ahb_
E9 RTS_N
UART 149 pwm11
rts_n
E10 I2S_1CH_WS I2S 47 i2s_1ch_ws
E11 I2S_SO_0 I2S 50 i2s_so_0
E12 IDCDATA I2C 12 idc0data
E13 VD0_OUT_13 VOUT 134 vd0_out[13]
E14 VD0_OUT_14 VOUT 135 vd0_out[14]
E15 VD0_OUT_4 VOUT 125 vd0_out[4]
E16 VD0_OUT_6 VOUT 127 vd0_out[6]
E17 VD0_OUT_3 VOUT 124 vd0_out[3]

Proprietary and Confidential 20

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
E18 VD0_OUT_7 VOUT 128 vd0_out[7]
E19 VD0_OUT_9 VOUT 130 vd0_out[9]
E20 VD_PWM VOUT 141 pwm0
E21 VSSI GROUND
E22 VSSI GROUND
E23 AVDD33 POWER
E24 VSSI GROUND
DDR0_DQ_2_
E25 LP4
DDR
Fo

DDR0_DQ_7_
E26 LP4
DDR
E27 ADC_CH_0 ADC
rM

E28 ADC_CH_1 ADC

F1 PWM0 PWM 41 pwm0
F2 PWM2 PWM 43 pwm2 wdt_ext_rst_l
F3 SC_A0 MOTOR 0 sc_a0 ssi1_sdk pwm3
C ii
eg

F4 SC_A2 MOTOR 2 sc_a2 ssi1_rxd pwm5

F5 SC_A1 MOTOR 1 sc_a1 ssi1_txd pwm4
on Be

DDR0_DQ_1_
F24 DDR
v

LP4
DDR0_DM_0_
F25 DDR
fid iji

LP4
DDR0_DQ_0_
F26 LP4
DDR
en ng

DDR0_DQ_3_
F27 LP4
DDR
DDR0_DQS_
F28 BAR_0_LP4
DDR
tia O

DDR1_DQS_0_
G1 LP4
DDR
G2 PWM1 PWM 42 pwm1
l nly

DEBOUNCE_
G3 GPIO_1
Other 165

G4 HPD HDMI 111 hdmitx_hpd

DETECT_
G5 VBUS
USB
G7 VSSI GROUND
G8 VSSI GROUND
G9 VDDI POWER
G10 VDDI POWER
P_GPIO1_
G11 VDDO
POWER
P_GPIO1_
G12 VDDO
POWER
G13 VD0_OUT_11 VOUT 132 vd0_out[11]
G14 VD0_OUT_12 VOUT 133 vd0_out[12]
G15 VD0_OUT_15 VOUT 136 vd0_out[15]
G16 VD0_OUT_5 VOUT 126 vd0_out[5]
G17 VD0_OUT_2 VOUT 123 vd0_out[2]
G18 VD0_OUT_8 VOUT 129 vd0_out[8]

Proprietary and Confidential 21

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
G19 VD0_VSYNC VOUT 138 vd0_vsync
P_MIPI_
G20 AVDD18_IO POWER
G21 AVDD POWER
G22 AVDD18 POWER
DDR0_DQ_9_
G24 LP4 DDR
DDR0_DQ_4_
G25 LP4 DDR
Fo

DDR0_DQ_5_
G26 LP4 DDR
DDR0_DQ_6_
G27 LP4 DDR
rM

DDR0_DQS_0_
G28 LP4 DDR
DDR1_DQS_
H1 BAR_0_LP4
DDR
C ii
eg

DDR1_DQ_2_
H2 LP4
DDR
on Be

DDR1_DQ_0_
H3 LP4
DDR
v

DEBOUNCE_
H4 GPIO_0
Other 164
fid iji

H5 VSSI GROUND
H7 OTP_VPP OTP
H8 VSSI GROUND
en ng

H9 VDDP POWER
H10 VDDP POWER
H11 VDDP POWER
tia O

H12 VDDI POWER

H13 VDDP POWER
l nly

H14 VSSI GROUND

H15 VDDI POWER
H16 VSSI GROUND
H17 VDDI POWER
H18 VSSI GROUND
H19 VDDI POWER
H20 VDDP POWER
H21 AVDD POWER
H22 AVDD18 POWER
DDR0_DQ_10_
H24 LP4
DDR
DDR0_DQ_11_
H25 LP4
DDR
DDR0_DM_1_
H26 LP4
DDR
DDR0_DQ_8_
H27 LP4
DDR
DDR0_DQS_1_
H28 LP4
DDR

Proprietary and Confidential 22

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
DDR1_DQ_1_
J1 LP4
DDR
DDR1_DM_0_
J2 LP4
DDR
DDR1_DQ_3_
J3 LP4
DDR
DDR1_DQ_6_
J4 LP4
DDR
J5 VSSI GROUND
J7 OTP_VPP OTP
Fo

J8 VSSI GROUND
J9 VDDI POWER
J10 VSSI GROUND
rM

J11 VDDI POWER

J12 VSSI GROUND
J13 VDDI POWER
C ii

J14 VSSI GROUND

eg

J15 VDDI POWER

on Be

J16 VSSI GROUND

J17 VDDI POWER
v

J18 VSSI GROUND

fid iji

J19 VDDI POWER

J20 VSSI GROUND
J21 AVSS GROUND
en ng

J22 VSSI GROUND

DDR0_
J24 CA_3_A_LP4
DDR
tia O

DDR0_DQ_15_
J25 LP4
DDR
DDR0_DQ_13_
J26 LP4
DDR
l nly

DDR0_DQ_14_
J27 LP4
DDR
DDR0_DQS_
J28 BAR_1_LP4
DDR
DDR1_DQ_4_
K1 LP4
DDR
DDR1_DQ_5_
K2 LP4
DDR
DDR1_DQ_7_
K3 LP4
DDR
K4 VSSI GROUND
K5 VSSI GROUND
K7 AVDD POWER
K8 VSSI GROUND
K9 VDDI POWER
K10 VSSI GROUND
K11 VDDI POWER
K12 VSSI GROUND
K13 VDDI POWER

Proprietary and Confidential 23

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
K14 VSSI GROUND
K15 VDDI POWER
K16 VSSI GROUND
K17 VDDI POWER
K18 VSSI GROUND
K19 VDDI POWER
K20 VSSI GROUND
K21 AVSS GROUND
K22 VSSI GROUND
Fo

DDR0_
K24 CA_2_A_LP4
DDR
DDR0_
K25 DDR
rM

CA_4_A_LP4
DDR0_DQ_12_
K26 LP4
DDR
DDR0_
K27 DDR
C ii

CA_1_A_LP4
eg

DDR0_
K28 DDR
on Be
CA_0_A_LP4
DDR1_DQS_1_
L1 DDR
v

LP4
DDR1_DQ_11_
fid iji

L2 LP4
DDR
DDR1_DQ_10_
L3 LP4
DDR
en ng

L4 VSSI GROUND
L5 VSSI GROUND
P_DDR1_
L7 POWER
tia O

VDDQ
P_DDR1_
L8 VDDQ_X
POWER
l nly

L9 VDDI POWER
L10 VSSI GROUND
L11 VDDI POWER
L12 VSSI GROUND
L13 VDDI POWER
L14 VSSI GROUND
L15 VDDI POWER
L16 VSSI GROUND
L17 VDDI POWER
L18 VSSI GROUND
L19 VDDI POWER
P_DDR0_
L20 VDDQ_X
POWER
P_DDR0_
L21 VDDQ
POWER
L22 VSSI GROUND
L24 VSSI GROUND
DDR0_
L25 CS_2_A_LP4
DDR

Proprietary and Confidential 24

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
DDR0_CS_A_
L26 LP4
DDR
DDR0_
L27 CA_5_A_LP4
DDR
DDR0_CK_A_
L28 LP4
DDR
DDR1_DQS_
M1 BAR_1_LP4
DDR
DDR1_DQ_8_
M2 LP4
DDR
Fo

DDR1_DQ_13_
M3 LP4
DDR
M4 VSSI GROUND
rM

M5 VSSI GROUND
P_DDR1_
M7 VDDQ
POWER
P_DDR1_
M8 POWER
C ii

VDDQ_X
eg

M9 VDDI POWER
on Be

M10 VSSI GROUND

M11 VDDI POWER
v

M12 VSSI GROUND

fid iji

M13 VDDI POWER

M14 VSSI GROUND
M15 VDDI POWER
en ng

M16 VSSI GROUND

M17 VDDI POWER
M18 VSSI GROUND
tia O

M19 VDDI POWER

P_DDR0_
M20 VDDQ_X
POWER
l nly

P_DDR0_
M21 VDDQ
POWER
M22 VSSI GROUND
M24 VSSI GROUND
DDR0_
M25 CA_0_B_LP4
DDR
DDR0_
M26 CA_2_B_LP4
DDR
DDR0_
M27 CA_1_B_LP4
DDR
DDR0_CK_A_
M28 BAR_LP4
DDR
DDR1_DQ_15_
N1 LP4
DDR
DDR1_DM_1_
N2 LP4
DDR
DDR1_DQ_9_
N3 LP4
DDR
N4 VSSI GROUND
N5 VSSI GROUND

Proprietary and Confidential 25

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
P_DDR1_
N7 VDDQ
DDR
P_DDR1_
N8 VDDQ_X
DDR
N9 VDDI POWER
N10 VSSI GROUND
N11 VDDI POWER
N12 VSSI GROUND
N13 VDDI POWER
Fo

N14 VSSI GROUND

N15 VDDI POWER
N16 VSSI GROUND
rM

N17 VDDI POWER

N18 VSSI GROUND
N19 VDDI POWER
P_DDR0_
N20 POWER
C ii
eg

VDDQ_X
P_DDR0_
N21 POWER
on Be

VDDQ
N22 VSSI GROUND
v

N24 VSSI GROUND

fid iji

DDR0_CS_B_
N25 LP4
DDR
DDR0_
N26 CA_4_B_LP4
DDR
en ng

DDR0_
N27 CA_3_B_LP4
DDR
DDR0_CK_B_
tia O

N28 BAR_LP4
DDR
DDR1_CK_A_
P1 LP4
DDR
l nly

DDR1_
P2 CA_3_A_LP4
DDR
DDR1_DQ_14_
P3 LP4
DDR
DDR1_DQ_12_
P4 LP4
DDR
P5 VSSI GROUND
P_DDR1_
P7 VDDQ
POWER
P_DDR1_
P8 VDDQ_X
POWER
P9 VDDI POWER
P10 VSSI GROUND
P11 VDDI POWER
P12 VSSI GROUND
P13 VDDI POWER
P14 VSSI GROUND
P15 VDDI POWER
P16 VSSI GROUND

Proprietary and Confidential 26

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
P17 VDDI POWER
P18 VSSI GROUND
P19 VDDI POWER
P_DDR0_
P20 VDDQ_X
POWER
P_DDR0_
P21 VDDQ
POWER
P22 VSSI GROUND
P24 VSSI GROUND
Fo

DDR0_DQ_20_
P25 LP4
DDR
DDR0_DQ_23_
P26 LP4
DDR
rM

DDR0_
P27 CA_5_B_LP4
DDR
DDR0_CK_B_
P28 LP4
DDR
C ii
eg

DDR1_CK_A_
R1 BAR_LP4
DDR
on Be

DDR1_
R2 CA_0_A_LP4
DDR
v

DDR1_
R3 DDR
fid iji

CA_4_A_LP4
DDR1_
R4 CS_2_A_LP4
DDR
R5 VSSI GROUND
en ng

P_DDR1_
R7 VDDQ
POWER
P_DDR1_
tia O

R8 VDDQ_X
POWER
R9 VDDI POWER
R10 VSSI GROUND
l nly

R11 VDDI POWER

R12 VSSI GROUND
R13 VDDI POWER
R14 VSSI GROUND
R15 VDDI POWER
R16 VSSI GROUND
R17 VDDI POWER
R18 VSSI GROUND
R19 VDDI POWER
P_DDR0_
R20 VDDQ_X
POWER
P_DDR0_
R21 VDDQ
POWER
R22 VSSI GROUND
R24 VSSI GROUND
DDR0_DQ_22_
R25 LP4
DDR
DDR0_DM_2_
R26 LP4
DDR

Proprietary and Confidential 27

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
DDR0_DQ_19_
R27 LP4
DDR
DDR0_
R28 CS_2_B_LP4
DDR
DDR1_
T1 CA_1_A_LP4
DDR
DDR1_
T2 CA_2_A_LP4
DDR
DDR1_
T3 CA_5_A_LP4
DDR
Fo

DDR1_CS_A_
T4 LP4
DDR
T5 VSSI GROUND
rM

P_DDR1_
T7 VDDQ
POWER
P_DDR1_
T8 VDDQ_X
POWER
C ii

T9 VDDI POWER
eg

T10 VSSI GROUND

on Be

T11 VDDI POWER

T12 VSSI GROUND
v

T13 VDDI POWER

fid iji

T14 VSSI GROUND

T15 VDDI POWER
T16 VSSI GROUND
en ng

T17 VDDI POWER

T18 VSSI GROUND
T19 VDDI POWER
tia O

P_DDR0_
T20 VDDQ_X
POWER
P_DDR0_
T21 POWER
l nly

VDDQ
T22 VSSI GROUND
T24 VSSI GROUND
DDR0_DQ_16_
T25 LP4
DDR
DDR0_DQ_17_
T26 LP4
DDR
DDR0_DQ_21_
T27 LP4
DDR
DDR0_DQS_
T28 BAR_2_LP4
DDR
DDR1_CK_B_
U1 BAR_LP4
DDR
DDR1_
U2 CA_2_B_LP4
DDR
DDR1_
U3 CA_3_B_LP4
DDR
DDR1_
U4 CA_1_B_LP4
DDR
U5 VSSI GROUND

Proprietary and Confidential 28

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
P_DDR1_
U7 VDDQ
POWER
P_DDR1_
U8 VDDQ_X
POWER
U9 VDDI POWER
U10 VSSI GROUND
U11 VDDI POWER
U12 VSSI GROUND
U13 VDDI POWER
Fo

U14 VSSI GROUND

U15 VDDI POWER
U16 VSSI GROUND
rM

U17 VDDI POWER

U18 VSSI GROUND
U19 VDDI POWER
P_DDR0_
U20 POWER
C ii
eg

VDDQ_X
P_DDR0_
U21 POWER
on Be

VDDQ
U22 VSSI GROUND
v

U24 VSSI GROUND

fid iji

DDR0_RE-
U25 SET_LP4_LP3
DDR
DDR0_CKE_
U26 LP4_LP3
DDR
en ng

DDR0_DQ_18_
U27 LP4
DDR
DDR0_DQS_2_
tia O

U28 LP4
DDR
DDR1_CK_B_
V1 LP4
DDR
l nly

DDR1_
V2 CS_2_B_LP4
DDR
DDR1_
V3 CA_4_B_LP4
DDR
DDR1_
V4 CA_0_B_LP4
DDR
P_HDMI_
V5 AVDD33_ESD
POWER
P_DDR1_
V7 VDDQ
POWER
V8 AVSS GROUND
V9 AVDD33 POWER
V10 AVSS GROUND
V11 VDDI POWER
V12 VSSI GROUND
V13 VDDI POWER
V14 VSSI GROUND
V15 VDDI POWER
V16 VSSI GROUND

Proprietary and Confidential 29

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
V17 VDDI POWER
V18 VSSI GROUND
V19 VDDI POWER
V20 VSSI GROUND
P_DDR0_
V21 VDDQ
POWER
V22 VSSI GROUND
V24 VSSI GROUND
DDR0_DQ_29_
V25 DDR
Fo

LP4
DDR0_DQ_28_
V26 LP4
DDR
DDR0_DQ_31_
rM

V27 LP4
DDR
DDR0_DQS_
V28 BAR_3_LP4
DDR
DDR1_DQS_2_
C ii

W1 DDR
eg

LP4
DDR1_DQ_21_
on Be

W2 LP4
DDR
v

DDR1_
W3 CA_5_B_LP4
DDR
fid iji

DDR1_CS_B_
W4 LP4
DDR
P_PWC_
W5 AVDD33
POWER
en ng

P_DDR1_
W7 VDDQ
POWER
W8 AVSS GROUND
tia O

W9 AVSS GROUND
W10 AVSS GROUND
W11 VDDI POWER
l nly

W12 VSSI GROUND

W13 VDDI POWER
W14 VSSI GROUND
W15 VDDI POWER
W16 VSSI GROUND
W17 VDDI POWER
W18 VSSI GROUND
W19 VDDI POWER
W20 VSSI GROUND
P_DDR0_
W21 VDDQ
POWER
W22 VSSI GROUND
W24 VSSI GROUND
DDR0_DQ_30_
W25 LP4
DDR
DDR0_DM_3_
W26 LP4
DDR

Proprietary and Confidential 30

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
DDR0_DQ_27_
W27 LP4
DDR
DDR0_DQS_3_
W28 LP4
DDR
DDR1_DQS_
Y1 BAR_2_LP4
DDR
DDR1_DQ_20_
Y2 LP4
DDR
DDR1_DQ_19_
Y3 LP4
DDR
Fo

DDR1_DQ_22_
Y4 LP4
DDR
P_PWC_
Y5 AVDD18
POWER
rM

P_DDR1_
Y7 VDDQ
POWER
Y8 AVDD18 POWER
C ii

Y9 AVSS GROUND
eg

Y10 AVDD POWER

on Be

Y11 VDDI POWER

P_GPIO2_
v

Y12 VDDO
POWER
Y13 POWER
fid iji
VDDI
Y14 VSSI GROUND
Y15 VDDI POWER
en ng

Y16 VSSI GROUND

Y17 VDDI POWER
Y18 VSSI GROUND
tia O

Y19 VDDI POWER

Y20 VSSI GROUND
P_DDR0_
Y21 POWER
l nly

VDDQ
Y22 VDDP POWER
Y24 VSSI GROUND
DDR0_DQ_25_
Y25 LP4
DDR
DDR0_CKE_2_
Y26 LP4_LP3
DDR
DDR0_DQ_24_
Y27 LP4
DDR
DDR0_DQ_26_
Y28 LP4
DDR
DDR1_DM_2_
AA1 LP4
DDR
DDR1_DQ_23_
AA2 LP4
DDR
DDR1_DQ_17_
AA3 LP4
DDR
DDR1_DQ_16_
AA4 LP4
DDR
AA5 VSSI GROUND

Proprietary and Confidential 31

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
P_DDR1_
AA7 VDDQ
POWER
AA8 AVDDH_PLL POWER
AA9 AVSS GROUND
AA10 AVDD POWER
AA11 VDDI POWER
P_GPIO2_
AA12 VDDO
POWER
AA13 VDDI POWER
Fo

AA14 VSSI GROUND

AA15 VDDI POWER
AA16 VSSI GROUND
rM

AA17 VDDI POWER

AA18 VSSI GROUND
AA19 VDDI POWER
AA20 VSSI GROUND
C ii
eg

P_DDR0_
AA21 VDDQ
POWER
on Be

AA22 AVDD POWER

v

AA24 VSSI GROUND

P_DDR0_
AA25 POWER
fid iji

VDDQ_CKE
DDR0_CALI-
AA26 BR_LP4
DDR
en ng

AA27 AVSS GROUND

P_DSI_
AA28 AVDD12
POWER
DDR1_DQ_18_
tia O

AB1 LP4
DDR
DDR1_DQ_31_
AB2 LP4
DDR
l nly

DDR1_DQ_28_
AB3 LP4
DDR
AB4 VSSI GROUND
DDR1_CKE_
AB5 LP4_LP3
DDR
AB7 CLK_AU I2S
AB8 I2S_1CH_CLK I2S 44 i2s_1ch_clk
AB9 DAC_COMP DAC
AB10 XI_RTC RTC
P_SENSOR_
AB11 VDDO
POWER
AB12 VSSI GROUND
P_USB0_
AB13 DVDD
POWER
P_USB0_
AB14 VDDH0
POWER
AB15 VSSI GROUND
P_ENET_
AB16 VDDO
POWER

Proprietary and Confidential 32

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
AB17 SMIO_33 SMIO 104 sdxc_wp
AB18 SMIO_29 SMIO 100 sdxc_d[1]
AB19 P_SD_VDDO POWER
AB20 VSSI GROUND
P_SDXC_
AB21 VDDO
POWER
AB22 AVDD POWER
AB24 AVDD18 POWER
AB25 SMIO_6 SMIO 77 nand_re norspi_dq[5]
Fo

AB26 AVSS GROUND

MIPI_DSI_
AB27 DN_3
VOUT
rM

MIPI_DSI_
AB28 DP_3
VOUT
DDR1_DQS_
AC1 BAR_3_LP4
DDR
C ii

DDR1_DQS_3_
eg

AC2 LP4
DDR
DDR1_DQ_24_
on Be

AC3 LP4
DDR
v

AC4 VSSI GROUND

AC5 XO_RTC RTC
fid iji

AC24 AVDDH_PLL POWER

AC25 SMIO_11 SMIO 82 nand_d[2] norspi_en[2]
AC26 SMIO_10 SMIO 81 nand_d[1] norspi_en[1]
en ng

MIPI_DSI_
AC27 DN_2
VOUT
MIPI_DSI_
tia O

AC28 DP_2
VOUT
DDR1_DQ_29_
AD1 LP4
DDR
l nly

DDR1_DQ_30_
AD2 LP4
DDR
DDR1_DQ_25_
AD3 LP4
DDR
AD4 PWC_WKUP1 PWC
AD5 PWC_WKUP PWC
AD6 IDC2CLK I2C 15 idc2clk pwm3
AD7 VSSI GROUND
AD8 PWC_PSEQ1 PWC
AD9 PWC_RSTINB PWC
AD10 GPIO_158 GPIO 158
AD11 GPIO_160 GPIO 160
AD12 SSI2EN0 SSI 30 ssi2_en0 pwm6 ssi0_en5
AD13 CLK_SI VIN
P_USB0_
AD14 VDD330
POWER
AD15 JTAG_TDO JTAG
AD16 ENET_TXD_2 Ethernet 57 enet_txd_2
AD17 ENET_MDIO Ethernet 65 enet_mdio enet_mdio ahb_mdio

Proprietary and Confidential 33

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
AD18 SMIO_38 SMIO 109 sd_reset
AD19 SMIO_24 SMIO 95 sd_d[6] norspi_en[6]
AD20 SMIO_9 SMIO 80 nand_d[0] norspi_en[0] snand_cs_n
AD21 SMIO_17 SMIO 88 nand_cle
AD22 SMIO_30 SMIO 101 sdxc_d[2]
AD23 SMIO_8 SMIO 79 nand_ale norspi_dq[7]
AD24 VSSI GROUND
AD25 SMIO_15 SMIO 86 nand_d[6] norspi_dq[2]
AD26 SMIO_0 SMIO 71 nand_ce norspi_clk snand_sck
Fo

MIPI_DSI_
AD27 DN_1 VOUT
MIPI_DSI_
AD28 DP_1 VOUT
rM

DDR1_DQ_26_
AE1 LP4 DDR
DDR1_DM_3_
AE2 LP4 DDR
C ii
eg

AE3 HDMI_REXT HDMI

on Be

DDR1_CKE_2_
AE4 LP4_LP3 DDR
v

AE5 CLK_AU_1CH I2S

AE6 IDC1DATA I2C
fid iji
14 idc1data
AE7 I2S_CLK I2S 48 i2s_clk
AE8 POR_L GLOBAL
en ng

idsp_vin_io- idsp_vin_io- idsp_pip_io-

AE9 SVSYNC1 VIN 117 pad_mas- pad_mas- pad_mas-
ter_vsync1 ter_vsync ter_vsync
idsp_vin_io- idsp_vin_io- idsp_pip_io-
tia O

AE10 SVSYNC3 VIN 119 pad_mas- pad_mas- pad_mas-

ter_vsync3 ter_vsync ter_vsync
AE11 SSI2MOSI SSI 28 ssi2_txd ssi0_en3
l nly

AE12 SSI0MISO SSI 24 ssi0_rxd

idsp_vin_io-
AE13 SHSYNC VIN 115 pad_mas-
ter_hsync
AE14 USB_REXT USB
AE15 JTAG_RST_L JTAG
AE16 ENET_TXEN Ethernet 54 enet_txen enet_txen
ENET_EXT_ enet_ext_ enet_ext_
AE17 OSC_CLK
Ethernet 69
osc_clk osc_clk
AE18 SMIO_5 SMIO 76 sd_wp
AE19 SMIO_3 SMIO 74 sd_cmd
AE20 SMIO_21 SMIO 92 sd_d[3]
AE21 SMIO_19 SMIO 90 sd_d[1]
AE22 SMIO_32 SMIO 103 sdxc_cd
AE23 SMIO_26 SMIO 97 sdxc_clk
AE24 WP SMIO 70 nand_wp
AE25 SMIO_13 SMIO 84 nand_d[4] norspi_dq[0] snand_si[0]
AE26 SMIO_12 SMIO 83 nand_d[3] norspi_en[3]

Proprietary and Confidential 34

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
MIPI_DSI_
AE27 DN_0 VOUT
MIPI_DSI_
AE28 DP_0 VOUT
DDR1_DQ_27_
AF1 LP4 DDR
P_DDR1_
AF2 VDDQ_CKE POWER
P_HDMI_
AF3 AVDD15_ESD POWER
Fo

DDR1_RE-
AF4 SET_LP4_LP3 DDR
AF5 CEC HDMI 112 hdmitx_cec
rM

AF6 GPIO_161 GPIO 161

AF7 GPIO_159 GPIO 159
ehci_app_
AF8 SSI3MISO SSI 33 ssi3_rxd idc0clk sc_c2
prt_ovcurr0
C ii
eg

idsp_vin_io- idsp_vin_io- idsp_pip_io-

AF9 SVSYNC4 VIN 120 pad_mas- pad_mas- pad_mas-
on Be

ter_vsync4 ter_vsync ter_vsync

ehci_prt_
v

AF10 SSI3MOSI SSI 32 ssi3_txd pwm8 ssi0_en7 sc_c1

pwr_0
AF11 SSI0MOSI SSI 23 ssi0_txd
fid iji

AF12 SSI0EN0 SSI 25 ssi0_en0

AF13 SENSOR_RST VIN 113 wdt_ext_rst_l
en ng

AF14 JTAG_TDI JTAG

AF15 ENET_TXD_1 Ethernet 56 enet_txd_1 enet_txd_1
AF16 ENET_RXDV Ethernet 63 enet_rxdv enet_rxdv
tia O

AF17 ENET_MDC Ethernet 64 enet_mdc enet_mdc ahb_mdc

ENET_CLK_
AF18 RX
Ethernet 67 enet_ref_clk enet_ref_rx

AF19 SMIO
l nly
SMIO_23 94 sd_d[5] norspi_en[5]
AF20 SMIO_2 SMIO 73 sd_clk
AF21 SMIO_18 SMIO 89 sd_d[0]
ehci_app_
AF22 SMIO_35 SMIO 106 sdxc_d[5]
prt_ovcurr1
AF23 SMIO_27 SMIO 98 sdxc_cmd
AF24 AVSS GROUND
AF25 SMIO_1 SMIO 72 nand_rb norspi_dq[4]
AF26 SMIO_16 SMIO 87 nand_d[7] norspi_dq[3] snand_si[3]
MIPI_DSI_DN_
AF27 CLK VOUT
MIPI_DSI_DP_
AF28 CLK VOUT
AG1 VSSI GROUND
DDR1_CALI-
AG2 BR_LP4 DDR
AG3 HDMI_CLK_M HDMI
AG4 HDMI_CH0_M HDMI
AG5 HDMI_CH1_M HDMI

Proprietary and Confidential 35

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
AG6 HDMI_CH2_M HDMI
AG7 DAC_VREFIN DAC
idsp_vin_io- idsp_vin_io- idsp_pip_io-
AG8 SVSYNC2 VIN 118 pad_mas- pad_mas- pad_mas-
ter_vsync2 ter_vsync ter_vsync
idsp_vin_io- idsp_vin_io- idsp_pip_io-
AG9 SVSYNC0 VIN 116 pad_mas- pad_mas- pad_mas-
ter_vsync0 ter_vsync ter_vsync
AG10 SSI3EN0 SSI 34 ssi3_en0 idc0data sc_c3
AG11 SSI2CLK SSI 27 ssi2_sclk ssi0_en2
Fo

AG12 SSI0EN1 SSI 26 ssi0_en1

AG13 CLK_SI_1 VIN 114
AG14 JTAG_TMS JTAG
rM

AG15 JTAG_CLK JTAG

AG16 ENET_RXD_2 Ethernet 61 enet_rxd_2
AG17 ENET_RXD_1 Ethernet 60 enet_rxd_1 enet_rxd_1
C ii

ENET_GTX_ enet_ext_ enet_ext_

eg

AG18 CLK Ethernet 69

osc_clk osc_clk
on Be

AG19 SMIO_4 SMIO 75 sd_cd

AG20 SMIO_20 SMIO 91 sd_d[2]
v

ehci_prt_
AG21 SMIO_36 SMIO 107 sdxc_d[6]
pwr_0
fid iji

ehci_prt_
AG22 SMIO_37 SMIO 108 sdxc_d[7]
pwr_1
AG23 SMIO_28 SMIO 99 sdxc_d[0]
en ng

P_NAND_
AG24 VDDO
POWER
AG25 VSSI GROUND
tia O

AG26 XOUT GLOBAL

AG27 AVSS GROUND
AG28 VSSI GROUND
l nly

AH1 VSSI GROUND

AH2 VSSI GROUND
AH3 HDMI_CLK_P HDMI
AH4 HDMI_CH0_P HDMI
AH5 HDMI_CH1_P HDMI
AH6 HDMI_CH2_P HDMI
AH7 DAC_RSET DAC
AH8 DAC_IO DAC
AH9 SSI2MISO SSI 29 ssi2_rxd pwm5 ssi0_en4
AH10 SSI3CLK SSI 31 ssi3_sclk pwm7 ssi0_en6 sc_c0
AH11 SSI0CLK SSI 22 ssi0_sclk
AH12 USB_DM USB
AH13 USB_DP USB
AH14 ENET_TXD_3 Ethernet 58 enet_txd_3
AH15 ENET_TXD_0 Ethernet 55 enet_txd_0 enet_txd_0
AH16 ENET_RXD_0 Ethernet 59 enet_rxd_0 enet_rxd_0
AH17 ENET_RXD_3 Ethernet 62 enet_rxd_3

Proprietary and Confidential 36

CV2S66 Datasheet - Preliminary

Multiplexed Functions
Loc. Pin Name Class
GPIO First Second Third Fourth Fifth
ENET_CLK_ enet_2nd_
AH18 TX
Ethernet 66
ref_clk
AH19 SMIO_25 SMIO 96 sd_d[7] norspi_en[7]
AH20 SMIO_22 SMIO 93 sd_d[4] norspi_en[4]
AH21 SMIO_39 SMIO 110 sdxc_reset
ehcI_app_
AH22 SMIO_34 SMIO 105 sdxc_d[4]
prt_ovcurr0
AH23 SMIO_31 SMIO 102 sdxc_
AH24 SMIO_7 SMIO 78 nand_we norspi_dq[6]
Fo

AH25 SMIO_14 SMIO 85 nand_d[5] norspi_dq[1] snand_si[1]

AH26 XIN GLOBAL
AH27 VSSI GROUND
rM

AH28 VSSI GROUND

Table 3-1. Pin List and Mapping Table for the CV2S66 Chip.
C ii
eg
on Be
v
fid iji
en ng
tia O
l nly

Proprietary and Confidential 37

CV2S66 Datasheet - Preliminary

3.2 Pin Tables

The pins for the CV2S66 chip are classified according to interface as follows:

• (Section 3.2.1) Pins: DRAM

• (Section 3.2.2) Pins: Sensor / Video Input
• (Section 3.2.3) Pins: Video Output
• (Section 3.2.4) Pins: MIPI DSI
• (Section 3.2.5) Pins: I2S Digital Audio
• (Section 3.2.6) Pins: Gigabit Ethernet Interface
Fo

• (Section 3.2.7) Pins: USB

• (Section 3.2.8) Pins: Smart Media Input/Output (SMIO)
rM

• (Section 3.2.9) Pins: SSI / SPI

• (Section 3.2.10) Pins: I2C / IDC
C ii

• (Section 3.2.11) Pins: UART

eg

• (Section 3.2.12) Pins: InfraRed Remote

on Be

• (Section 3.2.13) Pins: General Purpose Input/Output (GPIO)

v

• (Section 3.2.14) Pins: Analog to Digital Conversion

fid iji

• (Section 3.2.15) Pins: Power Management (PWC) and Real Time Clock (RTC)
• (Section 3.2.16) Pins: Timers
en ng

• (Section 3.2.17) Pins: Stepper

• (Section 3.2.18) Pins: Pulse Width Modulator (PWM)
tia O

• (Section 3.2.19) Pins: JTAG Control

• (Section 3.2.20) Pins: Global and Test
l nly

• (Section 3.2.21) Pins: Power, Ground and PLL

3.2.1 Pins: DRAM

Name Location Dir Type Description

K28, K27, K24, J24,
DDR0_CA_[0:5]_A_LP4
K25, L27
O LVSTL LPDDR4 command/address
M25, M27, M26,
DDR0_CA_[0:5]_B_LP4
N27, N26, P27
DDR0_CALIBR_LP4 AA26 I/O Analog Pull up to VDDQ via a 240-ohm resistor
DDR0_CK_A_LP4 L28
O LVSTL DRAM clock per channel
DDR0_CK_B_LP4 P28
DDR0_CK_A_BAR_LP4 M28 DDR0_CK_A/B_LP4 and DDR0_CK_A/B_
O LVSTL
DDR0_CK_B_BAR_LP4 N28 BAR_LP4 are differential clocks

Proprietary and Confidential 38

CV2S66 Datasheet - Preliminary

Name Location Dir Type Description

DDR0_CKE_LP4_LP3 U26
O LVSTL Clock enable
DDR0_CKE_2_LP4_LP3 Y26
DDR0_CS_A_LP4 L26
DDR0_CS_B_LP4 N25
O LVSTL Chip select
DDR0_CS_2_A_LP4 L25
DDR0_CS_2_B_LP4 R28

DDR0_DM_[0:3]_LP4 F25, H26, R26, W26 O LVSTL Data write mask (1 bit per 8 data bits)
Fo

F26, F24, E25, F27,

G25, G26, G27,
E26, H27, G24, H24,
rM

H25, K26, J26, J27,

DDR0_DQ_[0:31]_LP4 J25, T25, T26, U27, I/O LVSTL Bi-directional data bus
R27, P25, T27, R25,
P26, Y27, Y25, Y28,
C ii
eg

W27, V26, V25,

W25, V27
on Be

Data strobe (1 bit per 8 data bits)

v

DDR0_DQS_[0:3]_LP4 G28, H28, U28, W28 I/O LVSTL Output with write data, center aligned
Input with read data, edge aligned
fid iji

DDR0_DQS_BAR_[0:3]_ DDR0_DQS_[0:3]_LP4 and DDR0_DQS_

LP4
F28, J28, T28, V28 I/O LVSTL
BAR_[0:3]_LP4 are differential signals
DDR0_RESET_LP4_LP3 U25 O LVSTL Asynchronous reset
en ng

R2, T1, T2, P2, R3,

DDR1_CA_[0:5]_A_LP4
T3
O LVSTL LPDDR4 command/address
V4, U4, U2, U3, V3,
tia O

DDR1_CA_[0:5]_B_LP4
W3
DDR1_CALIBR_LP4 AG2 I/O Analog Pull up to VDDQ via a 240-ohm resistor
l nly

DDR1_CKE_LP4_LP3 AB5
O LVSTL Clock enable
DDR1_CKE_2_LP4_LP3 AE4
DDR1_CS_A_LP4 T4
DDR1_CS_B_LP4 W4
O LVSTL Chip select
DDR1_CS_2_A_LP4 R4
DDR1_CS_2_B_LP4 V2
DDR1_DM_[0:3]_LP4 J2, N2, AA1, AE2 O LVSTL Data write mask (1 bit per 8 data bits)
H3, J1, H2, J3, K1,
K2, J4, K3, M2,
N3, L3, L2, P4, M3,
P3, N1, AA4, AA3,
DDR1_DQ_[0:31]_LP4 I/O LVSTL Bi-directional data bus
AB1, Y3, Y2, W2,
Y4, AA2, AC3, AD3,
AE1, AF1, AB3, AD1,
AD2, AB2

Proprietary and Confidential 39

CV2S66 Datasheet - Preliminary

Name Location Dir Type Description

Data strobe (1 bit per 8 data bits)
DDR1_DQS_[0:3]_LP4 G1, L1, W1, AC2 I/O LVSTL Output with write data, center aligned
Input with read data, edge aligned
DDR1_DQS_BAR_[0:3]_ DDR1_DQS_[0:3]_LP4 and DDR1_DQS_
LP4
H1, M1, Y1, AC1 I/O LVSTL
BAR_[0:3]_LP4 are differential signals
DDR1_RESET_LP4_LP3 AF4 O LVSTL Asynchronous reset

DDR1_CK_A_BAR_LP4 R1
DDR0_CK_A/B_LP4 and DDR0_CK_A/B_
O LVSTL
BAR_LP4 are differential clocks
DDR1_CK_B_BAR_LP4 U1
Fo

DDR1_CK_A_LP4 P1
O LVSTL DRAM clock per channel
DDR1_CK_B_LP4 V1
rM

Table 3-2. DRAM Pins.

C ii
eg

3.2.2 Pins: Sensor / Video Input

on Be

Name Location Dir Type Description

v

CLK_SI AD13
fid iji

I/O CMOS Sensor master clock

CLK_SI_1 AG13
D15, D17, B16, B17, D18,
en ng

B19, D19, D20, B14, C14, SubLVDS/

Sensor data
SD_LVDS_N_[0:23] A13, D13, B23, B24, D24, I SLVS/ LVC-
Differential for sub-LVDS
B25, D25, D26, C27, D28, MOS /MIPI
Single ended for LVCMOS mode.
tia O

B22, B21, D22, B20

Termination resistor built in for sub-
C15, C17, A16, A17, C18,
LVDS / MIPI / SLVS mode.
A19, C19, C20, A14, D14, SubLVDS/
Both single and double data rates sup-
l nly

SD_LVDS_P_[0:23] B13, C13, A23, A24, C24, I SLVS/ LVC-

ported.
A25, C25, C26, B27, C28, MOS /MIPI
A22, A21, C22, A20
H-Sync / H-Valid with Master mode
SHSYNC AE13 O CMOS
configuration
SubLVDS/
SPCLK_LVDS_N_ C16, B18, B15, C23, B26, Sensor pixel clock
[0:5]
I SLVS/ LVC-
D21 Differential pairs for sub-LVDS and
MOS /MIPI
SLVS mode.
SubLVDS/
SPCLK_LVDS_P_ D16, A18, A15, D23, A26, SPCLK_LVDS_P_0 is used for single-
I SLVS/ LVC-
[0:5] C21 ended pixel clock with LVCMOS mode.
MOS /MIPI
AG9, AE9, AG8, AE10, V-Sync / V-Valid with Master mode con-
SVSYNC[0:4] O CMOS
AF9 figuration
Table 3-3. VIN Sensor Interface Pins.

Proprietary and Confidential 40

CV2S66 Datasheet - Preliminary

3.2.3 Pins: Video Output

This section covers Video Output interface pins for (Section 3.2.3.1) Digital Video output and (Section 3.2.3.2)
HDMI output.

3.2.3.1 VOUT Pins: Digital Video Output

Name Location Dir Type Description

VD0_CLK A11 I/O CMOS Video output clock
VD0_HSYNC C12 I/O CMOS Video output HSync signal
Fo

VD0_HVLD B11 I/O CMOS Video output data

C11, A12,
G17, E17,
E15, G16,
rM

E16, E18,
VD0_OUT_[0:15] I/O CMOS Video output data
G18, E19,
B12, G13,
G14, E13,
C ii
eg

E14, G15
VD0_VSYNC G19 I/O CMOS Video output VSync signal
on Be

VD_PWM E20 I/O CMOS VOUT pulse width modulation pin

v

Table 3-4. Digital Video Output Pins.

fid iji
en ng

3.2.3.2 VOUT Pins: HDMI Output

Name Location Dir Type Description

tia O

CEC AF5 I/O CMOS CEC control pin (3.3-V tolerance)

HDMI_CH0_M AG4
HDMI_CH0_P AH4
l nly

HDMI_CH1_M AG5
I/O Analog Differential TMDS data out (open drain)
HDMI_CH1_P AH5
HDMI_CH2_M AG6
HDMI_CH2_P AH6
HDMI_CLK_M AG3 I/O Analog
Differential TMDS clock (open drain)
HDMI_CLK_P AH3 I/O Analog
Reference resistor - 10 KOhms (1% tolerance)
HDMI_REXT AE3 I/O Analog
(Required even if HDMI port is unused)
HPD G4 I/O CMOS Hot plug detect (3.3-V tolerance)
IDC1CLK A9 I/O CMOS IDC second serial port clock for HDMI programming
IDC1DATA AE6 I/O CMOS IDC second serial port data for HDMI programming
P_HDMI_AVDD15_ Analog
ESD
AF3 S HDMI 1.8-V analog power (Electrostatic Discharge)
Power
P_HDMI_AVDD33_ ANALOG
ESD
V5 S HDMI 3.3-V analog power (Electrostatic Discharge)
POWER
Table 3-5. HDMI Output Pins.

Proprietary and Confidential 41

CV2S66 Datasheet - Preliminary

3.2.4 Pins: MIPI DSI

Name Location Dir Type Description

MIPI_DSI_DN_CLK AF27 I/O Analog DSI Clock
MIPI_DSI_DP_CLK AF28 I/O Analog DSI Clock
AE27, AD27, AC27,
MIPI_DSI_DN[0:3] I/O Analog DSI Data
AB27
AE28, AD28, AC28,
MIPI_DSI_DP[0:3] I/O Analog DSI Data
Fo

AB28
Table 3-6. MIPI DSI Pins.
rM

3.2.5 Pins: I2S Digital Audio

C ii
eg

Name Location Dir Type Description

CLK_AU AB7 O CMOS I2S audio master clock
on Be

CLK_AU_1CH AE5 O CMOS I2S audio master clock

v

I2S_CLK AE7 I/O CMOS I2S audio bit clock

B6 I CMOS I2S serial data in
fid iji
I2S_SI_0
I2S_SI_1 B7 I CMOS I2S serial data in
I2S_SO_0 E11 O CMOS I2S serial data out
en ng

I2S_SO_1 A8 O CMOS I2S serial data out

I2S_1CH_SO A5 O CMOS I2S serial data out
I2S_1CH_SI A6 O CMOS I2S serial data in
tia O

I2S_WS A7 I/O CMOS I2S word select

Table 3-7. I2S Controller Pins.
l nly

3.2.6 Pins: Gigabit Ethernet Interface

Name Location Dir Type Description

ENET_CLK_RX AF18 I/O CMOS Receive clock
ENET_CLK_TX AH18 I/O CMOS Transmit clock
ENET_EXT_OSC_CLK AE17 I/O CMOS Ethernet clock
ENET_GTX_CLK AG18 I/O CMOS Ethernet clock
ENET_MDC AF17 I/O CMOS RGMII clock
ENET_MDIO AD17 I/O CMOS RGMII data bus
ENET_RXD_0 AH16 I/O CMOS
ENET_RXD_1 AG17 I/O CMOS
Receive data
ENET_RXD_2 AG16 I/O CMOS
ENET_RXD_3 AH17 I/O CMOS
ENET_RXDV AF16 I/O CMOS Receive data valid

Proprietary and Confidential 42

CV2S66 Datasheet - Preliminary

Name Location Dir Type Description

ENET_TXD_0 AH15 I/O CMOS
ENET_TXD_1 AF15 I/O CMOS
Transmit data
ENET_TXD_2 AD16 I/O CMOS
ENET_TXD_3 AH14 I/O CMOS
ENET_TXEN AE16 I/O CMOS Transmit ready
Table 3-8. Gigabit Ethernet Pins.

3.2.7 Pins: USB

Fo

Name Location Dir Type Description

DETECT_VBUS G5 I/O CMOS USB slave bus detect
rM

P_USB0_DVDD AB13 S Power USB analog power supply

P_USB0_VDDH0 AB14 S Power USB analog power supply
P_USB0_VDD330 AD14 S Power USB analog power supply
C ii
eg

USB_DM AH12 I/O Analog Data

USB_DP AH13 I/O Analog Data
on Be

USB_REXT AE14 I/O Analog Reference resistor

v

Table 3-9. USB Interface Pins.

fid iji

3.2.8 Pins: Smart Media Input/Output (SMIO)

en ng

• The Smart Media Input/Output (SMIO) pins are CMOS type and programmable input/output.
tia O

• The pins are shared by controllers for NAND Flash (NAND) and SD / SDIO / SDHC / SDXC / MMC /
eMMC (SD).
l nly

• These pins use SMIO_[N] for the primary function name.

• The SMIO interface shares pins with General Purpose Input / Output (GPIO) in Section 3.2.13.
There also are GPIO pins that handle smart media functions (i.e., without sharing with SMIO pins).
These are listed in the SMIO tables below.

NAND SD
Name Loc. Description
Function Dir Function Dir
SMIO_0 AD26 NAND_CE O NAND chip enable
SMIO_1 AF25 NAND_RB I/O NAND ready / busy
SMIO_2 AF20 SD_CLK O SD0 Clock
SMIO_3 AE19 SD_CMD I/O SD0 command
SMIO_4 AG19 SD_CD I/O SD0 card detect
SMIO_5 AE18 SD_WP I/O SD0 write protect
SMIO_6 AB25 NAND_RE O NAND read enable
SMIO_7 AH24 NAND_WE O NAND write enable
SMIO_8 AD23 NAND_ALE O NAND address latch enable

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CV2S66 Datasheet - Preliminary

NAND SD
Name Loc. Description
Function Dir Function Dir
SMIO_9 AD20 NAND_D[0] I/O NAND data
SMIO_10 AC26 NAND_D[1] I/O NAND data
SMIO_11 AC25 NAND_D[2] I/O NAND data
SMIO_12 AE26 NAND_D[3] I/O NAND data
SMIO_13 AE25 NAND_D[4] I/O NAND data
SMIO_14 AH25 NAND_D[5] I/O NAND data
SMIO_15 AD25 NAND_D[6] I/O NAND data
SMIO_16 AF26 NAND_D[7] I/O NAND data
SMIO_17 AD21 NAND_CLE O NAND command latch enable
Fo

SMIO_18 AF21 SD_D[0] I/O SD0 data

SMIO_19 AE21 SD_D[1] I/O SD0 data
SMIO_20 AG20 SD_D[2] I/O SD0 data
rM

SMIO_21 AE20 SD_D[3] I/O SD0 data

SMIO_22 AH20 SD_D[4] I/O SD0 data
SMIO_23 AF19 SD_D[5] I/O SD0 data
C ii

SMIO_24 AD19 SD_D[6] I/O SD0 data

eg

SMIO_25 AH19 SD_D[7] I/O SD0 data

on Be

SMIO_26 AE23 SDXC_CLK O SD1 clock

SMIO_27 AF23 SDXC_CMD I/O SD1 command
v

SMIO_28 AG23 SDXC_D[0] I/O SD1 data

fid iji

SMIO_29 AB18 SDXC_D[1] I/O SD1 data

SMIO_30 AD22 SDXC_D[2] I/O SD1 data
SMIO_31 AH23 SDXC_D[3] I/O SD1 data
en ng

SMIO_32 AE22 SDXC_CD I/O SD1 card detect

SMIO_33 AB17 SDXC_WP I/O SD1 write protect
SMIO_34 AH22 SDXC_D[4] I/O SD1 data
tia O

SMIO_35 AF22 SDXC_D[5] I/O SD1 data

SMIO_36 AG21 SDXC_D[6] I/O SD1 data
SMIO_37 AG22 SDXC_D[7] I/O SD1 data
l nly

SMIO_38 AD18 SD_RESET I/O SD0 reset

SDXC_RE-
SMIO_39 AH21 SD1 reset
SET
SD0 high speed. Switch the SD
SD_HS_SEL E6 SD_HS I/O
power source from 1.8 V to 3.3 V.
SD1 high speed Switch the SDXC
SDXC_HS_SEL E5 SDXC_HS I/O
power source from 1.8 V to 3.3 V.
WP AE24 WP I/O NAND write protect
Table 3-10. Storage Media Interface Pins (SMIO) in NAND Flash and SD Modes.

Notes:
• The SD0 controller uses SD_X pins. The SD1 controller uses the SDXC_X pins.

• The host is required to provide pull-up resistors in SPI mode.

• SD1 requires pull-up resistors for SDXC_D[7:0].

• MMC4 card has open drain and push-pull modes. The open drain mode is not supported.

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CV2S66 Datasheet - Preliminary

3.2.9 Pins: SSI / SPI

Name Location Dir Pad Type Description 1

SSI0CLK AH11 I/O CMOS SSI0 master port bit clock
SSI0EN0 AF12 O CMOS SSI0 master port device enable
SSI0EN1 AG12 O CMOS SSI0 master port device enable
SSI0MISO AE12 I CMOS SSI0 master port data in
Fo

SSI0MOSI AF11 O CMOS SSI0 master port data out

SSI2CLK AG11 I/O CMOS SSI2 / NOR_SPI master bit clock
rM

SSI2EN0 AD12 O CMOS SSI2 / NOR_SPI master device enable

SSI2MISO AH9 I CMOS SSI2 / NOR_SPI master port data in
SSI2MOSI AE11 O CMOS SSI2 / NOR_SPI master port data out
C ii
eg

SSI3CLK AH10 I/O CMOS SSI3 master bit clock

on Be

SSI3EN0 AG10 O CMOS SSI3 master device enable

v

SSI3MISO AF8 I CMOS SSI3 master port data in

fid iji

SSI3MOSI AF10 O CMOS SSI3 master port data out

SSISCLK D3 I/O CMOS SSI slave bit clock
en ng

SSISEN D1 O CMOS SSI slave device enable

SSISMISO E7 I CMOS SSI slave port data in
SSISMOSI D5 O CMOS SSI slave port data out
tia O

Table 3-11. SSI / SPI Interface Pins.

l nly

Notes:
1. The SSI / SPI master clock speed and device-enable polarity are programmable.

3.2.10 Pins: I2C / IDC

Name Location Dir Pad Type Description

IDCCLK B9 I/O CMOS First IDC serial port - clock
IDCDATA E12 I/O CMOS First IDC serial port - data
Second IDC serial port - clock
IDC1CLK A9 I/O CMOS
Reserved for HDMI (Section 3.2.3.2)
Second IDC serial port - data
IDC1DATA AE6 I/O CMOS
Reserved for HDMI (Section 3.2.3.2)
Third IDC serial port - clock
IDC2CLK AD6 I/O CMOS
Reserved for HDMI (Section 3.2.3.2)

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CV2S66 Datasheet - Preliminary

Name Location Dir Pad Type Description

Third IDC serial port - data
IDC2DATA D11 I/O CMOS
Reserved for HDMI (Section 3.2.3.2)
IDC3CLK B8 I/O CMOS Fourth IDC serial port - clock
IDC3DATA C9 I/O CMOS Fourth IDC serial port - data
IDCSCLK A10 I/O CMOS IDC slave port - clock

IDCSDATA B10 I/O CMOS IDC slave port - data

Table 3-12. IDC Interface (I2C-Compatible) Pins.

Fo

3.2.11 Pins: UART

rM

Name Location Dir Pad Type Description

UART_APB_RX A4 I CMOS UART APB receive
C ii
eg

UART_APB_TX B5 O CMOS UART APB transmit

on Be

UART0_AHB_CTS_N D7 I/O CMOS UART Port 0 flow control

v

UART0_AHB_RTS_N C7 I/O CMOS UART Port 0 flow control

fid iji

UART0_AHB_RX C6 I CMOS UART Port 0 AHB receive

UART0_AHB_TX C5 O CMOS UART Port 0 AHB transmit
en ng

UART1_AHB_CTS_N C4 I/O CMOS UART Port 1 flow control

UART1_AHB_RTS_N E9 I/O CMOS UART Port 1 flow control
tia O

UART1_AHB_RX C2 I CMOS UART Port 1 AHB receive

UART1_AHB_TX C3 O CMOS UART Port 1 AHB transmit
l nly

UART2_AHB_CTS_N C1 I/O CMOS UART Port 2 flow control

UART2_AHB_RTS_N D8 I/O CMOS UART Port 2 flow control
UART2_AHB_RX B3 I CMOS UART Port 2 AHB receive
UART2_AHB_TX B2 O CMOS UART Port 2 AHB transmit
UART3_AHB_CTS_N D10 I/O CMOS UART Port 3 flow control
UART3_AHB_RTS_N D9 I/O CMOS UART Port 3 flow control
UART3_AHB_RX B4 I CMOS UART Port 3 AHB receive
UART3_AHB_TX A3 O CMOS UART Port 3 AHB transmit

Table 3-13. UART Interface Pins.

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CV2S66 Datasheet - Preliminary

3.2.12 Pins: InfraRed Remote

Name Location Dir Pad Type Description

IR_IN D12 I CMOS InfraRed input

Table 3-14. InfraRed Remote Interface Pins.

3.2.13 Pins: General Purpose Input/Output (GPIO)

The table below lists the General-Purpose (GPIO) pins on the chip. These pins have multi-function capability and
Fo

are CMOS type programmable input/output.

Multiplexed Function
rM

Pin Name GPIO

First Second Third Fourth Fifth
SC_A0 0 sc_a0 ssi1_sclk pwm3
SC_A1 1 sc_a1 ssi1_txd pwm4
C ii
eg

SC_A2 2 sc_a2 ssi1_rxd pwm5

SC_A3 3 sc_a3 ssi1_en0 pwm6
on Be

SC_B0 4 sc_b0 ssi1_en1 wdt_ext_rst_l

v

SC_B1 5 sc_b1 ssi1_en2 vin_strig0

SC_B2 6 sc_b2 ssi1_en3 vin_strig1
fid iji

SC_B3 7 sc_b3 enet_ptp_pps_o enet_ptp_pps_o

TIMER0 8 tm11_clk pwm7
idsp_pip_iopad_
en ng

TIMER1 9 tm12_clk
master_vsync
idsp_pip_iopad_
TIMER2 10 tm13_clk
master_hsync
tia O

IDCCLK 11 idc0clk
IDCDATA 12 idc0data
IDC1CLK 13 idc1clk
l nly

IDC1DATA 14 idc1data
IDC2CLK 15 idc2clk pwm3
IDC2DATA 16 idc2data pwm4
IDC3CLK 17 idc3clk pwm8
IDC3DATA 18 idc3data pwm9
IDCSCLK 19 idcsclk
IDCSDATA 20 idcsdata
IR_IN 21 ir_in wdt_ext_rst_l
SSI0CLK 22 ssi0_sclk
SSI0MOSI 23 ssi0_txd
SSI0MISO 24 ssi0_rxd
SSI0EN0 25 ssi0_en0
SSI0EN1 26 ssi0_en1
SSI2CLK 27 ssi2_sclk ssi0_en2
SSI2MOSI 28 ssi2_txd ssi0_en3
SSI2MISO 29 ssi2_rxd pwm5 ssi0_en4
SSI2EN0 30 ssi2_en0 pwm6 ssi0_en5
SSI3CLK 31 ssi3_sclk pwm7 ssi0_en6 sc_c0

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CV2S66 Datasheet - Preliminary

Multiplexed Function
Pin Name GPIO
First Second Third Fourth Fifth
SSI3MOSI 32 ssi3_txd pwm8 ssi0_en7 sc_c1 ehci_prt_pwr_0
ehci_app_prt_ov-
SSI3MISO 33 ssi3_rxd idc0clk sc_c2
curr0
SSI3EN0 34 ssi3_en0 idc0data sc_c3
ehci_app_prt_ov-
SSISCLK 35 ssis_sclk ssi1_sclk
curr0
ehci_app_prt_ov-
SSISMOSI 36 ssis_rxd ssi1_txd
curr1
SSISMISO 37 ssis_txd ssi1_rxd ehci_prt_pwr_0
Fo

SSISEN 38 ssis_en ssi1_en0 ehci_prt_pwr_1

UART_APB_RX 39 uart_apb_rx
UART_APB_TX 40 uart_apb_tx
PWM0 41 pwm0
rM

PWM1 42 pwm1
PWM2 43 pwm2 wdt_ext_rst_l
I2S_1CH_CLK 44 i2s_1ch_clk
C ii
eg

I2S_1CH_SI 45 i2s_1ch_si
I2S_1CH_SO 46 i2s_1ch_so
on Be

I2S_1CH_WS 47 i2s_1ch_ws
v

I2S_CLK 48 i2s_clk
I2S_SI_0 49 i2s_si_0
fid iji

I2S_SO_0 50 i2s_so_0
I2S_SI_1 51 i2s_si_1
I2S_SO_1 52 i2s_so_1
en ng

I2S_WS 53 i2s_ws
ENET_TXEN 54 enet_txen enet_txen
ENET_TXD_0 55 enet_txd_0 enet_txd_0
tia O

ENET_TXD_1 56 enet_txd_1 enet_txd_1

ENET_TXD_2 57 enet_txd_2
ENET_TXD_3 58 enet_txd_3
l nly

ENET_RXD_0 59 enet_rxd_0 enet_rxd_0

ENET_RXD_1 60 enet_rxd_1 enet_rxd_1
ENET_RXD_2 61 enet_rxd_2
ENET_RXD_3 62 enet_rxd_3
ENET_RXDV 63 enet_rxdv enet_rxdv
ENET_MDC 64 enet_mdc enet_mdc ahb_mdc
ENET_MDIO 65 enet_mdio enet_mdio ahb_mdio
ENET_CLK_TX 66 enet_2nd_ref_clk
ENET_CLK_RX 67 enet_ref_clk enet_clk_rx
ENET_GTX_CLK 68 enet_gtx_clk enet_gtx_clk
ENET_EXT_
OSC_CLK
69 enet_ext_osc_clk enet_ext_osc_clk

WP 70 nand_wp
SMIO_0 71 nand_ce norspi_clk snand_sck
SMIO_1 72 nand_rb norspi_dq[4]
SMIO_2 73 sd_clk
SMIO_3 74 sd_cmd

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CV2S66 Datasheet - Preliminary

Multiplexed Function
Pin Name GPIO
First Second Third Fourth Fifth
SMIO_4 75 sd_cd
SMIO_5 76 sd_wp
SMIO_6 77 nand_re norspi_dq[5]
SMIO_7 78 nand_we norspi_dq[6]
SMIO_8 79 nand_ale norspi_dq[7]
SMIO_9 80 nand_d[0] norspi_en[0] snand_cs_n
SMIO_10 81 nand_d[1] norspi_en[1]
SMIO_11 82 nand_d[2] norspi_en[2]
SMIO_12 83 nand_d[3] norspi_en[3]
Fo

SMIO_13 84 nand_d[4] norspi_dq[0] snand_si[0]

SMIO_14 85 nand_d[5] norspi_dq[1] snand_si[1]
SMIO_15 86 nand_d[6] norspi_dq[2] snand_si[2]
rM

SMIO_16 87 nand_d[7] norspi_dq[3] snand_si[3]

SMIO_17 88 nand_cle
SMIO_18 89 sd_d[0]
C ii

SMIO_19 90 sd_d[1]
eg

SMIO_20 91 sd_d[2]
on Be

SMIO_21 92 sd_d[3]
SMIO_22 93 sd_d[4] norspi_en[4]
v

SMIO_23 94 sd_d[5] norspi_en[5]

fid iji

SMIO_24 95 sd_d[6] norspi_en[6]

SMIO_25 96 sd_d[7] norspi_en[7]
SMIO_26 97 sdxc_clk
en ng

SMIO_27 98 sdxc_cmd
SMIO_28 99 sdxc_d[0]
SMIO_29 100 sdxc_d[1]
tia O

SMIO_30 101 sdxc_d[2]

SMIO_31 102 sdxc_d[3]
SMIO_32 103 sdxc_cd
l nly

SMIO_33 104 sdxc_wp

ehci_app_prt_ov-
SMIO_34 105 sdxc_d[4]
curr0
ehci_app_prt_ov-
SMIO_35 106 sdxc_d[5]
curr1
SMIO_36 107 sdxc_d[6] ehci_prt_pwr_0
SMIO_37 108 sdxc_d[7] ehci_prt_pwr_1
SMIO_38 109 sd_reset
SMIO_39 110 sdxc_reset
HPD 111 hdmitx_hpd
CEC 112 hdmitx_cec
idsp_vin_iopad_
SVSYNC0
master_vsync0
idsp_vin_iopad_
SHSYNC
master_hsync
SENSOR_RST 113 wdt_ext_rst_l
CLK_SI_1 114
idsp_vin_iopad_
SHSYNC 115
master_hsync

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CV2S66 Datasheet - Preliminary

Multiplexed Function
Pin Name GPIO
First Second Third Fourth Fifth
idsp_vin_iopad_ idsp_vin_iopad_ idsp_pip_iopad_
SVSYNC0 116
master_vsync0 master_vsync master_vsync
idsp_vin_iopad_ idsp_vin_iopad_ idsp_pip_iopad_
SVSYNC1 117
master_vsync1 master_vsync master_vsync
idsp_vin_iopad_ idsp_vin_iopad_ idsp_pip_iopad_
SVSYNC2 118
master_vsync2 master_vsync master_vsync
idsp_vin_iopad_ idsp_vin_iopad_ idsp_pip_iopad_
SVSYNC3 119
master_vsync3 master_vsync master_vsync
idsp_vin_iopad_ idsp_vin_iopad_ idsp_pip_iopad_
SVSYNC4 120
master_vsync4 master_vsync master_vsync
Fo

VD0_OUT_0 121 vd0_out[0]

VD0_OUT_1 122 vd0_out[1]
VD0_OUT_2 123 vd0_out[2]
rM

VD0_OUT_3 124 vd0_out[3]

VD0_OUT_4 125 vd0_out[4]
VD0_OUT_5 126 vd0_out[5]
VD0_OUT_6 127 vd0_out[6]
C ii
eg

VD0_OUT_7 128 vd0_out[7]

129
on Be
VD0_OUT_8 vd0_out[8]
VD0_OUT_9 130 vd0_out[9]
v

VD0_OUT_10 131 vd0_out[10]

fid iji

VD0_OUT_11 132 vd0_out[11]

VD0_OUT_12 133 vd0_out[12]
VD0_OUT_13 134 vd0_out[13]
en ng

VD0_OUT_14 135 vd0_out[14]

VD0_OUT_15 136 vd0_out[15]
VD0_CLK 137 vd0_clk
tia O

VD0_VSYNC 138 vd0_vsync

VD0_HSYNC 139 vd0_hsync
VD0_HVLD 140 vd0_hvld
l nly

VD_PWM 141 pwm0

UART0_AHB_RX 142 uart0_ahb_rx ssi1_sclk
UART0_AHB_TX 143 uart0_ahb_tx ssi1_txd
UART0_AHB_
CTS_N
144 uart0_ahb_cts_n ssi1_rxd
UART0_AHB_
RTS_N
145 uart0_ahb_rts_n ssi1_en0

UART1_AHB_RX 146 uart1_ahb_rx

UART1_AHB_TX 147 uart1_ahb_tx
UART1_AHB_
CTS_N
148 uart1_ahb_cts_n
UART1_AHB_
RTS_N
149 uart1_ahb_rts_n pwm11

UART2_AHB_RX 150 uart2_ahb_rx

UART2_AHB_TX 151 uart2_ahb_tx pwm10
UART2_AHB_
CTS_N
152 uart2_ahb_cts_n
UART2_AHB_
RTS_N
153 uart2_ahb_rts_n pwm11

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CV2S66 Datasheet - Preliminary

Multiplexed Function
Pin Name GPIO
First Second Third Fourth Fifth
UART3_AHB_RX 154 uart3_ahb_rx
UART3_AHB_TX 155 uart3_ahb_tx pwm10
UART3_AHB_
CTS_N
156 uart3_ahb_cts_n
UART3_AHB_
RTS_N
157 uart3_ahb_rts_n pwm9

GPIO_158 158
GPIO_159 159
GPIO_160 160
Fo

GPIO_161 161
SD_HS_SEL 162 sd_hs_sel
SDXC_HS_SEL 163 sdxc_hs_sel
rM

DEBOUNCE_
GPIO_0
164
DEBOUNCE_
GPIO_1
165
C ii
eg

Table 3-15. General Purpose Input / Output Pins.

on Be
v
fid iji

3.2.14 Pins: Analog to Digital Conversion

Name Location Dir Type Description

en ng

ADC_CH_[0:1] E27, E28 I Analog ADC analog input

Table 3-16. ADC Interface Pins.
tia O

3.2.15 Pins: Power Management (PWC) and Real Time Clock (RTC)
l nly

Name Location Dir Type Description

Power Up/Down control signals. PWC_PSEQ goes high
PWC_PSEQ1 AD8 O CMOS
when PWC_WKUP/PWC_WKUP1 goes high.
PWC reset input. Usually pulled up to PWC_PC_VDD
PWC_RSTINB AD9 I CMOS
through an RC circuit.
PWC_WKUP AD5 In the power-off state, a positive pulse just can trigger a
I CMOS
PWC_WKUP1 AD4 power-on sequence during a power-off state.
XI_RTC AB10 I XOSC RTC clock
XO_RTC AC5 O XOSC RTC clock output
Table 3-17. PWC and RTC Interface Pins.

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CV2S66 Datasheet - Preliminary

3.2.16 Pins: Timers

Name Location Dir Type Description

TIMER0 D1 I/O CMOS Interval Timer 0 external clock source
TIMER1 D6 I/O CMOS Interval Timer 1 external clock source
TIMER2 D4 I/O CMOS Interval Timer 2 external clock source
Table 3-18. Timer Pins.

Note: Frequency of the external clock source should be < 1/4 of the APB clock.
Fo

3.2.17 Pins: Stepper

rM

Name Location Dir Type Description

SC_A0 F3 I/O CMOS Stepper Controller A
C ii

Stepper Controller A /
eg

SC_A1 F5 I/O CMOS

Micro Stepper A
on Be

Stepper Controller A /
SC_A2 F4 I/O CMOS
Micro Stepper A
v

Stepper Controller A /
SC_A3 E1 I/O CMOS
fid iji

Micro Stepper A
SC_B0 E2 I/O CMOS Stepper Controller B
Stepper Controller B /
SC_B1 E8 I/O CMOS
en ng

Micro Stepper B
Stepper Controller B /
SC_B2 E4 I/O CMOS
Micro Stepper B
tia O

Stepper Controller B /
SC_B3 E3 I/O CMOS
Micro Stepper B
Table 3-19. Stepper / Microstepper Pins.
l nly

3.2.18 Pins: Pulse Width Modulator (PWM)

Name Location Dir Type Description

Pulse Width Modulator used to drive
VD_PWM E20 I/O CMOS
LCD panel Video Output
Pulse Width Modulator Output 0
PWM0 F1 I/O CMOS
Used for motor control
Pulse Width Modulator Output 1
PWM1 G2 I/O CMOS
Used for motor control
Pulse Width Modulator Output 2
PWM2 F2 I/O CMOS
Used for motor control
Table 3-20. PWM Pins.

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CV2S66 Datasheet - Preliminary

3.2.19 Pins: JTAG Control

Name Location Dir Pad Type Description

JTAG_CLK AG15 I CMOS Clock
JTAG_RST_L AE15 I CMOS Reset
JTAG_TDI AF14 I CMOS Data in
JTAG_TDO AD15 O CMOS Data out
JTAG_TMS AG14 I CMOS Test mode select
Table 3-21. JTAG Pins.
Fo

3.2.20 Pins: Global and Test

rM

Name Location Dir Type Description

POR_L AE8 I CMOS External reset pin (active low)
0 - Normal mode
TEST_MODE C10 I CMOS
1 - Test mode
C ii
eg

XIN AH26 I XOSC System clock (24-MHz crystal oscillator)

XOUT AG26 O XOSC System clock output
on Be

Table 3-22. Global and Test Pins.

v
fid iji

3.2.21 Pins: Power, Ground and PLL

en ng

Name Dir Type Description

tia O

AVSS G Analog Power Analog ground

HDMI 1.5-V analog power (Electrostatic
P_HDMI_AVDD15_ESD S Analog Power
Discharge)
l nly

HDMI 3.3-V analog power (Electrostatic

P_HDMI_AVDD33_ESD S Analog Power
Discharge)
P_DSI_AVDD12 S Power 1.2-V power for DSI
P_USB0_DVDD S Power USB analog power supply
P_USB0_VDDH0 S Power USB analog power supply
P_USB0_VDD330 S Power USB analog power supply
VDDI S Power Digital power supply
VSSI G Power Digital ground (24 width)
P_ENET_VDDO S Power Power for Ethernet
P_MIPI_AVDD18_IO S Power 1.8-V / 1.1-V MIPI I/O power
P_NAND_VDDO S Power NAND I/O power, 3.3 V / 1.8 V
OTP_VPP S Power OTP core power
P_PWC_AVDD18 S Power PWC RTC power
P_PWC_AVDD33 S Power PWC 3.3-V power
P_SD_VDDO S Power SD I/O power, 3.3 V / 1.8 V
P_SDXC_VDDO S Power SDXC I/O power, 3.3 V / 1.8 V
P_SENSOR_VDDO S Power Sensor I/O power, 3.3 V / 1.8 V
VDDP S IO Power IO predriver Power, 1.8V nominal

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CV2S66 Datasheet - Preliminary

Name Dir Type Description

AVDD S Analog Supply Analog power supply
AVDD18 S Analog Supply 1.8V Analog power supply
AVDD33 S Analog Supply 3.3V Analog power supply
P_GPIO1_VDDO S Power Power for GPIO
P_GPIO2_VDDO S Power Power for GPIO
P_DDR0_VDDQ S Power DDR Host 0 core power
P_DDR1_VDDQ S Power DDR Host 1 core power
P_DDR0_VDDQ_CKE S Power DDR Host core power

Table 3-23. Power, Ground and PLL Pins.

Fo
rM

C ii
eg
on Be
v
fid iji
en ng
tia O
l nly

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CV2S66 Datasheet - Preliminary

4. ELECTRICAL CHARACTERISTICS

4.1 Electrical: Overview

This chapter provides details on the electrical characteristics of the CV2S66 chip as follows:

• (Section 4.2) Electrical: Absolute Ratings

• (Section 4.3) Electrical: Recommended Operating Conditions
• (Section 4.4) Electrical: Video Signal Wave Forms and Timing
• (Section 4.5) Electrical: ENET AC Timing
Fo

• (Section 4.6) Electrical: SD Controller Timing

• (Section 4.7) Electrical: eMMC Boot Timing
rM

• (Section 4.8) Electrical: I2S Timing

• (Section 4.9) Electrical: SSI / SPI Timing
C ii

• (Section 4.10) Electrical: Flash AC Timing

eg

• (Section 4.11) Electrical: I2C Timing

on Be
v

4.2 Electrical: Absolute Ratings

fid iji

The following table gives absolute ratings for the nominal analog / digital voltages in Section 4.3.1.
en ng

Parameter Minimum Maximum

Analog supply voltage (3.0 V) -0.3 V 3.6 V
Digital supply voltage (3.0 V) -0.3 V 3.6 V
tia O

Analog supply voltage (1.8 V) -0.3 V 1.98 V

Digital supply voltage (1.8 V) -0.3 V 1.98 V
Analog supply voltage (0.75 V) -0.3 V 0.88 V
l nly

Digital supply voltage (0.75 V) -0.3 V 0.88 V

-0.3 V 3.6 V
Digital I/O range (V)
-0.3 V 1.98 V
-0.3 V 3.6 V
Analog I/O range (V)
-0.3 V 1.98 V
Operating temperature (case) (oC) -25 C to +85 C
Storage temperature (oC) -40 C to +150 C
Table 4-1. Absolute Ratings.

Note:
This Ambarella part will support a full range of operation at the case temperature range shown above, provided
that the customer PCB design, manufacturing processes, and power supply design are equivalent to those of the
Ambarella reference hardware design in terms of quality. It also is required that all other components used in the
customer’s system design meet this temperature range to guarantee proper system operation.

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CV2S66 Datasheet - Preliminary

4.3 Electrical: Recommended Operating Conditions

This section continues with recommended operating conditions for:

• (Section 4.3.1) Operating Conditions: Power Rails DC Characteristics
• (Section 4.3.2) Operating Conditions: Digital I/O
• (Section 4.3.3) Operating Conditions: DRAM I/O
• (Section 4.3.4) Operating Conditions: PWC and RTC Power Supply
• (Section 4.3.5) Operating Conditions: Video Sensor Input
• (Section 4.3.6) Operating Conditions: Video DAC
Fo

• (Section 4.3.7) Operating Conditions: ADC Electrical Specifications

• (Section 4.3.8) Operating Conditions: Crystal and Reference Clock Requirements
rM

4.3.1 Operating Conditions: Power Rails DC Characteristics

C ii
eg

Parameter Comments Minimum Typical Maximum Ripple

P_DSI_AVDD12 1.07 V 1.2 V 1.3 V 2%
on Be

P_MIPI_AVDD18_IO 1.7 V / 1.07 V 1.8 V / 1.2 V 1.9 V / 1.3 V 2%

v

P_HDMI_AVDD15ESD 1.4 V 1.5 V 1.6 V 2%

P_HDMI_AVDD33ESD 3.15 V 3.3 V 3.45 V 2%
fid iji

P_PWC_AVDD33 2.9 V 3.0 V 3.6 V 2%

P_PWC_AVDD18 0.7 V 1.8 V 1.98 V 2%
VDDI 0.73 V 0.75 V 0.78 V 2%
en ng

VDDP 1.7 V 1.8 V 1.9 V 2%

OTP_VPP 1.7 V 1.8 V 1.9 V 2%
AVDD 0.78 V 0.8 V 0.825 V 2%
tia O

AVDD18 1.7 V 1.8 V 1.9 V 2%

AVDDH_PLL 1.47 V 1.5 V 1.8 V 2%
2.85 V 3.0 V 3.6 V 2%
l nly
AVDD33
3.0-V mode 2.85 V 3.0 V 3.6 V 2%
P_SD_VDDO
1.8-V mode 1.7 V 1.8 V 1.9 V 2%
3.0-V mode 2.85 V 3.0 V 3.6 V 2%
P_SDXC_VDDO
1.8-V mode 1.7 V 1.8 V 1.9 V 2%
3.0-V mode 2.85 V 3.0 V 3.6 V 2%
P_NAND_VDDO
1.8-V mode 1.7 V 1.8 V 1.9 V 2%
3.0-V mode 2.85 V 3.0 V 3.6 V 2%
P_ENET_VDDO
1.8-V mode 1.7 V 1.8 V 1.9 V 2%
3.0-V mode 2.85 V 3.0 V 3.6 V 2%
P_GPIO1_VDDO
1.8-V mode 1.7 V 1.8 V 1.9 V 2%
3.0-V mode 2.85 V 3.0 V 3.6 V 2%
P_GPIO2_VDDO
1.8-V mode 1.7 V 1.8 V 1.9 V 2%
3.0-V mode 2.85 V 3.0 V 3.6 V 2%
P_SENSOR_VDDO
1.8-V mode 1.7 V 1.8 V 1.9 V 2%
DDR_DVDD_VDDQ 1.06 V 1.1 V 1.17 V 2%

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CV2S66 Datasheet - Preliminary

Parameter Comments Minimum Typical Maximum Ripple

LPDDR4 Mode 1.06 V 1.1 V 1.17 V 2%
DDR_DVDD_IO
LPDDR4x Mode 0.57 V 0.6 V 0.65 V 2%
Table 4-2. Power Rails DC Characteristics.

Note:
The electrical details provided in this chapter are preliminary estimates. Please contact an Ambarella representa-
tive for current electrical specifications.

4.3.2 Operating Conditions: Digital I/O

Fo

Parameter Comments Minimum Typical Maximum

VIL Input Low Voltage -0.3 V 0.3 * VDDO
rM

3.6 V
VIH Input High Voltage 0.7 * VDDO
(for 3.3 V-tolerant pins)
VOL Output Low Voltage 0.2 * VDDO
VOH Output High Voltage 0.8 * VDDO
C ii
eg

Table 4-3. Digital I/O Characteristics (Preliminary).

on Be
v
fid iji

4.3.3 Operating Conditions: DRAM I/O

en ng

4.3.3.1 DRAM: DC Supply Voltage Levels

Parameter Comments Minimum Typical Maximum

tia O

DDR_DVDD_VDDQ See Section 4.3.1

DDR_DVDD_IO See Section 4.3.1
l nly

Table 4-4. DRAM I/O Characteristics - DC Supply Voltage Levels (Preliminary).

4.3.3.2 DRAM: LVSTL I/O DC Specifications

Parameter Comments Minimum Typical Maximum

0.65 * DDR_
VIH DC input voltage high
DVDD_VDDIO
VIL DC input voltage low -0.2 V 0.25 * VDDIO
0.8 * DDR_
VOH DC output logic high
DVDD_VDDIO
0.2 * DDR_
VOL DC output logic low
DVDD_VDDIO
Table 4-5. DRAM I/O Characteristics - LVSTL I/O DC Specifications (Preliminary).

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CV2S66 Datasheet - Preliminary

4.3.4 Operating Conditions: PWC and RTC Power Supply

Parameter Comments Minimum Typical Maximum

P_PWC_AVDD18 RTC module supply 0.7 V 1.8 V 1.98 V
P_PWC_AVDD33 Power management supply 2.5 V 3.0 V 3.1 V
1.2 * PWC_
VIH For PWC_WKUP, PWC_RSTINB AVDD18
2.8 V
0.5 * PWC_
VIL For PWC_WKUP, PWC_RSTINB AVDD18
Fo

0.7 * PWC_
VOH PWC_PSEQ[1]
AVDD33
0.2 * PWC_
VOL PWC_PSEQ[1]
AVDD33
rM

VIH For XI_RTC 0.4V 0.2V

VIL For XI_RTC 0.2V
Table 4-6. PWC and RTC Supply.
C ii
eg
on Be
v

4.3.5 Operating Conditions: Video Sensor Input

fid iji

4.3.5.1 VIN: SLVS / LVCMOS I/O

en ng

Parameter Symbol Comment Min Typ. Max.

MIPI 1.07 V 1.2 V 1.3 V
Interface MIPI_AVDD18_IO
Supply Voltage LVCMOS 1.8 V 1.7 V 1.8 V 1.9 V
tia O

Digital VDD 0.73 V 0.75 V 0.78 V

LVCMOS 1.1 V 0.45 V
VIL
l nly

LVCMOS 1.8 V 0.6 V

Digital Input Voltage
LVCMOS 1.1 V 0.7 V
VIH
LVCMOS 1.8 V 1.2 V
VCM 0.2 V 1.4 V
Differential Input for SLVS
VDIFF 70 mV 400 mV
VCM 70 mV 330 mV
Differential Input for MIPI
VDIFF 70 mV 400 mV
Table 4-7. DC Characteristics: SLVS Interface.

4.3.5.2 VIN: MIPI LP Receiver DC Specification

Parameter Comments Minimum Typical Maximum

VIH Logic 1 input voltage 880 mV
Logic 0 input voltage, not in ULP
VIL 550 mV
state

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CV2S66 Datasheet - Preliminary

Parameter Comments Minimum Typical Maximum

VIL-ULP Logic 0 input voltage, ULP state 300 mV
VHYST Input hysteresis 25 mV
Table 4-8. MIPI LP Receiver DC Specification.

4.3.5.3 VIN: MIPI LP Receiver AC Specification

Description Minimum Typical Maximum

Fo

Input pulse rejection 300 V-ps

Minimum pulse width response 20 ns
Peak interference amplitude 200 mV
rM

Interference frequency 450 MHz

Table 4-9. MIPI LP Receiver AC Specification.
C ii
eg

4.3.6 Operating Conditions: Video DAC

on Be
v

Parameter Comments Minimum Typical Maximum

IO out current 34.6 mA
fid iji
IOFS
IOP Operating current 36 mA
V(IO) Out voltage full scale 1.17 V 1.28 V 1.43 V
en ng

Resolution DAC resolution 10 bits

DNL Differential non-linearity error ±2 LSB
INL Integral non-linearity error ±4 LSB
tia O

VREF Reference voltage 1.22 V

Table 4-10. Video DAC Electrical Specification.
l nly

4.3.7 Operating Conditions: ADC Electrical Specifications

4.3.7.1 ADC Electrical: DC Specification

Parameter Comments Minimum Typical Maximum

VDD Digital supply voltage 0.73 V 0.75 V 0.78 V
N Resolution 12 bits
INL INL ±1 LSB ±4 LSB
DNL DNL ±0.5 LSB ±2 LSB
Table 4-11. ADC DC Specification.

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CV2S66 Datasheet - Preliminary

4.3.7.2 ADC Electrical: AC Specification

Parameter Comments Minimum Typical Maximum

Fs Sampling rate 100 K 1 MS/s
FCLK Sampling clock 12 MHz
Signal-to-noise and distortion ratio
SNDR 54 dB 60 dB
(Fclk = 5 MHz and AIN = 50 KHz*)
Table 4-12. ADC AC Specification.

4.3.8 Operating Conditions: Crystal and Reference Clock Requirements

Fo

4.3.8.1 Crystal and Reference Clock Requirements: 24 MHz

rM

Description Minimum Typical Maximum

Nominal frequency N/A 24 MHz only N/A
C ii
eg

Frequency Tolerance + 30 PPM or better

Load Capacitance CL 10 pF
on Be

Maximum ESR 50 Ohm

v

Motional Capacitance 26 fF
Shunt Capacitance 7 pF
fid iji

Table 4-13. Jitter Specifications (24 MHz).

en ng

4.3.8.2 Crystal and Reference Clock Requirements: 32.768 KHz

tia O

Description Minimum Typical Maximum

Nominal frequency N/A 32.768 KHz N/A
l nly

Frequency Tolerance + 30 PPM or better

Load Capacitance CL 10 pF
Maximum ESR 70 KOhm
Motional Capacitance 3.4 fF
Shunt Capacitance 1 pF 2 pF
Table 4-14. Jitter Specifications (32.768 KHz).

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CV2S66 Datasheet - Preliminary

4.4 Electrical: Video Signal Wave Forms and Timing

4.4.1 Video Waveform: Video Input (VIN) Timing

SPCLK_LVDS_P/N[0/1/2]
tS tH

SD_LVDS_P/N[11:0] D0 D1 D2
Fo

1 UI

Figure 4-1. Video Input Timing.

rM

Parameter Setup (tS) Hold (tH) Comment

C ii
eg

Data:
SPCLK_LVDS_P / N[0/1/2] 75 ps 75 ps
on Be

SD_LVDS_P / N[11:0]
v

Table 4-15. SLVS / MIPI Video Input Timing Setup / Hold.

fid iji
en ng
tia O
l nly

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4.4.2 Video Output (VOUT) Timing

DSI_[DP/DN]CLK

DSI_DPCLK tWH tWL

- DSI_DNCLK tDOH

tDOS

DSI_[DP/DN][3:0] Bx B0 B1 B2 B3
Fo

DSI_DP[3:0]
rM

- DSI_DN[3:0]
tDOSQ tDOSQ
C ii
eg

80%
DSI_DPCLK - DSI_DNCLK
on Be
20%
v

DSI_DP[x] - DSI_DN[x] tDOLHT tDOHLT

fid iji

Figure 4-2. Video Output Timing.

en ng

Item Symbol Min. Typ. Max. Unit Comments

DO skew time
tia O

tDOSQ 150 ps Data rate 900 MHz DDR (1.8 Gbs)

(including jitter)
DO setup time tDOS 100 ps Data rate 900 MHz DDR (1.8 Gbs)
l nly

DO hold time tDOH 100 ps Data rate 900 MHz DDR (1.8 Gbs)
DO rise time tDOLHT 200 ps Simulated value with load capacitance (4 pF)
DO fall time tDOHLT 200 ps Simulated value with load capacitance (4 pF)
DCK pulse width Twh Twl 300 ps Including period jitter
Table 4-16. Video Output Timing Values: MIPI DSI.

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4.5 Electrical: ENET AC Timing

4.5.2.1 RGMII AC Timing

TXC (source of data) TXC with added internal delay

TholdT

TXD TXD[3:0] TXD[7:4]

Fo

TsetupT

TXCTL TXEN TXERR

rM

TholdR

TXC (at receiver)

TsetupR
C ii
eg

Figure 4-3. RGMII TX AC Timing

on Be
v
fid iji

RXC (source of data) RXC with added internal delay

TholdT
en ng

RXD RXD[3:0] RXD[7:4]

TsetupT
tia O

RXCTL RXDV RXERR

TholdR
l nly

RXC (at receiver)

TsetupR

Figure 4-4. RGMII RX AC Timing

Parameter Symbol Min Typ Max Unit

Clock cycle duration Tcyc 8 ns
Data to clock output setup (at Transmitter - integrated delay) TsetupT 1.2 2.0 ns
Clock to data output hold (at Transmitter - integrated delay) TsholdT 1.2 2.0 ns
Data to clock input setup (at Receiver - integrated delay) TsetupR 1.0 2.0 ns
Clock to data input hold (at Receiver - integrated delay) TholdR 1.0 2.0 ns
Rise / fall time (20% - 80%) Tr/Tf 0.75 ns
Table 4-17. RGMII AC Timing Parameters

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4.5.2.2 RMII AC Timing

t1 t2

REF_CLK

t4

TX_EN, TXD
t3
Fo

t6

CRS_DV, RXD
rM

t5

Figure 4-5. RMII AC Timing

C ii
eg
on Be
v

Parameter Symbol Min Typ Max Unit

fid iji

REF_CLK frequency 50 MHz

REF_CLK high pulse width t1 7 13 ns
en ng

REF_CLK low-pulse width t2 7 13 ns

TXEN, TXD[1:0] setup t3 4 ns
TXEN, TXD[1:0] hold t4 2 ns
tia O

CRS_DV, RXD[1:0] setup t5 4 ns

CRS_DV, RXD[1:0] hold t6 2 ns
l nly

Table 4-18. RMII AC Timing Parameters

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CV2S66 Datasheet - Preliminary

4.5.2.3 MDC/MDIO Timing

The period of Management Data Clock (MDC) is derived from gclk_core. Per the setting of cr register in MAC_R4_
RMII_address register of Ethernet controller, it can be in the range of 1.25 and 2.8 MHz, or even higher if neces-
sary.

t1 t2

MDC
Fo

t3

MDIO (to PHY)

rM

t4 t6

MDIO (from PHY)

C ii
eg

t5
on Be

Figure 4-6. MDC/MDIO Timing.

v
fid iji

Parameter Symbol Min Typ Max Unit

MDC pulse width high t1 40% 60% MDC period
en ng

MDC pulse width low t2 40% 60% MDC period

MDIO output hold time t3 0 ns
tia O

MDIO time to valid output t4 5 ns

MDIO input setup time t5 18 ns
l nly

MDIO input hold time t6 0 ns

Table 4-19. MDC / MDIO Timing Parameters.

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CV2S66 Datasheet - Preliminary

4.6 Electrical: SD Controller Timing

There are two voltages at which the SD card is operated:

• (Section 4.6.1) SD Controller Timing: 3.3 V

• (Section 4.6.2) SD Controller Timing: 1.8 V

4.6.1 SD Controller Timing: 3.3 V

Fo

tWL tWH
VDD
VOH
SD_CLK_OUT
rM

VOL

VSS
tTHL tTLH
C ii
eg

tIH
on Be

tISU
v

VDD
Host CMD Input VIH
VLD
fid iji
V
Host DAT Input IL

VSS
en ng

Figure 4-7. SD Host Input Timing.

tia O

tWL tWH
VDD
l nly
VOH
SD_CLK_OUT VOL

VSS
tTHL tTLH

tODLY (min)

tODLY (max)
VDD
Host CMD Output VOH

Host DAT Output

VLD
V OL

VSS

Figure 4-8. SD Host Output Timing.

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CV2S66 Datasheet - Preliminary

Parameter Symbol Min Max Unit Comment

Clock CLK: All values are referred to as min (VIH) and max (VIL)
Clock Frequency: Data Transfer Mode fPP 0 50 MHz CCARD ≤ 10 pF (1 Card)
Clock Frequency: Identification Mode fOD 0/100 400 kHz CCARD ≤ 10 pF (1 Card)
Clock Low Time tWL 7 ns CCARD ≤ 10 pF (1 Card)
Clock High Time tWH 7 ns CCARD ≤ 10 pF (1 Card)
Clock Rise Time tTLH 3 ns CCARD ≤ 10 pF (1 Card)
Clock Fall Time tTHL 3 ns CCARD ≤ 10 pF (1 Card)
Fo

Inputs CMD, DAT: Referenced to CLK

Input Set-Up Time tISU 5.83 ns CCARD ≤ 10 pF (1 Card)
rM

Input Hold Time tIH 1.5 ns CCARD ≤ 10 pF (1 Card)

Outputs CMD, DAT: Referenced to CLK at 50 MHz
Output Delay Time tODLY 8.85 12.16 ns CL ≤ 40 pF (1 Card)
C ii
eg

Table 4-20. SD Controller Timing Parameters.

on Be
v

Parameter Symbol Min Max Unit Comment

fid iji

Supply Voltage VDD 2.70 3.60 V

Output High Voltage VOH 0.75*VDD V
Output Low Voltage VOL - 0.125* VDD V
en ng

Input High Voltage VIH 0.625* VDD VDD +0.3 V

Input Low Voltage VIL VSS-0.3 0.25*VDD V
tia O

Power Up Time 250 ms From 0V to VDD(min)

Table 4-21. Threshold Level for High Voltage.
l nly

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CV2S66 Datasheet - Preliminary

4.6.2 SD Controller Timing: 1.8 V

The card input setup time and hold time are measured at VIL (max.) and VIH (min.). The timing parameter, Clock
Threshold (VCT), is used to indicate clock reference point and is defined as 0.975V.

Parameter Symbol Min Max Unit Comment

Clock CLK: All values are referred to as min (VIH) and max (VIL)
100 MHz (Max).
Clock Period tCLK 10 - ns Between rising edge.
Fo

VCT=0.975 V
0x2 *
Clock rising/failing time tCR, tCF - ns CCARD = 10 pF
tCLK
rM

Clock Duty - 30 70 %
Card Inputs CMD, DAT: Referenced to CLK
CCARD = 10 pF,
Input Set-Up Time tIS 3 - ns
C ii

VCT=0.975V
eg

CCARD = 5 pF,
Input Hold Time tIH 0.8 - ns
on Be

VCT=0.975V
Outputs CMD, DAT: Referenced to CLK at 50 MHz
v

Output Delay Time tODLY - 7.5 ns CL = 30 pF

fid iji

Output Hold Time tOHLD 1.5 - ns CL = 15 pF

Table 4-22. SD Controller Timing Parameters in SDR50 Mode.
en ng

Parameter Symbol Min Max Unit Comment

tia O

Supply Voltage VDD 2.70 3.60 V

Regular Voltage VDDIO 1.7 1.95 V Generated by VDD
l nly

Output High Voltage VOH 1.4 - V

Output Low Voltage VOL - 0.45 V
Input High Voltage VIH 1.27 2.00 V
Input Low Voltage VIL VSS-0.30 0.58 V
Table 4-23. Threshold Level for 1.8V Signaling.

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CV2S66 Datasheet - Preliminary

tCLK
VDDIO
VIH - - - -
SD_CLK_OUT -- -- -- -- V CT
VIL

VSS

tCR tCF tCR tCF

Figure 4-9. Clock Signal Timing.

Fo

VDDIO
rM

SD_CLK_IN
VCT
-
VSS
C ii
eg

tIH
on Be
v

tIS
VDDIO
fid iji

Host CMD Input VIH

Host DAT Input

VLD
V
en ng
IL

VSS
tia O

Figure 4-10. SD Host Input Timing.

l nly

tCLK
VDDIO

SD_CLK_OUT
VCT
- -V CT

VSS
tOHLD(min)
tODLY
(max)
VDDIO
Host CMD Output VOH

Host DAT Output

VLD
V OL

VSS

Figure 4-11. SD Host Output Timing.

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CV2S66 Datasheet - Preliminary

4.7 Electrical: eMMC Boot Timing

To successfully boot from eMMC, the eMMC device should return boot data with the following timing constraints.

Clock
tSRF
tISU tIHL

CMD / DAT DATA DATA

Fo
rM

Figure 4-12. eMMC Boot Timing Diagram.

C ii
eg

Parameter Symbol Minimum Maximum

Host CMD / DAT input timing
on Be

Input setup time tISU 5.83 ns

v

Input hold time tIHL 1.5 ns

fid iji

Signal rise time 3 ns

tSRF
Signal Fall Time 3 ns
en ng

Table 4-24. eMMC Boot Timing.

Note:
tia O

CMD / DAT input rise and fall time are measured by VIL (max) and VIH (min).
l nly

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4.8 Electrical: I2S Timing

4.8.1 I2S Master Timing

SCK
tSW

WS
Fo

tSD
rM

SD_o
tHOL tSET
C ii
eg

SD_i
on Be

Figure 4-13. Timing Diagram for I2S Master.

v
fid iji

Parameter Symbol Min Max Unit

en ng

Clock period T 50 - ns
Clock high to word select change tSW - 2 ns
Clock high to SD_o change tSD - 1 ns
tia O

SD_i setup time tSET 12 - ns

SD_i hold time tHOL 0 - ns
l nly

Table 4-25. Timing Parameters for I2S Master.

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CV2S66 Datasheet - Preliminary

4.8.2 I2S Slave Timing

SCK
tWST tWHL

WS
tSD
Fo

SD_o
rM

tDHL tDST

SD_i
C ii
eg

Figure 4-14. Timing Diagram for I2S Slave.

on Be
v
fid iji

Parameter Symbol Min Max Unit

Clock period T 50 - ns
Word select setup time tWST 5 - ns
en ng

Word select hold time tWHL 0 - ns

Clock high to SD_o change tSD - 13 ns
tia O

SD_i setup time tDST 3 - ns

SD_i hold time tDHL 0 - ns
l nly

Table 4-26. Timing Parameters for I2S Slave.

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4.9 Electrical: SSI / SPI Timing

4.9.1 SSI / SPI Master Timing Timing Diagram for SSI / SPI Master

tES T tSE

EN
Fo

SCK
tED tSD
rM

MOSI
C ii
eg

tHOL tSET
on Be

MISO
v

Figure 4-15. Timing Diagram for SSI / SPI Master.

fid iji
en ng

Parameter Symbol Min Max Unit

Clock period T 50 - ns
Slave enable low to clock high tES 0.5T-2 - ns
tia O

Clock low to slave enable high tSE 0.5T-2 - ns

MISO setup time tSET 8-rx_margin[1] - ns
l nly

MISO hold time tHOL 0 - ns

Slave enable to MOSI valid from high impedance tED - 0.5T+1 ns
Clock low to MOSI valid tSD - 2 ns
Table 4-27. Timing Parameters for SSI / SPI Master.

Note:
[1]
Configuration register at offset 0x00 bits [25:22]

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CV2S66 Datasheet - Preliminary

4.9.2 SSI / SPI Slave Timing

tES T tSE

EN

SCK
tHOL tSET
Fo

MOSI
tED tSD tEDZ
rM

MISO

Figure 4-16. Timing Diagram for SSI / SPI Slave.

C ii
eg
on Be

Parameter Symbol Min Max Unit

v

Clock period T 100 - ns

fid iji

Slave enable low to clock high tES 0.5T-3 - ns

Clock low to slave enable high tSE 0.5T-3 - ns
en ng

MOSI setup time tSET 0 - ns

MOSI hold time tHOL 3+3*T SSI_CLK
[1]
- ns
tia O

Slave enable to MISO valid from high impedance tED - 20+6*TSSI_CLK ns

Clock low to MISO valid tSD - 20+4*TSSI_CLK ns
Clock low to MISO high impedance tEDZ - 20+6*TSSI_CLK ns
l nly

Table 4-28. Timing Parameters for SSI / SPI Slave.

Note:
[1]
Internal SPI clock period

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CV2S66 Datasheet - Preliminary

4.10 Electrical: Flash AC Timing

The AC timing of flash controller is configurable and is one or multiple of gclk_core clock period. The following
table shows the list of configurable timing parameters.

Parameter Symbol Min Max Unit

CLE setup time tCLS (tcls_count+1) * T ± 0.37 ns
CLE hold time tCLH (tclh_count+1) * T ± 0.37 ns
ALE setup time tALS (tals_count+1) * T ± 0.26 ns
ALE hold time tALH (talh_count+1) * T ± 0.26 ns
Fo

CE# setup time tCS (tcs_count+1) * T ± 0.26 ns

CE# hold time tCH (tch_count+1) * T ± 0.26 ns
rM

Data setup time tDS (tds_count+1) * T ± 0.78 ns

Data hold time tDH (tdh_count+1) * T ± 0.78 ns
WE# pulse width tWP (twp_count+1)*T ns
C ii
eg

WE# high hold time tWH (twh_count+1)*T ns

WE# high to busy tWB (twb_count+1)*T ns
on Be

Ready to RE# low tRR (trr_count+1)*T ns

v

RE# pulse width tRP (trp_count+1)*T ns

fid iji

RE# high hold time tREH (treh_count+1)*T ns

CE# hold from RE# high tCEH (tceh_count+1) * T ± 0.24 ns
en ng

(Internal) read-data latching time from RE# low tRDELAY (trdelay_count+1)*T ns

CLE to RE# delay tCLR (tclr_count+1)*T± 0.30 ns
tia O

WE# high to RE# low tWHR (twhr_count+1)*T± 0.08 ns

Output Hi-Z to RE# low tIR (tir_count+1)*T± 0.53 ns
RE# high to output Hi-Z tRHZ (trhz_count+1)*T± 0.53 ns
l nly

ALE to RE# delay tAR (tar_count+1)*T± 0.17 ns

Table 4-29. Timing Parameters for FLASH.

Notes:
• T is the period of gclk_core

• t*_count is the control register setting of the flash controller

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CV2S66 Datasheet - Preliminary

4.10.1 Command Latch Cyle

CLE t CLS t CLH

CE t CS t CH

WE t WP
Fo

ALE t ALS t ALH

rM

t DS t DH

I/Ox Command
C ii
eg
on Be

Figure 4-17. Command Latch Cycle

v
fid iji

4.10.2 Address Latch Cycle

CLE t CLS
en ng
tia O
CE t CS
l nly

WE t WP t WH t WP t WH t WP t WH t WP t WH

t ALH t ALH t ALH t ALH t ALH

ALE t ALS t ALS t ALS t ALS t ALS

t DH t DH t DH t DH t DH

t DS t DS t DS t DS t DS

I/Ox Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3

Figure 4-18. Address Latch Cycle.

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CV2S66 Datasheet - Preliminary

4.10.3 Write Data Latch Cycle

CLE t CLH

CE t CH
Fo

ALE t ALS
rM

WE t WP t WH t WP t WP

tDS tDH tDS tDH tDS tDH

C ii
eg

I/Ox DIN 0 DIN 1 DIN final

on Be

Figure 4-19. Write Data Latch Cycle.

v
fid iji

4.10.4 Read Operation Timing

en ng
tCLR
CLE

tCEH
CE
tia O

WE
l nly

t AR
ALE

RE t RP t REH t RHZ

t WB t RR

I/Ox 0x0 CA-1 CA-2 RA-1 RA-2 RA-3 0x30 D(N) D(N+1) D(M)
Column Address Row Address
t RDELAY

R/ B BUSY

Figure 4-20. Read Operation Timing.

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CV2S66 Datasheet - Preliminary

4.10.5 Status Read Cycle

CLE tCLS tCLH tCLR

CE tCS tCH
Fo

WE t WP

tWHR
rM

RE
tDS tDH tIR tRHZ
C ii
eg

I/Ox 0x70 Status Output

on Be
v

Figure 4-21. Status Read Operation Timing.

fid iji
en ng
tia O
l nly

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CV2S66 Datasheet - Preliminary

4.11 Electrical: I2C Timing

tf tr tSU;DAT tBUF

SDA 70%
30%

tHD;STA tHD;DAT tVD;DAT tSU;STA tHD;STA tSP tSU;STO

tf tr tHIGH tVD;ACK

SCL 70%
30%

1/fSCL tLOW
Fo

START Five cycles ACK cycle START Seven ACK cycle STOP START
(Repeated) cycles

Figure 4-22. Definition of Timing for F/S-Mode Devices on the I2C-Bus.

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Standard Mode Fast Mode

Parameter Symbol Unit
Min Max Min Max
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SCL cycle time fSCL 0 100 0 400 KHz

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Set-up time START condition tSU;STA 4.7 0.6 us

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Hold time START condition tHD;STA 4.0 0.6 us

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Low period of SCL tLOW 4.7 1.3 us

High period of SCL tHIGH 4.0 0.6 us
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Data set-up time tSU;DAT 250 100 ns

Data hold time tHD;DAT 0 3.45 0 0.9 us
Rise time tRISE 1000 20 300 ns
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Fall time tFALL 300 20 300 ns

Set-up time STOP condition tSU;STO 4.0 0.6 us
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Bus free time between STOP and START condition tBUF 4.7 1.3 us
Capacitive load for each bus line Cb 400 400 pF
Table 4-30. I2C Characteristic of SDA and SCL for F/S-Mode.

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5. PACKAGE

The CV2S66 chip has a 716-pin HS-BGA package (19 mm x 19 mm).

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Figure 5-1. Top / Bottom View of the CV2S66 Package.

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CV2S66 Datasheet - Preliminary
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Figure 5-2. Side View of the CV2S66 Package.

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Dimensions
Description Symbol
Minimum Nominal Maximum
Total thickness A - - 2.57
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Stand off A1 0.27 - 0.37

Substrate thickness A2 0.67 REF
Heat slug thickness A3 1.3 REF
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Body size D 19 BSC

E 19 BSC
Ball diameter 0.4
Ball opening 0.35
Ball width b 0.38 - 0.48
Ball pitch e 0.65 BSC
Ball count n 716
Edge ball center to center D1 17.55 BSC
E1 17.55 BSC
Body center to contact ball SD 0.325 BSC
SE 0.325 BSC
Package edge tolerance aaa 0.1
Flatness bbb 0.25
Coplanarity ddd 0.12
Ball offset (package) eee 0.15
Ball offset (ball) fff 0.08
Table 5-1. Dimensions of the CV2S66 Package (millimeters).

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CV2S66 Datasheet - Preliminary

Notes:
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CV2S66 Datasheet - Preliminary

6. CONTACT AND ORDER INFORMATION

All chips in the CV2 series are lead-free, halogen-free and RoHS compliant.

CV2S66-A1-RH
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In M em or y of R achel H su

Ver si on
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C hi p par t N um ber
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For complete Ambarella contact information, please visit www.ambarella.com.

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CV2S66 Datasheet - Preliminary

7. ERRATA

7.1 Errata: I2S Interface (I2S_SI_1)

During the I2S interface qualification process, Ambarella found that the DMA mode does not work for the I2S_
SI_1 data port; therefore, users should avoid using this port.

For multi-channel audio application needs, Ambarella suggests users to enable a workaround through the DSP /
TDM mode whereby two or more channels of audio are muxed on one I2S input data line (using I2S_SI_0). The
other option is to use both the I2S controllers by streaming one stereo pair on I2S_SI_0 and the other on the other
on I2S_1CH_SI.
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7.2 Errata: I2C Interface

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Ambarella has observed a glitch with I2C (IDC) signals due to fast transition and long PCB traces, especially for
single load use cases. The glitch typically occurs when the signal transitions from low to high. A glitch on SCL
can be problematic, as it may appear as an incorrect clock.
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As a workaround, Ambarella suggests adding an RC filter on the SCL / SDA signal. An option is to add a 100
eg

ohm series resistor and a 100pF capacitor (single I2C device on the bus). Depending on the load, use a smaller
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capacitance value, especially if there are multiple devices on the same bus. This issue exists for both I2C master
and slave configurations.
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For more details or questions, please contact the Ambarella support team.

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CV2S66 Datasheet - Preliminary

8. IMPORTANT NOTICE

All Ambarella design specifications, datasheets, drawings, files, and other documents (together and separately,
“materials”) are provided on an “as is” basis, and Ambarella makes no warranties, expressed, implied, statutory, or
otherwise with respect to the materials, and expressly disclaims all implied warranties of noninfringement, mer-
chantability, and fitness for a particular purpose. The information contained herein is believed to be accurate and
reliable. However, Ambarella assumes no responsibility for the consequences of use of such information.

Ambarella reserves the right to correct, modify, enhance, improve, and otherwise change its products and ser-
vices at any time and to discontinue any product or service without notice. Customers should obtain the latest
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relevant information before placing orders and should verify that such information is current and complete.
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All products are sold subject to Ambarella’s terms and conditions of sale supplied at the time of order acknowledg-
ment. Ambarella warrants performance of its hardware products to the specifications applicable at the time of
sale in accordance with its standard warranty. Testing and other quality control techniques are used to the extent
Ambarella deems necessary to support this warranty.
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Ambarella assumes no liability for applications assistance or customer product design. Customers are responsible
for their products and applications using Ambarella components. To minimize the risks associated with customer
v

products and applications, customers should provide adequate design and operating safeguards and ensure their
products and applications meet applicable standards and safety requirements.
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Ambarella does not warrant or represent that any license, either expressed or implied, is granted under any patent
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right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or pro-
cess in which Ambarella products or services are used. Information published or provided by Ambarella regarding
third-party products or services does not constitute a license from Ambarella to use such products or services or
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a warranty or endorsement thereof. Use of such information may require a license from a third party under the
patents or other intellectual property of the third party, or a license from Ambarella under the patents or other intel-
lectual property of Ambarella.
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Reproduction of information from Ambarella documents is not permissible without prior approval from Ambarella.

Ambarella products are not authorized for use in safety-critical applications (such as life support) where a failure
of the product would reasonably be expected to cause severe personal injury or death, unless officers of the par-
ties have executed an agreement specifically governing such use. Customers acknowledge and agree that they
are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any
use of Ambarella products in such safety-critical applications, notwithstanding any applications-related information
or support that may be provided by Ambarella. Further, customers must fully indemnify Ambarella and its repre-
sentatives against any damages arising out of the use of Ambarella products in such safety-critical applications.

Ambarella products are neither designed nor intended for use in military/aerospace applications or environments.
Customers acknowledge and agree that any such use of Ambarella products is solely at the customer’s risk, and
they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

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CV2S66 Datasheet - Preliminary

9. REVISION HISTORY

Our goal is to provide our customers with the highest-quality documentation possible, and to continuously improve
our publications to ensure that your experience with Ambarella’s products is a positive one. If you have any ques-
tions or comments regarding this document, please contact the Technical Writing team at docs@ambarella.com.
Your feedback is welcomed and appreciated.

NOTE: Page/chapter numbers for previous drafts may differ from those in the current version.

Version Date Comments

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0.1 28 November 2018 Initial Version

0.2 30 November 2018 Updated Figure 1-1 Functional Block Diagram
0.3 3 December 2018 Updated Figure 1-1 Functional Block Diagram
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Updated Section 1.2 Feature List

0.4 4 December 2018
Updated Chapter 5 Package - Dimensions
Updated Section 3.2.1 Pins: DRAM for new description of DDR0_CALIBR_
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LP4
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Updated Table 4-3 Digital I/O Characteristics - changed VDD33 to VDDO

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Updated Stereo Disparity Engine in Section 1.2 Feature List

Updated Table 4-7 SLVS Interface - MIPI_AVDD18_IO
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Updated Table 4-2 Power Rails DC Characteristics - VDDP, OTP_VPP, P_

MIPI_AVDD18_IO, P_DSI_AVDD12
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Updated Key Features on title page for video processing performance

Updated Image / Video Processing, Video Encoding Engine, I2S, and Timer
information in Section 1.2 Feature List
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0.5 27 March 2019

Added a note to Section 3.2.16 Timer
Updated Table 3-2 DRAM Pins - DDR1_CALIBR_LP4 description
Updated the number of GPIO pins in Section 1.2
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Added differential input for MIPI to Table 4-7 SLVS Interface

Updated Table 4-14 SLVS / MIPI Video Input Timing Setup/Hold
Updated Table 4-6 PWC and RTC Supply - deleted PWC_PSEQ2, PWC_
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PSEQ3, and PWC_RSTOB

Updated ISP processing rates
Updated DDR clock rates
Updated fisheye encode performance
Updated Section 1.2 Feature List - deleted bullet point on ADC: TV2 and
updated multiple boot options
Updated Section 2.5 Audio Input and Output
Updated Section 2.9 Interfaces: SSI / SPI
0.6 19 May 2019 Removed MIPI virtual channel support
Updated Section 4.3.7.1 Crystal and Reference Clock Requirements
Added Section 4.5 ENET AC Timing
Added Chapter 7 Errata
Updated Figure 1-1 Functional Block Diagram
Updated DRAM to 1.56 GHz
0.7 10 July 2019
Updated encoding to 4Kp30 HEVC + 1080p30 HEVC + 4Kp4 MJPEG

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Version Date Comments

Updated Section 1.2 Feature list for HDR companding support
Updated Section 1.1 Introduction
Added timing diagrams to Chapter 4 Electrical Characteristics: SD controller,
eMMC boot, I2S, SSI/ /SPI, Flash AC, I2C
Removed micro-stepper section
Updated Interfaces chapter for Video Input, HDMI, USB, SSI / SPI, RTC
Updated Table 3-1 and Table 3-15 to remove CAN multiplexed functions
0.8 4 October 2019 Updated Table 3-7 I2S Controller Pins: I2S_SO_1 location
Updated Section 4.4.1 Video Waveform: Video Input (VIN) Timing
Updated Table 4-7 DC Characteristics: SLVS Interface
Added Table 4-10 Video DAC Electrical Specification
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Updated Table 4-11 ADC DC Specification for DNL max LSB

Updated Table 4-30 I2C Characteristic of SDA and SCL for max fast mode of
SCL cycle time
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Updated Chapter 6 Contact and Order Information for part number

0.9 15 October 2019 Updated DRAM to 1.296 GHz
Updated Table 4-7 DC Characteristic: SLVS Interface for SLVS Vcm max
value
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1.0 17 January 2020 Updated maximum AVDD value to 0.825 V

Updated Table 5-1 Dimensions of the Package
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Added notes to Section 2.3 Interfaces: VIN

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Updated Figure 5-1 Top / Bottom View of the CV2 Package

Updated Figure 5-2 Side View of the CV2 Package
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Updated Section 4.3.4 RTC Power Supply to reflect correct P_PWC_

AVDD18 max value
1.1 27 April 2020 Updated Table 4-27 Timing Parameters for SSI/SPI Master Clock Period -
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min Clock Period to 50 ns

Added Section 7.2 I2C errata
Updated timing diagrams and tables in Sections 4.4, 4.5, 4.6, 4.7, 4.8, 4.9,
4.10, and 4.11
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Table 9-1. Revision History.

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