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Sequential MOS Logic Circuits

The document discusses various sequential logic circuits including NOR based SR latch, CMOS NOR based SR latch, nMOS depletion load SR latch, NAND based SR latch, clocked NOR based SR latch, clocked NAND based JK latch, clocked AOI based JK latch, clocked NAND based JK latch, clocked D latch, master-slave D flip-flop, 2-phase clock, depletion load NMOS dynamic shift register, and enhancement load NMOS dynamic shift register.

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195 views

Sequential MOS Logic Circuits

The document discusses various sequential logic circuits including NOR based SR latch, CMOS NOR based SR latch, nMOS depletion load SR latch, NAND based SR latch, clocked NOR based SR latch, clocked NAND based JK latch, clocked AOI based JK latch, clocked NAND based JK latch, clocked D latch, master-slave D flip-flop, 2-phase clock, depletion load NMOS dynamic shift register, and enhancement load NMOS dynamic shift register.

Uploaded by

satyendumohapatra573
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 26

SEQUENTIAL MOS LOGIC

CIRCUITS
By
Pradyut Kumar Biswal
Dept. of Electronics and Telecommunication
IIIT Bhubaneswar
NOR based SR Latch circuit

2
CMOS NOR based SR Latch circuit

3
CMOS NOR based SR Latch circuit

M6 M8

M5 M7

Q Q

S M1 M2 M3 M4 R

4
CMOS NOR based SR Latch circuit
 S = VOH, R = VOL

M6 M8

M5 M7

Q Q

S M1 M2 M3 M4 R

Q = VOL Q = VOH

When, S= VOH, R= VOL, M1, M2, M7, M8 = ON


M3, M4, M5, M6 = OFF 5
CMOS NOR based SR Latch circuit
 S = VOL, R = VOH

M6 M8

M5 M7

Q Q

S M1 M2 M3 M4 R

Q = VOH Q = VOL

When, S= VOL, R= VOH, M1, M2, M7, M8 = OFF


M3, M4, M5, M6 = ON 6
CMOS NOR based SR Latch circuit
 S = VOL, R = VOL Assume initially, Q = VOH

M6 M8

M5 M7

Q Q

S M1 M2 M3 M4 R

Q = VOL Q = VOH

When, S= VOL, R= VOL, and Q = VOH,


7
Then, M2, M6, M7, M8 = ON, M1, M3, M4, M5 = OFF
CMOS NOR based SR Latch circuit
 S = VOL, R = VOL Assume initially, Q = VOL

M6 M8

M5 M7

Q Q

S M1 M2 M3 M4 R

Q = VOH Q = VOL

When, S= VOL, R= VOL, and Q = VOL,


8
Then, M3, M5, M6, M8 = ON, M1, M2, M4, M7 = OFF
CMOS NOR based SR Latch
Transient Analysis:

M6 M8

M5 M7

Q Q

S M1 M2 M3 M4 R

CQ CQ

9
CMOS NOR based SR Latch circuit
Transient Analysis:

Assuming that the latch is initially reset and that a set operation is being
performed by applying S = "1" and R = "0," the rise time associated
with node Q is: 10
nMOS depletion load SR Latch circuit

Based on NOR gates

11
NAND Based SR-Latch circuit

12
NAND Based SR-Latch circuit

(CMOS circuit) (nMOS depletion load circuit)

13
Clocked NOR based SR Latch

14
Clocked NAND based SR Latch

15
Clocked AOI based JK Latch

16
Clocked AOI based JK Latch

17
Clocked NAND based JK Latch

18
Clocked D-Latch circuit

19
Clocked D-Latch circuit

20
Master-slave D flip-flop circuit

Negative edge triggered


21
2-PHASE CLOCK

22
DEPLETION LOAD NMOS DYNAMIC SHIFT
REGISTER

23
ENHANCEMENT LOAD NMOS DYNAMIC
SHIFT REGISTER (RATIOED LOGIC)

24
ENHANCEMENT LOAD NMOS DYNAMIC
SHIFT REGISTER (RATIOLESS LOGIC)

25
THANKS

26

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