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A 17 GHz programmable frequency divider for space applications in a 130 nm

SiGe BiCMOS technology

Conference Paper · October 2015

DOI: 10.1109/BCTM.2015.7340548

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 A 17 GHz Programmable Frequency Divider
for Space Applications in a 130 nm
SiGe BiCMOS Technology

Frank Herzel , Johannes Borngräber , Arzu Ergintav , Maciej Kucharski , and Dietmar Kissinger
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
Technische Universität Berlin, Einsteinufer 17, 10587 Berlin, Germany
Email: herzel@ihp-microelectronics.com

Abstract—A programmable frequency divider for fractional-N with a lower phase noise, if high-performance VCOs are
frequency synthesizers is presented. The input frequency range employed. By using such a PLL produced in a 0.25 m SiGe
is from DC to 17 GHz for divider ratios from 16 to 255. We show BiCMOS technology, an integrated phase error below 0.7
by analysis and time-domain simulations that the quantization was reported in fractional-N operation for an output frequency
noise folding in a fractional-N PLL can be reduced tremendously, of 9.8001 GHz [3]. An advanced fractional PLL module for
if a prescaler between VCO and programmable divider can be
avoided by using this high-speed divider. The programmable
S-band to Ka-band applications was presented in [4]. Using
divider was manufactured in a 130 nm SiGe BiCMOS technology. external VCOs, frequencies from 2 to 18 GHz can be generated
Robust operation is obtained from a supply voltage VCC=2.3- with that module. The integrated PLL circuit used in [4]
3.9 V. The measured divider phase noise floor for a 100 MHz contains a fractional-N divider and a phase-frequency detector
output signal is as low as -156 dBc/Hz. The chip occupies 1.7 mm (PFD). The programmable divider is preceded by a DTC due
including bondpads and draws 154 mA from a 2.3 V supply. to speed limitations of the 250 nm BiCMOS process used. As
a result, the in-band fractional spurs are at a level of -55 dBc
I. I NTRODUCTION after bias optimization. Further reduction of the spur level is
desirable for a flexible PLL building block.
Current telecommunication satellite payloads use fixed
transmit and receive frequencies during the lifetime of the A 57 GHz programmable frequency divider for fractional-
satellite. In future systems, however, changes of orbit loca- N frequency synthesizers was presented in [5]. Besides careful
tions and new emerging applications will require flexible fre- design and good technology, the high speed was achieved by
quency synthesizers. Fractional-N phase-locked loops (PLLs) merging logic gates with flip-flops. This is a known technique
can derive flexible output frequencies with an extremely high used to implement logic functionality in between flip-flops
resolution from a crystal reference [1]. They even allow to with minimum increase in propagation delay. The implementa-
compensate crystal frequency shifts due to aging by adjusting tion in [5] was realized by stacking up to five transistors. As a
the feedback divider ratio in the PLL. Programmable frequency result, low-voltage operation is difficult to achieve. Moreover,
dividers are key components of fractional-N PLLs, where the the signal swing is reduced by the transistor stacking, which
spectral purity of the signal is crucial. For downconverters raises the phase noise contribution of the divider.
in the Ka-band (20/30 GHz) the local oscillator frequency is
typically in the range of 8-12 GHz. This frequency range is This paper presents a programmable frequency divider
also relevant for X-band radar. avoiding stacking of more than three transistors. As a result,
low-voltage, low-noise operation is combined with sufficient
Silicon-Germanium heterojunction bipolar transistors speed for most space applications.
(SiGe HBTs) are of high interest for space applications. This
device technology is inherently radiation-hard with respect
to gamma rays, neutrons and protons [2]. A fully integrated II. P HASE N OISE I SSUES
8-12 GHz fractional-N PLL for space applications in a SiGe
PLL phase noise is affected by the divider in two different
HBT technology has been reported in [1]. Manufactured in a
ways. First, the finite slope of the differential signals at the zero
0.25 m SiGe-BiCMOS technology a typical in-band phase
crossings makes the divider phase susceptible to noise. This
noise level of -100 dBc/Hz has been achieved in integer-N
effect can be minimized by using a large current [6]. A second
operation, but in fractional-N operation the noise floor was
effect of the frequency divider on PLL noise may become
about 10 dB higher. This large difference was partly due
much more important in a fractional-N PLL. It is related to
to the insertion of a divide-by-two circuit (DTC) between
the quantization noise of the sigma-delta modulator (SDM)
the 8-12 GHz voltage-controlled oscillator (VCO) and the
which is folded down to low frequencies due to the nonlinear
programmable divider. As demonstrated in Section II, this
input-output characteristic of the PD [7]. As shown in [8], a
may increase the in-band phase noise by up to 12 dB.
DC offset current at the charge pump output may significantly
A programmable divider can be used together with a reduce the in-band phase noise in a fractional-N PLL. This is
phase detector (PD) as a stand-alone module in conjunction due to the fact that in this case the PD bias point is shifted
with an external VCO. This allows a more flexible solution to a more linear region. Then, the PD characteristic can be
approximated by a second order polynomial [9]

(1)

where is the output current, is the linear PD gain, is

the deviation of the phase error from the average value , and
is the normalized curvature of the PD
input-output characteristic at the bias point. With these
assumptions, the noise current power spectral density (PSD)
reads for Gaussian noise [9]

(2)

where is the standard deviation of the PD input phase error

and is the sampling frequency at the PD input. Note that the
PSD is defined as a two-sided quantity to be compatible with
the convention for the phase noise spectrum. Transforming
to the PD input and from there to the PLL output we obtain
from (2) the phase noise contribution related to PD nonlinearity Fig. 1. Phase noise contribution due to the phase detector nonlinearity with
and without DTC in the feedback divider.
given by
(3)

where is the closed-loop PLL transfer function from the

input to the output. The in-band phase-noise plateau due to
quantization noise folding is given by

(4)

where is the average PLL feedback divider ratio including

the fixed-frequency prescaler, if used.
If a DTC needs to be included for divider speed limitations
as in [1] and [4], the relative change of the divider ratios and
the phase excursions are doubled. From (3) we conclude that
the inclusion of a DTC would raise this noise contribution
( ) by 12 dB. In order to verify (3) and the predicted
effect, we performed a transient MATLAB simulation with Fig. 2. Block diagram of the divider circuit.
and without DTC in the PLL feedback divider. In this simu-
lation, a 3rd order, single-loop, feed-forward type SDM was
used in conjunction with a second-order PD transfer function 10.0001 GHz. As evident from Fig. 1, the inclusion of a
according to (1). With these assumptions, the PLL output phase DTC in the divider chain halves , since is halved from
was calculated in the time domain for a long SDM sequence. 0.001 to 0.0005. Moreover, the DTC raises the in-band spur
Subsequently, the phase noise spectrum was obtained by fast level by approximately 12 dB due to the doubled value of .
Fourier transformation with a resolution of 1 Hz. The numeri-
cal results are plotted in Fig. 1 for the two cases together with III. DIVIDER D ESIGN
the analytical results according to (3). Obviously, the time-
domain simulations give similar results as the analysis, despite Fig. 2 shows a block diagram of the divider. It is based on
the fact that the assumption of Gaussian phase noise in the a modular programmable divider concept presented in [11]. In
derivation of (3) is not fulfilled in reality. More importantly, our case, the divider is composed of a cascade of seven divide-
we conclude from Fig. 1 that this phase noise contribution by-2/3 circuits. The output is taken after the fourth stage.
is indeed reduced by 12 dB, if the DTC is omitted in the In order to reduce timing jitter, the output is re-timed in a
feedback divider of the PLL. This gives us reason to hope synchronization flip-flop using the output of the second stage.
that the 10 dB difference between fractional-N and integer-N The ECL output signal is converted to a CMOS signal toggling
operation in [1] will be reduced tremendously, if a 130 nm between 0V and VCC, where high-voltage MOSFETs with a
technology is used allowing higher divider speeds. The largest thick gate oxide are used. Fig. 3 shows the schematic of the
fractional spurs occur at the frequency offset , dual-modulus divider. It is composed of two master-slave D-
where is the fractional part of the programmable divider flip-flops and two AND gates. Depending on the value of the
ratio [10]. The most critical cases with respect to spur per- differential mode control (MC) signal, the incoming signal CK
formance are near-integer divider ratios where or is divided by 2 or 3, respectively. Fig. 4 shows the schematic
. As an illustration, we consider a fractional-N PLL with of the flip-flop. This traditional topology avoids stacking of
an input frequency 100 MHz and an output frequency more than three transistors. It is not optimized for the highest
 ဆဇ programmable
divider

Fig. 3. Schematic of the divide-by-2/3 circuit.

Fig. 5. Chip photograph.

D Q D Q
in out 20
D Q D Q

CK

Minimum Input Power (dBm)

10
(a) N=100
VCC N=98
N=127
0

VOUT
-10
D

-20
CK 0 5 10 15
Input Frequency (GHz)

Fig. 6. Measured divider input sensitivity for divider ratios of N=100, 98,
and 127.
(b)

Fig. 4. Schematic of the D-flip-flop. (a) General structure using two latches;
(b) implementation of each latch. of VCC=2.5 V. This sensitivity corresponds to a single-ended
excitation and includes the cable losses. At low frequencies
the sensitivity is limited by the integrated metal-insulator-
possible speed, but for robustness with respect to voltage vari- metal (MIM) capacitances in the signal path. By using DC
ations and for a low noise. Therefore, we used relatively large coupling at the input, arbitrarily slow clock signals can be
transistor currents. Reduction of power consumption would divided, provided that the slope of the clock edges is large
be possible at the expense of a higher phase noise reflecting enough. Fig. 7 shows the phase noise spectrum at the CMOS
the universal power-noise trade-off observed in many analog output for a divider ratio of N=36. The output frequency is
circuits [12]. The circuit was designed and manufactured in limited by the speed of the high-voltage CMOS output buffer.
a 130 nm SiGe BiCMOS technology [13]. This technology
features five thin and two thick aluminum layers, where the
top layer used for inductors has a thickness of 3 m. For high- -100
speed tasks MOSFETs with thin gate oxide are available, and
for high-voltage purposes MOSFETs with a thick gate oxide -110 fin=10.188GHz
can be used. Fig. 5 shows a chip photograph. fin=7.2GHz
Phase Noise [dBc/Hz]

-120
fin=3.6GHz
IV. M EASUREMENT R ESULTS -130

The programmable divider is operated from a supply volt- -140

age VCC. A second supply VDD=1.2 V is used for program- fout=283MHz
ming the divider ratio using thin-gate-oxide MOSFETs. The -150 fout=200MHz
on-wafer measurements were performed using a single-ended fout=100MHz
sinusoidal input with the second input connected to ground. -160
The circuit is functional for supply voltages VCC from 2.3 V 103 104 105 106 107
1000 10000 100000 1000000 10000000

to 3.9 V. The divider draws 154 mA from a 2.3 V supply and Frequency Offset [Hz]
occupies 1.6 mm chip area including bondpads. Fig. 6 shows Fig. 7. Phase noise spectrum of divider input and divider output for three
the resulting divider input sensitivity for a supply voltage different input frequencies.
View publication stats

TABLE I. M ULTI -M ODULUS F REQUENCY D IVIDER P ERFORMANCE

∗
Reference Division Maximum input Voltage supply Current Phase noise floor Normalized phase noise floor Technology
ratios frequency consumption T m ax

[1] 12-511 8 GHz 2.5 V 190 mA -154.5 dBc/Hz -144 dBc/Hz 250 nm SiGe BiCMOS
(30 MHz output) 75 GHz / 95 GHz

[5] 12-259 57 GHz 3.3 V 91 mA N/A N/A SiGe bipolar

170 GHz / 250 GHz

[14] 64-127 44 GHz 3V 64 mA -142 dBc/Hz -147 dBc/Hz 130 nm SiGe BiCMOS
(177 MHz output) 240 GHz / 330 GHz

[15] 32-1048575 7 GHz 3V 104 mA -160 dBc/Hz -154 dBc/Hz SiGe BiCMOS
(50 MHz output) N/A / N/A

This work 16-255 17 GHz 2.3 V 154 mA -156 dBc/Hz -156 dBc/Hz 130 nm SiGe BiCMOS
(100 MHz output) 240 GHz / 330 GHz
∗
normalized to a 100 MHz output frequency.

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