Analysis and Design of Digital Circuits

With HDL(22EC34)
Introduction to Verilog & Preliminary Concept

Suresh C
Assistant Professor
EEE Dept,
RVCE

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Outline
◼ Course Outline
◼ Recommended Books
◼ Prerequisites of the subject
◼ Module 1: Overview of Digital Design with
Verilog HDL

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 Unit-1 Syllabus
Design Methodology-An Introduction L Verilog History, System
representation, Number representation and Verilog ports. Verilog Data
Types: Net, Register and Constant .
Verilog Operators and primitives, Logical, Arithmetic, Bitwise,
Reduction, Relational, Concatenation and Conditional.
Verilog Primitives. Logic Simulation, Design Verification, and
Test Methodology: Four-Value Logic and Signal Resolution in Verilog
Testing methodology .
Test Methodology Signal Generators for Test benches.Event-Driven
Simulation, Sized Numbers,
Introduction to Modeling Styles: Dataflow modeling, Behavioral
modelling, Structural modelling.

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◼ Text Book:
◼ 1,Samir Palnitkar, “Verilog HDL: A Guide to Digital
Design and Synthesis”, Pearson Education, Second
Edition.
◼ 2. Digital Logic and Computer Design, M. Morris Mano, Pearson
Education Inc., 13thImpression, 2011, ISBN: 978-81-7758-409-7.

◼ 3. Fundamentals of Logic Design, Charles H. Roth (Jr.), West

publications, 4th Edition,1992, ISBN13: 978-0-314-92218-2.

◼ 4. Digital Fundamentals, Thomas Floyd, 11th Edition, Pearson

Education India,ISBN13: 978-1-292- 07598-3, 2015.

◼ 5. Digital Principle and Design, Donald D. Givone,Mc Graw-Hill,

ISBN: 0-07-119520-3 (ISE), 2003..

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 Module 1: Overview of
Digital Design with Verilog
Overview of Digital Design with Verilog
HDL
◼ Evolution of computer aided digital circuit
design
◼ Emergence of HDLs
◼ Typical design flow
◼ Importance of HDLs
◼ Popularity of Verilog HDL
◼ Trends in HDLs

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Evolution of Computer Aided Digital
Design
◼ Digital circuits were designed with
❑ Vacuum tubes
❑ Transistors
❑ Integrated circuits (ICs)
◼ SSI
◼ MSI : hundreds of gates
◼ LSI : thousands of gates
❑ CAD techniques began to evolve
❑ circuit and Logic simulation about 100 transistors
◼ VLSI : more than 100,000 transistors
◼ ULSI : Ultra Large Scale Integration

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Overview of Digital Design with Verilog
HDL
◼ Evolution of computer aided digital circuit
design
◼ Emergence of HDLs
◼ Typical design flow
◼ Importance of HDLs
◼ Popularity of Verilog HDL
◼ Trends in HDLs

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Emergence of HDLs
◼ Hardware Description Language (HDL)
❑ A hardware description language is the language that
describes the hardware of digital systems in textual form
and resembles a programming language, but specifically
oriented to describing hardware structures and behavior.
❑ Allowed designed to model the concurrency of processes
found in hardware elements
❑ Verilog HDL originated in 1983

❑ VHDL was developed under contract from DARPA

❑ Could be used to describe digital circuits at a register

transfer level (RTL)
◼ Specify how the data flows between registers and how
the design processes the data
◼ Logic synthesis tools can be used to produce gate-level
netlist from the RTL description automatically
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Different Levels of Abstraction
◼ Architecture / Algorithm Level/Behavioural
❑ Describe the functionality (behavior) of a circuit
◼ Register Transfer Logic (RTL) Level
❑ Describe the data flow of a circuit
◼ Gate Level
❑ Describe the connectivity (structure) of a circuit
◼ Switch Level

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Different Levels of Abstraction

• Behavioral Level :Module can be implemented in terms of the desired

design algorithm without concern for the hardware implementation
details. Very similar to C programming

Dataflow Level: Module designed by specifying dataflow. The

designer is aware of how data flows between hardware registers
and how the data is processed in the design

Gate Level: Module implemented in terms of logic gates like (and

,or) and interconnection between gates

Switch Level: Module implemented with switches and

interconnects. Lowest level of Abstraction
An Example of Verilog HDL

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Overview of Digital Design with Verilog
HDL
◼ Evolution of computer aided digital circuit
design
◼ Emergence of HDLs
◼ Typical design flow
◼ Importance of HDLs
◼ Popularity of Verilog HDL
◼ Trends in HDLs

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Typical Design
Flow for
Designing VLSI
IC

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Design Flow of using HDL

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Overview of Digital Design with Verilog
HDL
◼ Evolution of computer aided digital circuit
design
◼ Emergence of HDLs
◼ Typical design flow
◼ Importance of HDLs
◼ Popularity of Verilog HDL
◼ Trends in HDLs

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Why use the HDL ?
◼ Difficult to design directly on hardware
◼ Mixed-level modeling and simulation
◼ Easier to explore different design options
◼ Reduce design time and cost

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Advantages of HDLs
◼ Advantages compared to traditional
schematic-based design
❑ Design with RTL description + logic synthesis tool
◼ Abstract level
◼ Independent to fabrication technology
◼ Reuse when fabrication technology changing
❑ Functional verification can be done early
◼ Optimized to meet the desired functionality
❑ Analogous to computer programming
◼ Textual description with comments

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Overview of Digital Design with Verilog
HDL
◼ Evolution of computer aided digital circuit
design
◼ Emergence of HDLs
◼ Typical design flow
◼ Importance of HDLs
◼ Popularity of Verilog HDL
◼ Trends in HDLs

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History of the Verilog HDL
◼ 1984: Gateway Design Automation introduced the
Verilog-XL digital logic simulator
❑ The Verilog language was part of the Verilog-XL simulator
❑ The language was mostly created by 1 person, Phil Moorby
❑ The language was intended to be used with only 1 product
◼ 1989: Gateway merged into Cadence Design
Systems
◼ 1990: Cadence made the Verilog HDL public
domain
❑ Open Verilog International (OVI) controlled the language

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History of the Verilog HDL (Cont’d)

◼ 1995: The IEEE standardized the Verilog

HDL (IEEE 1364)
◼ 2001: The IEEE enhanced the Verilog HDL
for modeling scalable designs, deep sub-
micron accuracy, etc.

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Useful Features of the Verilog HDL
◼ A general-purpose HDL
❑ Easy to learn and use

❑ Syntax is similar to C (VHDL is similar to PASCAL)

◼ Allows different levels of abstraction to be mixed in the same

model
❑ In terms of switches, gates, RTL, or behavioral code

❑ Need to learn only for stimulus and hierarchical design

◼ Most popular logic synthesis tools support Verilog

◼ Rich of Verilog HDL libraries
❑ Provided by fabrication vendors for postlogic synthesis simulation

❑ Allows the widest choice of vendors while designing a chip

◼ With powerful PLI (Programming Language Interface)

❑ Write custom C code to interact with internal data structure

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Overview of Digital Design with Verilog
HDL
◼ Evolution of computer aided digital circuit
design
◼ Emergence of HDLs
◼ Typical design flow
◼ Importance of HDLs
◼ Popularity of Verilog HDL
◼ Trends in HDLs

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 Trends in HDLs
◼ Higher levels of abstraction
❑ Think only in terms of functionality for designers

❑ CAD tools take care of the implementation details

◼ Behavioral modeling
❑ Design directly in terms of algorithms and

❑ the behavior of the circuit

◼ Formal verification
◼ Supports for Mixed-level design
❑ Ex: very high speed and timing-critical circuits like μPs

❑ Mix gate-level description directly into the RTL description

◼ System-level design in a mixed bottom-up methodology

❑ Use either existing Verilog modules, basic building blocks, or IPs

❑ Ex: SystemC for SoC designs

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 Hierarchical Modelling Concepts
◼ Learning Objectives
◼ Understand top-down and bottom-up design
methodologies for digital design.
◼ Explain differences between modules and module
instances in Verilog.
◼ Describe four levels of abstraction—behavioral, data
flow, gate level, and switch level—to represent the same
module.
◼ Describe components required for the simulation of a
digital design. Define a stimulus block and a design
block. Explain two methods of applying stimulus.

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Top Down Design Methodology

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Bottom Up Design Methodology

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Example : Design of 4 bit Ripple
Counter using Top Down approach

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 Ripple Counter
◼ A n-bit ripple counter can count up to 2n states. It is also
known as MOD n counter. It is known as ripple counter
because of the way the clock pulse ripples its way
through the flip-flops. Some of the features of ripple
counter are:
◼ It is an asynchronous counter.
◼ Different flip-flops are used with a different clock pulse.
◼ All the flip-flops are used in toggle mode.
◼ Only one flip-flop is applied with an external clock pulse
and another flip-flop clock is obtained from the output of
the previous flip-flop.
◼ The flip-flop applied with external clock pulse act as LSB
(Least Significant Bit) in the counting sequence.
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T-Flip flop

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Design Hierarchy of 4 Bit ripple
Counter

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 Verilog - Module
◼ A module is the building block in Verilog.
◼ It is declared by the keyword module
and is always terminated by the
keyword endmodule.
◼ Each statement is terminated with a
semicolon, but there is no semi-colon
after endmodule.

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 Verilog Modules
◼ Basic building block in
Verilog
❑ Hierarchical design (top-

down vs. bottom-up)

❑ Multiple modules in a

single file
◼ Order of definition not
important
❑ Modules are:
◼ Declared
◼ Instantiated
❑ Modules declarations
cannot be nested

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 Module Representation
◼ Module
❑ A logic circuit → module
❑ Its ports: inputs and
outputs
❑ Begins with module,
ends with endmodule
◼ Module<module
name>(module terminal
list);
<Module internals>
◼ End module
 Different Levels of Abstraction
 Behavioural/Architectural / Algorithmic Level
Implement a design algorithm in high-level language
constructs.
 Data flow level/Register Transfer Level
Describes the flow of data between registers and
how a design process these data.
 Gate Level
Describe the logic gates and the interconnections between
them.
 Switch (Transistor) Level
Describe the transistors and the interconnections
between them.
 Verilog Module Instances
◼ A module provides template from which we
can create actual objects.
◼ When module is invoked, Verilog creates a
unique from the template. Each object has
its own name, variables, parameters and I/O
interface.
◼ The process of creating objects from
template is called Instantiation, and the
objects are called Instances.

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Module Instantiation (cont’d)
◼ General syntax
<module_name> <instance_name>(port connection list);

◼ Example:
// assuming module ripple_carry_counter(q, clk, reset);
ripple_carry_counter cntr1(wire_vec1, wire2, wire3);

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Example Full Adder
module fastr(x, y, cin, sum, cout);
input x,y,cin;
output sum,cout;
wire t1,t2,t3;
ha ha1 ( x,y,t1,t2);
ha ha2 ( t1,cin,sum,t3 );
or or2 ( cout ,t3,t2);
endmodule
module ha(x, y, s, c);
input x,y;
output s,c;
assign s = x^y;
assign c = x&y;
endmodule

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◼
Module Instantiation
Recall the Ripple-carry counter and TFF

module TFF(q, clk, reset);

output q;
input clk, reset;
...
endmodule

module ripple_carry_counter(q, clk, reset);

output [3:0] q;
input clk, reset;

//4 instances of the module TFF are created.

TFF tff0(q[0],clk, reset);
TFF tff1(q[1],q[0], reset);
TFF tff2(q[2],q[1], reset);
TFF tff3(q[3],q[2], reset);
endmodule

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 Module Instances-Ripple Counter
module reg4 (q,d,clock); module dff (q,qb,data,clk);
output [3:0] q; output q, qb;
input [3:0] d; input data, clk;
input clock; //default delay parameter
wire [3:0] q, d; parameter delay = 1;
wire clock; dff_udp #(delay) (q,data,clk);
//port order connection, not (qb, q);
//2nd port not connected endmodule
dff u1 (q[0], , d[0], clock);
//port name connection,
//qb not connected
dff u2 (.clk(clock),.q(q[1]),.data(d[1]));
//explicit parameter redefine
dff u3 (q[2], ,d[2], clock);
defparam u3.delay = 3.2;
//implicit parameter redefine
dff #(2) u4 (q[3], , d[3], clock);
endmodule

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 Components of Simulation
◼ The functionality of the design block can be
tested by applying stimulus and checking
results such a block is called stimulus block.
◼ Separate stimulus and design block.
◼ Stimulus block can be written using verilog,
separate language is not required. Stimulus
block is also called as Test bench.
◼ Different test benches can be written to test a
design block

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Stimulus Block Instantiates Design
Block(Ripple Counter)

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Stimulus and design Blocks Instantiated in
a Dummy top level Module Design Block

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 Example:- 4 bit Ripple Counter
◼ To illustrate the concepts discussed in the previous
sections, let us build the complete simulation of a ripple
carry counter.
◼ We will define the design block and the stimulus block.
◼ We will apply stimulus to the design block and monitor
the outputs.
◼ As we develop the Verilog models, you do not need to
understand the exact syntax of each construct at this
stage.
◼ At this point, you should simply try to understand the
design process. We discuss the syntax in much greater
detail in the later modules.

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Example: 4 bit Ripple Counter
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module T_FF are created.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule
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◼ Example 2- Ripple Carry Counter Top
Block

module T_FF(q, clk, reset);

output q;
input clk, reset; wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q); // not is a Verilog-provided primitive. case sensitive
endmodule

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Example 3 . Flipflop D_F
◼ // module D_FF with synchronous reset module
D_FF(q, d, clk, reset);
◼ output q;
◼ input d, clk, reset;
◼ reg q;
// Lots of new constructs. Ignore the functionality of the // constructs. //
Concentrate on how the design block is built in a top-down fashion.
◼ always @(posedge reset or negedge clk)
◼ if (reset) q <= 1'b0;
◼ else q <= d;
◼ endmodule
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 Stimulus Block
◼ We need to write the stimulus block to check if the ripple
carry counter design is functioning correctly.
◼ In this case, we must control the signals clk and reset so
that the regular function of the ripple carry counter and
the asynchronous reset mechanism are both tested.
◼ Consider the waveforms shown in Figure next slide to
test the design.
◼ Waveforms for clk, reset, and 4-bit output q are shown.
The cycle time for clk is 10 units;
◼ The reset signal stays up from time 0 to 15 and then
goes up again from time 195 to 205. Output q counts
from 0 to 15.

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Stimulus Block

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Example 1-6 Stimulus Block
◼ module stimulus; reg clk;
◼ reg reset; wire[3:0] q;
◼ // instantiate the design block
◼ ripple_carry_counter r1(q, clk, reset);
◼ // Control the clk signal that drives the design block. Cycle time = 10 initial
◼ clk = 1'b0; //set clk to 0 always
◼ #5 clk = ~clk; //toggle clk every 5 time units
◼ // Control the reset signal that drives the design block
◼ // reset is asserted from 0 to 20 and from 200 to 220. initial
◼ begin
◼ reset = 1'b1;
◼ #15 reset = 1'b0;
◼ #180 reset = 1'b1;
◼ #10 reset = 1'b0;
◼ #20 $finish; //terminate the simulation
◼ end
◼ // Monitor the outputs
◼ initial
◼ $monitor($time, " Output q = %d", q);
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◼ endmodule
58
Summary
◼ In this module we discussed the following concepts.
◼ Two kinds of design methodologies are used for digital
design: top-down and bottom-up. A combination of these
two methodologies is used in today's digital designs. As
designs become very complex, it is important to follow
these structured approaches to manage the design
process.
◼ Modules are the basic building blocks in Verilog.
Modules are used in a design by instantiation. An
instance of a module has a unique identity and is
different from other instances of the same module. Each
instance has an independent copy of the internals of the
module. It is important to understand the difference
between modules and instances.
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◼ There are two distinct components in a
simulation: a design block and a stimulus
block. A stimulus block is used to test the
design block. The stimulus block is usually
the top-level block. There are two different
styles of applying stimulus to a design block.
◼ The example of the ripple carry counter
explains the step-by-step process of building
all the blocks required in a simulation.

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 Outcomes of Module-1
◼ After completion of the module the
students are able to:
◼ Understand the importance, trends of HDL
and design flow and design methodologies
for digital design.
◼ Differentiate the modules and module
instances in Verilog with an example.
◼ Define stimulus block and design block

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 Recommended questions
◼ 1.Discuss in brief about the evolution of CAD tools
and HDLs used in digital system design.
◼ 2.Explain the typical VLSI IC design flow with the help
of flow chart.
◼ 3.Discuss the trends in HDLs?
◼ 4.Why Verilog HDL has evolved as popular HDL in
digital circuit design?
◼ 5.Explain the advantages of using HDLs over
traditional schematic based design.
◼ 6.Describe the digital system design using
hierarchical design methodologies with an example.

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◼ 7.Apply the top-down design methodology to
demonstrate the design of ripple carry counter.
◼ 8. Apply the bottom-up design methodology to
demonstrate the design of 4-bit ripple carry adder.
◼ 9.Write Verilog HDL program to describe the 4-bit ripple
carry counter.
◼ 10.Define Module andan Instance. Describe 4 different
description styles of Verilog HDL.
◼ 11.Differentiate simulation and synthesis. What is
stimulus?
◼ 12.Write test bench to test the 4-bit ripple carry counter.
◼ 13.Write a test bench to test the 4-bit ripple carry adder.

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