‭ HDL Code:‬

V ‭ a<=”0000”;‬
q
‭Library ieee;‬ ‭elsif (clk ’event and clk=’1’) then‬
‭use ieee.std_logic_1164.all;‬ ‭if dir=’1’ then‬
‭use ieee.std_logic_arith.all;‬ ‭qa (3) <=din;‬
‭use ieee.std_logic_unsigned.all;‬ ‭qa (2) <=qa (3);‬
‭entity ALU is‬ ‭qa (1) <=qa (2);‬
‭port (a, b,s: in std_logic_vector(3 downto 0);‬ ‭qa (0) <= qa (1);‬
‭cin: in std_logic;‬ ‭else‬
‭y: out std_logic_vector(3 downto 0));‬ ‭qa (3) <=qa (2);‬
‭end ALU;‬ ‭qa (2) <=qa (1);‬
‭architecture BBBB of ALU is‬ ‭qa (1) <=qa (0);‬
‭begin‬ ‭qa (0) <= din;‬
‭with s (3 downto 0) select‬ ‭end if;‬
‭y<=a+b+cin when “0000”,‬ ‭end if;‬
‭a-b when “0001”,‬ ‭end process;‬
‭a+’1’ when “0010”,‬ ‭q<=qa;‬
‭a-‘1’ when “0011”,‬ ‭end NNNN;‬
‭a+b when “0100”,‬
‭b-‘1’ when “0101”,‬ ‭ ibrary IEEE;‬
L
‭b when “0110”,‬ ‭use ieee.STD_LOGIC_1164.ALL;‬
‭b+’1’ when “0111”;‬ ‭use ieee.std_logic_arith.all;‬
‭not a when “1000”,‬ ‭use ieee.std_logic_unsigned.all;‬
‭a and b when “1001”,‬ ‭entity UPDOWN is‬
‭a or b when “1010”,‬ ‭port (clk, reset, up_down: in std_logic;‬
‭a xor b when “1011”,‬ ‭q:out std_logic_vector(3 downto 0));‬
‭a nand b when “1100”,‬ ‭end UPDOWN;‬
‭a nor b when “1101”,‬ ‭architecture Behavioral of UPDOWN is‬
‭a xnor b when “1110”,‬ ‭signal qa: std_logic_vector (3 downto 0);‬
‭not b when others;‬ ‭begin‬
‭end BBBB;‬ ‭process (clk, reset)‬
‭Simulation result‬ ‭begin‬
‭a=0011 b=0100 S=0100 then output Y= 0111 (a + b operation)‬ ‭if (clk'event and clk='1') then‬
‭a=0011 b=0100 S=1100 then output Y = 1111 (a NAND b operation)‬ ‭if reset='1' then‬
‭qa<="0000";‬
‭ HDL Code:‬
V ‭elsif (up_down='1') then‬
‭Library ieee;‬ ‭qa<=qa+'1';‬
‭Use ieee.std_logic_1164.all;‬ ‭else‬
‭Entity FF is‬ ‭qa<=qa-'1';‬
‭Port (J, K, reset, clk: in std_logic;‬ ‭end if;‬
‭q :out std_logic);‬ ‭end if;‬
‭End FF;‬ ‭end process;‬
‭Architecture Behavior of FF is‬ ‭q<=qa;‬
‭Signal qa: std_logic;‬ ‭end Behavioral;‬
‭begin‬
‭process (clk, reset)‬
‭Begin‬
‭if (clk’event and clk=‘1’) then‬
‭if reset=‘1’ then‬
‭qa<=‘0’;‬
‭elsif (j=‘0’ and k=‘0’) then‬
‭qa<=qa;‬
‭elsif (j=‘0’ and k=‘1’) then‬
‭qa<=‘0’;‬
‭elsif (j=‘1’ and k=‘0’) then‬
‭qa<=‘1’;‬
‭else‬
‭qa<= not qa;‬
‭end if;‬
‭end if;‬
‭end process;‬
‭q<=qa;‬
‭end Behavior;‬

‭ ibrary ieee;‬
L
‭use ieee.std_logic_1164.all;‬
‭entity shift is‬
‭Port (clk, reset, din, dir: in std_logic;‬
‭q:out std_logic_vector(3 downto 0));‬
‭end shift;‬
‭architecture NNNN of shift is‬
‭signal qa: std_logic_vector (3 downto 0);‬
‭begin‬
‭Process (clk, reset)‬
‭begin‬
‭if reset=’1’ then‬