FAST CMOS OCTAL IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT

IDT54/74FCT533T/AT/CT
TRANSPARENT IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
Integrated Device Technology, Inc.
LATCHES

FEATURES: – Reduced system switching noise

• Common features:
– Low input and output leakage ≤1µA (max.) DESCRIPTION:
– CMOS power levels
The FCT373T/FCT2373T, FCT533T and FCT573T/
– True TTL input and output compatibility
FCT2573T are octal transparent latches built using an ad-
– VOH = 3.3V (typ.)
vanced dual metal CMOS technology. These octal latches
– VOL = 0.3V (typ.)
have 3-state outputs and are intended for bus oriented appli-
– Meets or exceeds JEDEC standard 18 specifications
cations. The flip-flops appear transparent to the data when
– Product available in Radiation Tolerant and Radiation Latch Enable (LE) is HIGH. When LE is LOW, the data that
Enhanced versions meets the set-up time is latched. Data appears on the bus
– Military product compliant to MIL-STD-883, Class B when the Output Enable (OE) is LOW. When OE is HIGH, the
and DESC listed (dual marked) bus output is in the high- impedance state.
– Available in DIP, SOIC, SSOP, QSOP, CERPACK The FCT2373T and FCT2573T have balanced drive out-
and LCC packages puts with current limiting resistors. This offers low ground
• Features for FCT373T/FCT533T/FCT573T: bounce, minimal undershoot and controlled output fall times-
– Std., A, C and D speed grades reducing the need for external series terminating resistors.
– High drive outputs (-15mA IOH, 48mA IOL) The FCT2xxxT parts are plug-in replacements for FCTxxxT
– Power off disable outputs permit “live insertion” parts.
• Features for FCT2373T/FCT2573T:
– Std., A and C speed grades
– Resistor output (-15mA IOH, 12mA IOL Com.)
(-12mA IOH, 12mA IOL Mil.)
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT373T/2373T AND IDT54/74FCT573T/2573T
D0 D1 D2 D3 D4 D5 D6 D7

D D D D D D D D
O O O O O O O O
G G G G G G G G

LE

OE
O0 O1 O2 O3 O4 O5 O6 O7
2564 cnv* 01

FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT533T

D0 D1 D2 D3 D4 D5 D6 D7

D D D D D D D D
O O O O O O O O
G G G G G G G G

LE

OE

O0 O1 O2 O3 O4 O5 O6 O7
The IDT logo is a registered trademark of Integrated Device Technology, Inc. 2564 cnv* 02

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995

1995 Integrated Device Technology, Inc. 6.12 DSC-4216/6
1
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT54/74FCT373/2373T
INDEX

VCC
OE
O0
D0

O7
OE 1 20 VCC
O0 2 19 O7
D0 3 18 D7 3 2 20 19
P20-1 4 1 18
D1 4 17 D6 D1 D7
D20-1
O1 5 SO20-2 16 O6 O1 5 17 D6
O2 6 SO20-7 15 O5 O2 6 L20-2 16 O6
SO20-8 D2 7 15 O5
D2 7 14 D5
&
D3 8 13 D4 D3 8 14 D5
E20-1
9 10 11 12 13
O3 9 12 O4
GND 10 11 LE

D4
O3

O4
GND
LE
2564 cnv* 03 2564 cnv* 04

DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW LCC
TOP VIEW

IDT54/74FCT573/2573T
INDEX

VCC
O0
D0
OE
D1
OE 1 20 VCC
D0 2 19 O0
3 2 20 19
D1 3 18 O1 4 1 18
P20-1 D2 O1
D2 4 D20-1 17 O2 5 17
D3 O2
D3 5 SO20-2 16 O3 D4 6 16 O3
L20-2
D4 6 SO20-7 15 O4
SO20-8 D5 7 15 O4
D5 7 14 O5 D6 8 14 O5
&
D6 8 E20-1 13 O6 9 10 11 12 13
D7 9 12 O7
GND
D7

10 11 LE
O7
GND
LE

O6
2564 cnv* 05 2564 cnv* 06

DIP/SOIC/SSOP/QSOP/CERPACK LCC
TOP VIEW TOP VIEW

IDT54/74FCT533
INDEX
VCC
OE

O7
D0
O0

OE 1 20 VCC
O0 2 19 O7
D0 3 18 D7 3 2 20 19
D1 4 1 18 D7
D1 4 P20-1 17 D6
O1 O1 5 17 D6
5 D20-1 16 O6
O2 6 SO20-2 15 O5 O2 6 L20-2 16 O6
& D2 7 15 O5
D2 7 14 D5
E20-1
D3 8 13 D4 D3 8 14 D5
9 10 11 12 13
O3 9 12 O4
GND 10 11 LE
LE
O4
GND

D4
O3

2564 cnv* 07 2564 cnv* 08

DIP/SOIC/CERPACK
TOP VIEW LCC
TOP VIEW

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FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE (533)(1) FUNCTION TABLE (373 and 573)(1)

Inputs Outputs Inputs Outputs
DN LE OE ON DN LE OE ON
H H L L H H L H
L H L H L H L L
X X H Z X X H Z
NOTE: 2564 tbl 01 NOTE: 2564 tbl 02
1. H = HIGH Voltage Level 1. H = HIGH Voltage Level
L = LOW Voltage Level L = LOW Voltage Level
X = Don’t Care X = Don’t Care
Z = High Impedance Z = High Impedance

DEFINITION OF FUNCTIONAL TERMS

Pin Names Description
DN Data Inputs
LE Latch Enable Input (Active HIGH)
OE Output Enable Input (Active LOW)
ON 3-State Outputs
ON Complementary 3-State Outputs
2564 tbll 03

ABSOLUTE MAXIMUM RATINGS(1) CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Rating Commercial Military Unit Symbol Parameter(1) Conditions Typ. Max. Unit
VTERM(2) Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V CIN Input VIN = 0V 6 10 pF
with Respect to Capacitance
GND
COUT Output VOUT = 0V 8 12 pF
VTERM(3) Terminal Voltage –0.5 to –0.5 to V Capacitance
with Respect to VCC +0.5 VCC +0.5 2564 lnk 05
NOTE:
GND
1. This parameter is measured at characterization but not tested.
TA Operating 0 to +70 –55 to +125 °C
Temperature
TBIAS Temperature –55 to +125 –65 to +135 °C
Under Bias
TSTG Storage –55 to +125 –65 to +150 °C
Temperature
PT Power Dissipation 0.5 0.5 W
I OUT DC Output –60 to +120 –60 to +120 mA
Current
NOTES: 2564 lnk 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.

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FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current(4) VCC = Max. VI = 2.7V — — ±1 µA
II L Input LOW Current (4) VI = 0.5V — — ±1
I OZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
I OZL (3-State Output pins) (4) VO = 0.5V — — ±1
II Input HIGH Current(4) VCC = Max., VI = VCC (Max.) — — ±1 µA
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
VH Input Hysteresis — — 200 — mV
I CC Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 0.01 1 mA
2564 lnk 06

OUTPUT DRIVE CHARACTERISTICS FOR FCT373T/533T/573T

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VOH Output HIGH Voltage VCC = Min. I OH = –6mA MIL. 2.4 3.3 — V
VIN = VIH or V IL I OH = –8mA COM'L.
I OH = –12mA MIL. 2.0 3.0 — V
I OH = –15mA COM'L.
VOL Output LOW Voltage VCC = Min. I OL = 32mA MIL. — 0.3 0.5 V
VIN = VIH or V IL I OL = 48mA COM'L.
I OS Short Circuit Current VCC = Max., VO = GND (3) –60 –120 –225 mA
I OFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or V O ≤ 4.5V — — ±1 µA
2564 lnk 07

OUTPUT DRIVE CHARACTERISTICS FOR FCT2373T/2573T

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
I ODL Output LOW Current VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) 16 48 — mA
I ODH Output HIGH Current VCC = 5V, VIN = VIH or V IL, VOUT = 1.5V (3) –16 –48 — mA
VOH Output HIGH Voltage VCC = Min. I OH = –12mA MIL. 2.4 3.3 — V
VIN = VIH or VIL I OH = –15mA COM'L.
VOL Output LOW Voltage VCC = Min. I OL = 12mA — 0.3 0.50 V
VIN = VIH or V IL
2564 lnk 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.

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FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
∆ICC Quiescent Power Supply Current VCC = Max. — 0.5 2.0 mA
TTL Inputs HIGH VIN = 3.4V(3)
ICCD Dynamic Power Supply VCC = Max. VIN = VCC FCTxxxT — 0.15 0.25 mA/
Current(4) Outputs Open VIN = GND MHz
OE = GND FCT2xxxT — 0.06 0.12
One Input Toggling
50% Duty Cycle
IC Total Power Supply Current (6) VCC = Max. VIN = VCC FCTxxxT — 1.5 3.5 mA
Outputs Open VIN = GND FCT2xxxT — 0.6 2.2
fi = 10MHz
50% Duty Cycle VIN = 3.4 FCTxxxT — 1.8 4.5
OE = GND VIN = GND
LE = VCC FCT2xxxT 0.9 3.2
One Bit Toggling
VCC = Max. VIN = VCC FCTxxxT — 3.0 6.0 (5)
Outputs Open VIN = GND FCT2xxxT — 1.2 3.4 (5)
fi = 2.5MHz
50% Duty Cycle VIN = 3.4 FCTxxxT — 5.0 14.0 (5)
OE = GND VIN = GND
LE = VCC FCT2xxxT — 3.2 11.4 (5)
Eight Bits Toggling
NOTES: 2564 tbl 09
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

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FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT373T/2373T/573T/2573T FCT373AT/2373AT/573AT/2573AT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 1.5 8.0 1.5 8.5 1.5 5.2 1.5 5.6 ns
tPHL DN to ON RL = 500Ω
tPLH Propagation Delay 2.0 13.0 2.0 15.0 2.0 8.5 2.0 9.8 ns
tPHL LE to ON
tPZH Output Enable Time 1.5 12.0 1.5 13.5 1.5 6.5 1.5 7.5 ns
tPZL
tPHZ Output Disable Time 1.5 7.5 1.5 10.0 1.5 5.5 1.5 6.5 ns
tPLZ
tSU Set-up Time HIGH 2.0 — 2.0 — 2.0 — 2.0 — ns
or LOW, DN to LE
tH Hold Time HIGH 1.5 — 1.5 — 1.5 — 1.5 — ns
or LOW, DN to LE
tW LE Pulse Width HIGH 6.0 — 6.0 — 5.0 — 6.0 — ns
2564 tbl 10

FCT373CT/2373CT/573CT/2573CT FCT373DT/573DT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 1.5 4.2 1.5 5.1 1.5 3.8 — — ns
tPHL DN to ON RL = 500Ω
tPLH Propagation Delay 2.0 5.5 2.0 8.0 2.0 4.0 — — ns
tPHL LE to ON
tPZH Output Enable Time 1.5 5.5 1.5 6.3 1.5 4.8 — — ns
tPZL
tPHZ Output Disable Time 1.5 5.0 1.5 5.9 1.5 4.0 — — ns
tPLZ
tSU Set-up Time HIGH 2.0 — 2.0 — 1.5 — — — ns
or LOW, DN to LE
tH Hold Time HIGH 1.5 — 1.5 — 1.0 — — — ns
or LOW, DN to LE
tW LE Pulse Width HIGH (3) 5.0 — 6.0 — 3.0 — — — ns
2564 tbl 11

FCT533T FCT533AT FCT533CT

Com'l. Mil. Com'l. Mil. Com'l. Mil.

Symbol Parameter Conditions (1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 1.5 10.0 1.5 12.0 1.5 5.2 1.5 5.6 1.5 4.2 1.5 5.1 ns
tPHL DN to ON RL = 500Ω
tPLH Propagation Delay 2.0 13.0 2.0 14.0 2.0 8.5 2.0 9.8 2.0 5.5 2.0 8.0 ns
tPHL LE to ON
tPZH Output Enable 1.5 11.0 1.5 12.5 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns
tPZL Time
tPHZ Output Disable 1.5 7.0 1.5 8.5 1.5 5.5 1.5 6.5 1.5 5.0 1.5 5.9 ns
tPLZ Time
tSU Set-up Time HIGH 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns
or LOW, DN to LE
tH Hold Time HIGH 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
or LOW, DN to LE
tW LE Pulse Width HIGH 6.0 — 6.0 — 5.0 — 6.0 — 5.0 — 6.0 — ns
NOTES: 2564 tbl 12
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.

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FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS SWITCH POSITION
Test Switch
V CC 7.0V Open Drain
Disable Low Closed
500Ω Enable Low
VIN V OUT Open
All Other Tests
Pulse D.U.T. 2564 lnk 13
Generator DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
50pF
500Ω RT = Termination resistance: should be equal to ZOUT of the Pulse
RT CL Generator.

2564 drw 09

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA 3V
INPUT 1.5V
tSU tH 0V LOW-HIGH-LOW
PULSE 1.5V
TIMING 3V
INPUT 1.5V
0V tW
ASYNCHRONOUS CONTROL
PRESET tREM
3V
CLEAR 1.5V HIGH-LOW-HIGH 1.5V
ETC. 0V PULSE
SYNCHRONOUS CONTROL
PRESET 3V 2564 drw 11
CLEAR 1.5V
CLOCK ENABLE tSU tH 0V
ETC. 2564 drw 10

PROPAGATION DELAY ENABLE AND DISABLE TIMES

ENABLE DISABLE
3V 3V
SAME PHASE 1.5V
INPUT TRANSITION CONTROL 1.5V
0V INPUT
tPLH tPHL 0V
VOH tPZL tPLZ
OUTPUT 1.5V OUTPUT 3.5V 3.5V
VOL NORMALLY SWITCH 1.5V
tPLH tPHL LOW CLOSED 0.3V VOL
3V tPZH tPHZ
OPPOSITE PHASE
INPUT TRANSITION 1.5V VOH
0V OUTPUT SWITCH 0.3V
NORMALLY OPEN 1.5V
2564 drw 12 HIGH
0V 0V
2564 drw 13
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

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FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT XX FCT X XXXX X X

Temp. Range Family Device Type Package Process

Blank Commercial
B MIL-STD-883, Class B

P Plastic DIP
D CERDIP
SO Small Outline IC
L Leadless Chip Carrier
E CERPACK
PY Shrink Small Outline Package
Q Quarter-size Small Outline Package

373T Non-Inverting Octal Transparent Latch

573T Non-Inverting Octal Transparent Latch
533T Inverting Octal Transparent Latch
373AT
573AT
533AT
373CT
573CT
533CT
373DT
573DT

Blank High Drive

2 Balanced Drive

54 –55°C to +125°C
74 0°C to +70°C

2564 drw 14

6.12 8