CMOS STATIC RAM IDT7164S

IDT7164L
64K (8K x 8-BIT)
Integrated Device Technology, Inc.

FEATURES: DESCRIPTION:
• High-speed address/chip select access time The IDT7164 is a 65,536 bit high-speed static RAM orga-
— Military: 20/25/30/35/45/55/70/85ns (max.) nized as 8K x 8. It is fabricated using IDT’s high-performance,
— Commercial: 15/20/25/35/70ns (max.) high-reliability CMOS technology.
• Low power consumption Address access times as fast as 15ns are available and the
• Battery backup operation — 2V data retention voltage circuit offers a reduced power standby mode. When CS1 goes
(L Version only) HIGH or CS2 goes LOW, the circuit will automatically go to,
• Produced with advanced CMOS high-performance and remain in, a low-power stand by mode. The low-power (L)
technology version also offers a battery backup data retention capability
• Inputs and outputs directly TTL-compatible at power supply levels as low as 2V.
• Three-state outputs All inputs and outputs of the IDT7164 are TTL-compatible
• Available in: and operation is from a single 5V supply, simplifying system
— 28-pin DIP and SOJ designs. Fully static asynchronous circuitry is used, requiring
• Military product compliant to MIL-STD-883, Class B no clocks or refreshing for operation.
The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ;
and 28-pin 600 mil DIP.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

A0
V CC

ADDRESS 65,536 BIT GND

DECODER MEMORY ARRAY

A12

0 7

I/O 0
I/O CONTROL

I/O 7

CS 1

CS 2 CONTROL
OE LOGIC
2967 drw 01
WE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1996

1996 Integrated Device Technology, Inc. 2967/8
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 6.1 1
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

NC 1 28 V CC
A 12 2 27 WE
A7 3 26 CS2
A6 4 25 A8 TRUTH TABLE(1,2,3)
A5 5
D28-1
24 A9 WE CS1 CS2 OE I/O Function
A4 6 23 A 11 X H X X High-Z Deselected – Standby (ISB)
A3 7 D28-3 22 OE X X L X High-Z Deselected – Standby (ISB)
A2 8 P28-1 21 A 10
A1 9
P28-2 20 CS1 X VHC VHC or
VLC
X High-Z Deselected –Standby (ISB1)

A0 10 19 I/O 7
SO28-5 X X VLC X High-Z Deselected –Standby (ISB1)
I/O 0 11 18 I/O 6
17 I/O 5 H L H H High-Z Output Disabled
I/O 1 12
I/O 2 13 16 I/O 4 H L H L DataOUT Read Data
GND 14 15 I/O 3 L L H X DataIN Write Data
NOTES: 2967 tbl 02
DIP/SOJ
2967 drw 02
1. CS2 will power-down CS1, but CS1 will not power-down CS2.
TOP VIEW 2. H = VIH, L = VIL, X = don't care.
3. VLC = 0.2V, VHC = VCC - 0.2V

PIN DESCRIPTIONS
Name Description
A0–A12 Address
I/O0–I/O7 Data Input/Output
CS1 Chip Select
CS2 Chip Select
WE Write Enable RECOMMENDED OPERATING
OE Output Enable TEMPERATURE AND SUPPLY VOLTAGE
GND Ground Grade Temperature GND VCC
VCC Power Military –55°C to +125°C 0V 5V ± 10%
2967 tbl 01 Commercial 0°C to +70°C 0V 5V ± 10%
2967 tbl 04

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Rating Com’l. Mil. Unit
(2)
VTERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND
TA Operating 0 to +70 –55 to +125 °C RECOMMENDED DC OPERATING
Temperature CONDITIONS
TBIAS Temperature –55 to +125 –65 to +135 °C Symbol Parameter Min. Typ. Max. Unit
Under Bias
VCC Supply Voltage 4.5 5.0 5.5 V
TSTG Storage –55 to +125 –65 to +150 °C
GND Supply Voltage 0 0 0 V
Temperature
VIH Input HIGH Voltage 2.2 — VCC + 0.5 V
PT Power Dissipation 1.0 1.0 W
VIL Input LOW Voltage –0.5(1) — 0.8 V
IOUT DC Output 50 50 mA
Current NOTE: 2967 tbl 05
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
NOTES: 2967 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.5V.

6.1 2
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter(1) Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
CI/O I/O Capacitance VOUT = 0V 8 pF
NOTE: 2967 tbl 06
1. This parameter is determined by device characterization, but is not
production tested.

DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7164S15 7164S20 7164S25 7164S30
7164L15 7164L20 7164L25 7164L30
Symbol Parameter Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Unit
ICC1 Operating Power Supply S 110 — 100 110 90 110 — 100 mA
Current, CS1 = VIL, CS2 = VIH,
Outputs Open, VCC = Max., f = 0(3) L 100 — 90 100 80 100 — 90
ICC2 Dynamic Operating Current S 180 — 170 180 170 180 — 170 mA
CS1 = VIL, CS2 = VIH,
Outputs Open, VCC = Max., f = fMAX(3) L 150 — 150 160 150 160 — 150
ISB Standby Power Supply Current S 20 — 20 20 20 20 — 20 mA
(TTL Level), CS1 ≥ VIH or CS2 ≤ VIL
VCC = Max., Outputs Open, f = fMAX(3) L 3 — 3 5 3 5 — 5
ISB1 Full Standby Power Supply Current S 15 — 15 20 15 20 — 20 mA
(CMOS Level), f = 0(3), VCC = Max.
1. CS1 ≥ V HC and CS2 ≥ V HC, or L 0.2 — 0.2 1 0.2 1 — 1
2. CS2 ≤ VLC

DC ELECTRICAL CHARACTERISTICS(1) (Continued)

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7164S35 7164S45 7164S55 7164S70(2)/85(4)
7164L35 7164L45 7164L55 7164L70(2)/85(4)
Symbol Parameter Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Unit
ICC1 Operating Power Supply S 90 100 — 100 — 100 90 100 mA
Current, CS1 = VIL, CS2 = VIH,
Outputs Open, VCC = Max., f = 0(3) L 80 90 — 90 — 90 80 90
ICC2 Dynamic Operating Current S 150 160 — 160 — 160 150 160 mA
CS1 = VIL, CS2 = VIH,
Outputs Open, VCC = Max., f = fMAX(3) L 130 140 — 130 — 125 130 120
ISB Standby Power Supply Current S 20 20 — 20 — 20 20 20 mA
(TTL Level), CS1 ≥ V IH, or CS2 ≤ VIL
VCC = Max., Outputs Open, f = fMAX(3) L 3 5 — 5 — 5 3 5
ISB1 Full Standby Power Supply Current S 15 20 — 20 — 20 15 20 mA
(CMOS Level), f = 0(3), VCC = Max.
1. CS1 ≥ VHC and CS2 ≥ VHC, or L 0.2 1 — 1 — 1 0.2 1
2. CS2 ≤ VLC
NOTES: 2967 tbl 07
1. All values are maximum guaranteed values.
2. 70 ns available in both military and commercial devices.
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
4. Also available: 100ns military devices.

6.1 3
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%)
IDT7164S IDT7164L
Symbol Parameter Test Condition Min. Max. Min. Max. Unit
|ILI| Input Leakage Current VCC = Max., MIL. — 10 — 5 µA
VIN = GND to VCC COM’L. — 5 — 2
|ILO| Output Leakage Current VCC = Max., CS1 = VIH, MIL. — 10 — 5 µA
VOUT = GND to VCC COM’L. — 5 — 2
VOL Output Low Voltage IOL = 8mA, VCC = Min. 0.4 — 0.4 V
IOL = 10mA, VCC = Min. — 0.5 — 0.5
VOH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — 2.4 — V
2967 tbl 08

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES

(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Typ. (1) Max.
VCC @ VCC @
Symbol Parameter Test Condition Min. 2.0v 3.0V 2.0V 3.0V Unit
VDR VCC for Data Retention — 2.0 — — — — V
ICCDR Data Retention Current MIL. — 10 15 200 300 µA
COM’L. — 10 15 60 90
tCDR(3) Chip Deselect to Data 1. CS1 ≥ VHC 0 — — — — ns
Retention Time CS2 ≥ VHC, or
tR(3) Operation Recovery Time 2. CS2 ≤ VLC tRC(2) — — — — ns
|ILI| (3)
Input Leakage Current — — — 2 2 µA
NOTES: 2967 tbl 09
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.

AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
2967 tbl 10

5V 5V

480Ω 480Ω

DATA OUT DATA OUT

255Ω 30pF* 255Ω 5pF*

2967 drw 03 2967 drw 04

Figure 2. AC Test Load
Figure 1. AC Test Load
(for tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ)
*Includes scope and jig capacitances

6.1 4
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)

7164S15(1) 7164S20 7164S25 7164S30(2)
7164L15(1) 7164L20 7164L25 7164L30
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 15 — 20 — 25 — 30 — ns
tAA Address Access Time — 15 — 19 — 25 — 29 ns
(3)
tACS1 Chip Select-1 Access Tim — 15 — 20 — 25 — 30 ns
(3)
tACS2 Chip Select-2 Access Time — 20 — 25 — 30 — 35 ns
(4)
tCLZ1,2 Chip Select-1, 2 to Output in Low-Z 5 — 5 — 5 — 5 — ns
tOE Output Enable to Output Valid — 7 — 8 — 12 — 15 ns
tOLZ(4) Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — ns
(4)
tCHZ1,2 Chip Select-1, 2 to Output in High-Z — 8 — 9 — 13 — 13 ns
(4)
tOHZ Output Disable to Output in High-Z — 7 — 8 — 10 — 12 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — ns
(4)
tPU Chip Select to Power Up Time 0 — 0 — 0 — 0 — ns
(4)
tPD Chip Deselect to Power Down Time — 15 — 20 — 25 — 30 ns
Write Cycle
tWC Write Cycle Time 15 — 20 — 25 — 30 — ns
tCW1, 2 Chip Select to End-of-Write 14 — 15 — 18 — 22 — ns
tAW Address Valid to End-of-Write 14 — 15 — 18 — 22 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 14 — 15 — 21 — 23 — ns
tWR1 Write Recovery Time (CS1, WE) 0 — 0 — 0 — 0 — ns
tWR2 Write Recovery Time (CS2) 5 — 5 — 5 — 5 — ns
tWHZ(4) Write Enable to Output in High-Z — 6 — 8 — 10 — 12 ns
tDW Data to Write Time Overlap 8 — 10 — 13 — 13 — ns
tDH1 Data Hold from Write Time (CS1, WE) 0 — 0 — 0 — 0 — ns
tDH2 Data Hold from Write Time (CS2) 5 — 5 — 5 — 5 — ns
tOW(4) Output Active from End-of-Write 4 — 4 — 4 — 4 — ns
NOTES: 2967 tbl 11
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only. Also available: 100ns military devices.
3. Both chip selects must be active for the device to be selected.
4. This parameter is guaranteed by device characterization, but is not production tested.

6.1 5
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS (Continued) (VCC = 5.0V ± 10%, All Temperature Ranges)

7164S35 7164S45(2) 7164S55(2) 7164S70/85(2)
7164L35 7164L45(2) 7164L55(2) 7164L70/85(2)
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 35 — 45 — 55 — 70/85 — ns
tAA Address Access Time — 35 — 45 — 55 — 70/85 ns
(3)
tACS1 Chip Select-1 Access Time — 35 — 45 — 55 — 70/85 ns
(3)
tACS2 Chip Select-2 Access Time — 40 — 45 — 55 — 70/85 ns
(4)
tCLZ1,2 Chip Select-1, 2 to Output in Low-Z 5 — 5 — 5 — 5 — ns
tOE Output Enable to Output Valid — 18 — 25 — 30 — 35/40 ns
(4)
tOLZ Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — ns
(4)
tCHZ1,2 Chip Select-1, 2 to Output in High-Z — 15 — 20 — 25 — 30/35 ns
(4)
tOHZ Output Disable to Output in High-Z — 15 — 20 — 25 — 30/35 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — ns
(4)
tPU Chip Select to Power Up Time 0 — 0 — 0 — 0 — ns
(4)
tPD Chip Deselect to Power Down Time — 35 — 45 — 55 — 70/85 ns
Write Cycle
tWC Write Cycle Time 35 — 45 — 55 — 70/85 — ns
tCW1, 2 Chip Select to End-of-Write 25 — 33 — 50 — 60/75 — ns
tAW Address Valid to End-of-Write 25 — 33 — 50 — 60/75 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 25 — 25 — 50 — 60/75 — ns
tWR1 Write Recovery Time (CS1, WE) 0 — 0 — 0 — 0 — ns
tWR2 Write Recovery Time (CS2) 5 — 5 — 5 — 5 — ns
tWHZ(4) Write Enable to Output in High-Z — 14 — 18 — 25 — 30/35 ns
tDW Data to Write Time Overlap 15 — 20 — 25 — 30/35 — ns
tDH1 Data Hold from Write Time (CS1, WE) 0 — 0 — 0 — 0 — ns
tDH2 Data Hold from Write Time (CS2) 5 — 5 — 5 — 5 — ns
tOW(4) Output Active from End-of-Write 4 — 4 — 4 — 4 — ns
NOTES: 2967 tbl 11
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only. Also available: 100ns military devices.
3. Both chip selects must be active for the device to be selected.
4. This parameter is guaranteed by device characterization, but is not production tested.

6.1 6
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 1(1)

tRC

ADDRESS

tAA tOH

OE
tOE
tOLZ (5)

CS2
tACS2 (5)
tCHZ2
tCLZ2 (5)

CS1
tACS1 tOHZ (5)
(5) (5)
tCLZ1 tCHZ1
DATA OUT DATA VALID

2967 drw 05
(1, 2, 4)
TIMING WAVEFORM OF READ CYCLE NO. 2
tRC

ADDRESS

tAA
tOH
tOH

DATA OUT DATA VALID

2967 drw 06

(1, 3, 4)
TIMING WAVEFORM OF READ CYCLE NO. 3
CS1

CS2
tACS2
(5)
tCLZ2 (5) tCHZ2
tACS1 (5)
tCHZ1
tCLZ1 (5)

DATA OUT DATA VALID

tPU

POWER ICC
SUPPLY
CURRENT ISB

NOTES: tPD
1. WE is HIGH for Read cycle. 2967 drw 07
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.

6.1 7
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 6)

tWC

ADDRESS

CS2

CS1
tAW tWR1(3)
tAS

WE
(4) (6)
tWP tOW(7)
DATA OUT

tDW tDH1, 2
tWHZ (7)
DATA IN DATA VALID

2967 drw 08

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2)

tWC

ADDRESS

tAS tWR2 (3)

CS2

tCW tWR1 (3)

CS1 (5)

tAW

WE
tDW tDH1,2

DATA IN DATA VALID

2967 drw 09

NOTES:
1. WE, CS1 or CS2 must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2.
3. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the
I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not
apply and the minimum write pulse width is as short as the specified tWP.
7. Transition is measured ±200mV from steady state.

6.1 8
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

LOW VCC DATA RETENTION WAVEFORM

DATA
RETENTION
MODE
V CC 4.5V 4.5V

tCDR V DR ≥ 2V tR

CS V IH V IH
V DR
2967 drw 10

ORDERING INFORMATION
IDT 7164 X XX XXX X
Device Power Speed Package Process/
Type Temperature
Range

Blank Commercial (0°C to +70°C)

B Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B

Y 300 mil SOJ (SO28-5)

TD 300 mil CERDIP (D28-3)
D 600 mil CERDIP (D28-1)
P 600 mil Plastic DIP (P28-1)
TP 300 mil Plastic DIP (P28-2)

15 Commercial Only
20
25
30 Military Only
35 Speed in nanoseconds
45 Military Only
55 Military Only
70
85 Military Only
S Standard Power
L Low Power 2967 drw 11

6.1 9