CLASS TEST S.No.

: 01SK_CS_ABC_010424

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COMPUTER ORGANIZATION
COMPUTER SCIENCE & IT
Date of Test : 01/04/2024

ANSWER KEY h

1. (a) 7. (b) 13. (b) 19. (d) 25. (d)

2. (b) 8. (a) 14. (b) 20. (d) 26. (d)

3. (c) 9. (c) 15. (b) 21. (b) 27. (b)

4. (a) 10. (b) 16. (b) 22. (d) 28. (b)

5. (d) 11. (c) 17. (c) 23. (b) 29. (a)

6. (b) 12. (d) 18. (b) 24. (b) 30. (c)

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D E TA I L E D E X P L A N AT I O N S

1. (a)
Since, it uses horizontal micro-programmed that requires 1 bit control / signal.
For 125 control signal, we need 125 bits.
Total number of micro-operation instruction = 215 × 6 = 1290
It requires 11 bit.

2. (b)
• Isolated Input/Output: This configuration uses the common bus and common address space but
different control signal for both memory and input/output, so that memory address range is not affected
by interface address assignment.
• Memory Mapped Input/Output: This configuration uses common bus and common control signals but
unique address space.
• In synchronous clock is common and in asynchronous clock is different.

3. (c)
When instruction is a computation:
Memory reference : Fetch instruction
Fetch reference of the operand
Fetch operand
Total 3 memory references.
When instruction is a branch:
Memory reference : Fetch instruction
Fetch operand reference and loading program counter
Total 2 memory references.

4. (a)
• Implied addressing mode: Specified implicitly in the definition of instruction.
• Immediate addressing mode: Specified in the address field of an instruction.
• Register addressing mode: Registers which are in CPU.
• Register indirect addressing mode: Register specifies the address of the operand.

5. (d)
Instruction pipelining is a technique that implements a form of parallelism called instruction level parallelism
with a single processor.
It therefore allows faster CPU thoughput.

6. (b)
Pr ogrammed I/O: Processor issues an I/O command, on behalf of a processor, to an IO module; that
Programmed
process then busy-waits for the operation to be completed before proceeding.
Interrupt driven I/O: The processor isues an IO command on behalf of a process, continues to execute
subsequent instruction, and is interrupted by the IO module when the latter has completed its work.
Direct memory access: A DMA module controls the exchange of data between main memory and IO
module.

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7. (b)
For 1 second it take 109 byte
64 k
So for 64 kbyte it takes = = 64 µsec
109
Main memory latency = 64 µsec
Total time required to fetch = 64 µsec + 64 µsec = 128 µsec

8. (a)
64K
Number lines = ⇒ 211
32
211
Number sets = ⇒ 27
24

32 bit

Tag SO WO

20 bit 7 bit 5 bit

Tag memory size = S × P × # tag bits

= 128 × 16 × 25 = 51200 bits

9. (c)
Consider each statement :
S 1 : Microprogrammed control unit uses variable logic to interrupt instruction since its uses encoded
scheme for the instruction.
S 2 : Horizontal microprogramming control unit does not requires an additional hardware (like a decoder)
because a fixed logic is associated with the instructions.
S 3 : The performance of a system depends on the direct proportion of memory accesses satisfied by
cache.

10. (b)
1 bit 8 bits 23 bits
1 10000101 11000 ... 0
Sign Exponent Mantissa

Bias exponent value = 10000101

Actual exponent = 10000101 – 127 [∵ 127 is bias]
= 133 – 127 = 6
Normalized mantissa bits = 11000000000000000000000
Actual value = 1.11000000000000000000000
Decimal number = 1.11000 × 26
= –(1110000)2
= –(112)10

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11. (c)
Rate of transfer to or from any one disk = 30 MBps.

4B
Maximum memory transfer rate = = 400 × 106 Bps = 400 MBps
10 × 10 −9
Since rate of data transfer = 30 MBps

 400 
Here number of disk transfer =   = 13
 30 
Therefore, 13 disks can simultaneously transfer data to or from the main memory.

12. (d)
1 2 3 4 5 6 7 8 9 10 11
I1 IF ID EX MM WB
I2 IF ID ID EX MM WB
I3 IF IF ID EX MM WB
I4 IF ID EX MM WB
I5 IF ID ID EX MM WB

Total 11 cycles are required.

13. (b)
Memory mapped I/O uses the same address bus to address both memory and I/O devices the memory
and registers of the I/O devices are mapped to address values.
So, when an address is accessed by the CPU, it may refer to a portion of physical RAM, but it can also
refer to memory of I/O device.

14. (b)

16 KB 214
Number of lines = = 5 = 29
32 B 2

29
Number of sets = 2
= 27
2
Physical address size = 256 MB = 28 bits

28 bit

TAG SO WO

16 bit 7 bit log2 32 = 5 bit

Total set will be from 0 to 127 (using 7 bits).

In option (b)
(FB3D64C)16 = F B 3 D 0 1 1 0 0 1 0 0 C

16 bit 7 bit 5 bit

TAG set WO

It's decimal
value is 50
Hence option (b) is correct.

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15. (b)
Considering each statement :
S 1 : Delayed control transfer, also known as delayed branching, is an attempt to cope with control hazards.
S 2 : The branch target stores the previous target address for the current branch, other algorithms for
branch prediction also exist.
S 3 : For any given instruction set architecture implemented on a N-stage pipelined processor, N registers
probably is not enough registers to completely prevent structural hazards involving a shortage of
register hardware.

16. (b)

[1 × 0.1 + 2 × 0.1 + 3 × 0.5 + 4 × 0.3]

P1 CPU time =
1.5 × 109
= 2 × 10–9 sec = 2 nsec

[2 × 0.1 + 2 × 0.1 + 2 × 0.5 + 2 × 0.3]

P2 CPU time =
2.5 × 109
= 0.8 × 10–9 sec = 0.8 nsec
∴ P2 is faster than P1 processor.

17. (c)

1000
2.5 memory reference per instruction ⇒ instruction per 1000 reference.
2.5
⇒ 400 instructions.
 260   120 
200 =   x+ 2x
 400 
Now
 400 

400 × 200
x =
500
80000
x =
500
x = 160
2x = 320

18. (b)

Pipeline prog

Others Memory Instruction

All other Memory 60% 40%
instruction operations are
are optimized not optimized
Optimized Not optimized
0 stalls
60% 40%
0 stalls 3 stalls

0 stalls 3 stalls

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Number of stalls/Instruction = (0.4 × 0.4 × 3) = 0.48

Average instruction ET = (1 + # stalls / Instruction) × Cycle time
= (1 + 0.48) × 8 ns = 11.84 ns

19. (d)
Increasing the cache line size brings in more from memory when a miss occurs. If accessing a certain
byte suggests that nearby bytes are likely to be accessed soon (locality), then increasing the cache line
essentially prefetches those other bytes. This, in turn, forestalls a later cache miss on those other bytes.
If misses occur because the cache is too small, then the designers should increase the size!
Conflict misses occur when multiple memory locations are repeatedly accessed but map to the same
cache location. Consequently, when they are accessed, they keep kicking one another out of the cache.
Increasing the associativity implies that each chunk of the cache is effectively doubled so that more than
one memory item can rest in the same cache chunk.

20. (d)
Considering each statement :
S1 : 4-control signals are needed for each data register.

MDRoutE MDRout

MDR

MDRinE MDRin

(Memory (Internal
bus) processor bus)
MDR is directly connected to data lines of the processor. It has 2 input and 2 output. Data may be
loaded into MDR either from memory or from internal bus. Data present in MDR may be placed on
either bus are memory. It requires total 4 control signals.
S2 : The main disadvantage of direct mapping is that cache hit ratio decreases sharply if two or more
frequently used blocks map on the same region.

21. (b)
Stages of Pipeline

WB I1 I2 I3 I3 I4
EX I1 I 2 I2 I3 I3 I3 I4 I4
ID I1 I 1 I2 I2 I 3 – I4 I4 I4
IF I 1 I2 – I3 I3 I 4 –
1 2 3 4 5 6 7 8 9 10 11 12 13
Number of Clock Cycles

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22. (d)

IF ID OF PD and WB

I1 : 1 memory reference 2 memory reference 1 memory reference —

I2 : 1 memory reference 3 memory reference 2 memory reference —

I3 : 1 memory reference 1 memory reference — 1 ALU operation

I4 : 1 memory reference 3 memory reference 2 memory reference —

I5 : 1 memory reference — — 1 ALU operation

Total Execution Time = (Number of memory reference × 3 cycles + Number of ALU

operation × 1 cycles) × cycle time
1 59
= (19 × 3 + 2 × 1) × = ns = 11.8 ns
5 GHz 5
23. (b)
The required probability = 10C (0.35)3 (0.65)7 = 0.252
3

24. (b)
16 MB
Time taken by I/O device = = 128sec
128 kB
128
Percentage time CPU is busy = × 100 = 82.05
128 + 28
25. (d)
(i) is true, it is logically done.
(ii) is false, structural dependency resolved using re-naming.
(iii) Delayed branch re-arranges code to reduce control dependency.

26. (d)
10001110
10000000
Sum = 100001110
Z = 0, C = 1, O =1, S = 0

27. (b)
4 3 4 3
op code Source data Destination

Mode R Mode R
Register = 5 = 3 bits
Modes = 14 =4 bits
Type Single operand or No operand Double operand
Arithmetic (10) 2 8
Logic (15) 9 6
Data moving (20) 12 8
Branch (10) 5 5
Total 27 double operands = 5 bits
Size of instruction word = 5 + 7 + 7 = 19

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28. (b)
The device generates 8 × 1024 = 8192 bytes/sec
i.e. 1 second 8192 bytes
1
for 1 byte ⇒ sec
8192
⇒ 122 µs
Given that each interrupt consumes 100 µs.
100
∴ Fraction of processor time consumed in = (for every byte) = 0.82
122
29. (a)
3 memory reference → 1 instruction
900 memory reference → ? instruction
900
Number of instruction = = 300
3
 Number of miss L1 
Number of memory stalls/instruction =  × Hit L2 
 Number of instruction 
 Number of miss L2 
+ × Miss panelty L2 
 Number of instruction 
 200   80 
=  × 100  +  × 300 
 300   300 
 200 
=  + 80   146.66 cycles
 3 

30. (c)
µ-instruction format:

µ-operation Condition Branch Address

F1 F2 F3 4 bits log2(4) log2(128)

2 bits 7 bits
log2(7) log2(7) log2(7)
3 bits 3 bits 3 bits

Size of one micro-instruction = (3 + 3 + 3) + 4 + 2 + 7 = 22 bits

So, option (c) is correct answer.

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