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Introduction

This document discusses test data compression techniques for integrated circuits. It introduces linear compression schemes that use a linear decompressor to decompress test vectors. These schemes exploit unspecified bits in test cubes to achieve compression by representing test cubes as vectors generated from a linear decompressor using fewer bits than the number of scan cells. The document proposes a technique to modify the output space of a linear decompressor to allow fewer free variables while still representing all test cubes, improving compression ratios.

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72 views3 pages

Introduction

This document discusses test data compression techniques for integrated circuits. It introduces linear compression schemes that use a linear decompressor to decompress test vectors. These schemes exploit unspecified bits in test cubes to achieve compression by representing test cubes as vectors generated from a linear decompressor using fewer bits than the number of scan cells. The document proposes a technique to modify the output space of a linear decompressor to allow fewer free variables while still representing all test cubes, improving compression ratios.

Uploaded by

api-3852471
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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INTRODUCTION

WITH integrated circuits, especially system-on-chip (SoC) designs,


becoming increasingly complex with each generation, the amount of test
data required to achieve acceptable test quality is becoming very large.
Hence, the test data storage requirements on an external tester and the test
data bandwidth requirements between the tester and chip are growing
rapidly. Test data compression techniques provide a means to reduce these
requirements thereby allowing less expensive testers to be used as well as
reducing the test time. Compressing the output response is relatively easy
since lossy compression techniques can be employed, e.g., using a multiple-
input signature register (MISR). However, compressing test vectors is much
more difficult because lossless compression techniques must be used.
Recently, as reducing test vector volume has become such an important
problem, a significant amount of research has been done on lossless
compression techniques for test vectors.

An important class of test vector compression schemes involve a


decompressor which uses only linear operations to decompress the test
vectors. This class, which will be henceforth referred to as linear
compression schemes, uses a linear decompressor. A number of different
techniques for designing linear decompressors have been proposed in the
literature. These include techniques based on linear feedback shift register
(LFSR) reseeding and combinational linear expansion circuits consisting of
XOR gates. Linear compression exploits the unspecified (don’t care) bit
positions in test cubes (i.e., deterministic test vectors where the unassigned
bit positions are left as don’t cares) to achieve large amounts of
compression.

The idea of using an LFSR as a linear decompressor and solving for test
cubes using linear algebra was described . Linear decompressors that can
receive data from the tester in a continuous-flow (i.e., “streaming” data) are
especially useful for test data compression. Continuous-flow linear
decompressors can be directly connected to the tester and operate very
efficiently since they simply receive the data as fast as the tester can transfer
it. From a tool integration standpoint, this is very nice since it mimics the
standard behavior of normal scan chains. There is no need for any special
scheduling or synchronization. Most of the commercial tools for
compressing test vectors are based on linear decompressors.
If there are c scan cells, then the space of all possible scan vectorsis
c
2 . The output space of a linear decompressor is the set of scan vectors that
can be generated by the linear decompressor. Each bit stored on the tester
can be thought of as a “free-variable” that can be assigned any value (0 or
1). Consider the case where the linear decompressor receives an input
sequence from the tester consisting of -free-variables when generating a scan
vector. Assuming the linear decompressor is always initialized to the same
state before generating each scan. The output space will be equal to 2n if
every input sequence maps to a unique scan vector, and less than 2n if some
input sequences map to the same scan vector. In the degenerate case where
the linear decompressor is just a set of wires directly connecting each scan
chain to a tester channel, then n = c and the content of every scan cell is
equal to a unique free variable such that the output space of the linear
decompressor contains all possible scan vectors. However, in order to get
compression, n needs to be less than c , and thus, in the general case, the
output space of the linear decompressor will be a subset of all possible scan
vectors.

In order to be able to compress a test set, the output space of any


decompressor must contain all the test cubes in the test set. Linear
decompressors have some advantages compared with nonlinear
decompressors. They generally have a larger output space for the same n
because of the use of XOR gates which tend to minimize the number of
input sequences that map to the same scan vector. Another useful property is
that the output space of a linear decompressor is a linear subspace spanned
by a Boolean matrix A. The advantage of having the output space be defined
by A is that determining whether a particular test cube is contained in the
output space and the corresponding input sequence to generate it can be
done by solving a set of linear equations using Gaussian elimination.

When using an LFSR as a linear decompressor, it has been shown that


if the number of free-variables used to generate a test cube is 20 more than
the number of specified bits in a test cube, then the probability of the test
cube not being in the output space is less than one in a million. However, for
a given test set, the number of free-variables can be reduced further provided
the corresponding reduced output space still contains all the test cubes in the
test set. Reducing the number of free-variables decreases the amount of
storage required on the tester and, hence, increases the compression. As the
number of free-variables are reduced, the output space becomes smaller and
smaller until a point is reached where one or more test cubes are no longer in
the output space. This point terminates the reduction in free-variables and
limits the compression that can be achieved by the linear compression
scheme for a particular test set.

This project describes a technique to alter and reshape the output space of a
linear decompressor, which will allow the number of free-variables to be
reduced further while still keeping all the test cubes in the output space
thereby increasing the compression. Any method for designing a linear
decompressor can be used first to obtain the best linear Decompressor that it
can. Using that linear decompressor as a starting point, the proposed
techniques reduce the number of free-variables further to improve the
compression.

Reconfiguration of a Decompressor modifies the output space of the


decompressor resulting in higher compression. This technique can be used in
SoC designs that have intellectual property (IP) cores where the core
internals are not visible. Further, in multicore SoCs, a single
“reconfigurable” decompressor can be used for several cores instead of
having several decompressors thereby providing a significant reduction in
hardware overhead.

Note that the techniques described in this paper can be used


in conjunction with any linear decompressor including all of the
1. Combinational linear decompressor.
2. XOR network and matrix
ones previously referenced to improve the compression further. They
transform the output space of the linear decompressor in a way that allows a
smaller number of free-variables from the tester to be used to encode the test
set.

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