DFT SCAN COMPRESSION

ASSIGNMENT
SUBMITTED BY:-SHASHANKA K M

JANUARY 14, 2021

HP
 1) What is Scan compression?
ANS:-
Scan compression is the most commonly used design-for-test (DFT) architecture for
reducing ATPG test application time and test data volume.When the scan chains are
properly balanced, you can reduce test time and test data volume close to the target
ratio.

2) What are the inputs and outputs of Scan compression?

ANS:-
Output files
write design my gate scan.v Verilog -replace
write atpg_setup my atpg -replace
EDT inserted synthesis netlist
Following outputs from Tessent Scan:

• Scan-inserted gate-level netlist of the design

• Test procedure file that describes how to operate the scan chains
• Dofile that contains the circuit setup and test structure information
Input files

• Skeleton design netlist

• Dofile
• Test procedure file
• Tessent cell library
• Scan inserted gated Verilog file

3) What is Compression Ratio, Test time, test data volume? Calculate

Compression Ratio, Test Time, Maximum Chain Length (MCL), and Test
Data Volume For Following Given Data: Pattern count 2000
● Internal Core Scan Chains 20
● External EDT Input Channels 4
● Test Clock Frequency 25 MHz
● Total Number Of SCAN Flip-Flop In Core Design 200,000.
ANS:-
 4) Draw the EDT architecture and Explain It neatly?
ANS:-

Embedded Deterministic Testing (EDT) is the technology used by Tessent TestKompress. EDT
technology is based on traditional, deterministic ATPG and uses the same fault models to
obtain similar test coverage using a familiar flow EDT extends ATPG with improved
compression of scan test data and a reduction in test time, Tessent TestKompress achieves
compression of scan test data by controlling a large number of internal scan chains using a
small number of scan channels. Scan channels can be thought of as virtual scan chains because
they operate the same as traditional scan chains from the tester's point of view.
The EDT technology consists of logic embedded on a chip and a new deterministic test pattern
generation technique.
An on-chip decompressor is located between the external scan channel inputs and the
internal scan chain inputs. An on-chip selective compactor is inserted between the internal
scan chain outputs and the external scan channel outputs. Optionally, the EDT architecture
may also include logic to bypass the decompressor and the compactor, thereby making the
internal scan chains directly accessible from the ATE.
The ratio of internal scan chains to tester scan channels usually sets the maximum
compression level.
Decompressor structure Since the decompressor plays a crucial role in determining the
effectiveness of EDT test data compression, it has to satisfy several requirements, including
•very low linear dependency in its outputs
• very high speed of operation
• very low silicon area
• high modularity of the design
Although it is possible to build a decompressor based on LFSRs or CAs, a completely new and
original architecture, called a ring generator, was developed for this application. A ring
generator is a distinct form of a linear finite state machine and, to perform on-chip
decompression, it is further connected to a linear phase shifter. The phase shifter is necessary
to drive a relatively large number of scan chains and reduce linear dependencies between
sequences entering the scan chains. In addition, the phase shifter is designed to guarantee a
balanced usage of all memory elements in the ring generator, and it introduces a minimal
propagation delay between the outputs of the ring generator and the serial inputs of the scan chains.

Ring generator. An example 32-bit ring generator implementing the primitive polynomial
x 32 + x 18 + x 14 + x 9 + 1 It has been obtained by applying a number of m-sequence preserving
transformations to the canonical form of type I LFSR featuring the same feedback polynomial.
Details of the ring generator synthesis process can be found in [18]. The proposed structure
has three main benefits as compared with conventional LFSRs or CAs. First, the propagation
delay introduced by the feedback logic is significantly reduced. In fact, in the worst case, only
one 2-input XOR gate is placed between any pair of memory elements. Second, the maximum
internal fan-out is limited to only two devices fed by any stem in the ring generator.
Furthermore, the total length of feedback lines is drastically reduced. The circuit in Fig. 4, for
instance, features only three very short connections. In general, a typical ring generator has
fewer levels of logic than a corresponding type I LFSR and a smaller fan-out than the original
type II LFSR. Hence, it can operate at higher speeds than those of conventional solutions and
is the layout- and timing-friendly. It is, therefore, well-positioned to achieve higher
performance than any other pseudorandom test pattern generator used so far.

Injectors. The compressed test data are provided to the decompressor through input
channels connected to taps of the ring generator by means of additional XOR gates placed
between the memory elements. Those connections are referred to as injectors. In fact, each
input channel is usually split into a number of internal injectors providing the same test data
to several memory elements at the same time. For instance, four external channels feed the
ring generator of each having two injectors. Although there are several schemes that can be
employed to configure injectors, the pattern shown in appears to assure the best
performance of the whole decompressor. Due to this arrangement, test data can be quickly
distributed to the entire ring generator.

Phase shifter. The linear phase shifter, which is added to the outputs of the ring generator
memory elements in the form of an XOR network, allows the ring generator to mutually
displace the produced sequences in various scan paths. As demonstrated in given any linear
finite state machine with a phase shifter, the probabilities of linear dependency in multiple
scans are virtually equal to the theoretical bounds presented once the interchain separation
reaches the length of the scan chains. The EDT phase shifter is made of XOR gates with a
limited number of inputs (called XOR taps) to reduce propagation delays. In this class of
circuits, the effective inter-chain separation is much larger than the required one. As a result,
the probabilities of linear dependency become practically independent of the minimal
required separation; they closely follow the limiting bounds and allow one to maximize the
likelihood of compression of test patterns. All results presented in this paper were obtained
assuming that the number of XOR taps is equal to 3.

Decompression. The decompressor consists of a ring generator, which is basically a Ring

LFSR with external inputs as shown in Figure 3. The external inputs feeding the ring generator are
commonly referred as EDT channels. The outputs of the ring generator flops will connect to scan chain
inputs through a phase shifter consisting of XOR gates. As discussed earlier, phase shifter helps
supporting more scan chains than the degree of LFSR. Creation of the compressed pattern from the
original ATPG test pattern consists of solving a set of linear equations based on the ring generator
polynomial and the phase shifter connections. Inputs to the ring generator are driven from the
compressed pattern stored on the ATE.

Compactor
Basically, there are two types of Test Response compactors –
1. Spatial compactor [reduces the number of output pins compared to input pins]
2. Time compactor [reduces the length of the output bit stream compared to the length of
input bit stream]

EDT uses the spatial compactor which consists of group of XOR trees. It allows multiple scan
chains to be observed at the same time on a given scan output channel. Several scan chains
are XOR-combined into individual scan channels.
But there are two problems that we may encounter –
a. ‘X’ contamination due to unknown value propagation
Scan cells can capture unknown or’X’ values from black boxes, non-scan cells, false paths,
etc. Let’s assume we have two scan chains that are compacted into one scan channel using
one XOR gate, as shown below. An X captured in one of the chains will then block the
corresponding cell in another chain, resulting in loss of observability.
b. Fault Aliasing due to bad Probability of Aliasing (PAL)
A fault is aliased when it is observed by an even number of scan cells that happened to line
up at the same location in different scan chains that are compacted to the same output
channel. The example shown below here illustrates this case. For this unique scenario, it is
not possible to see the difference between a good and faulted circuit.
Selective compaction of test responses Undoubtedly, MISRs are the most popular test
response compaction devices used in a parallel scan chain environment. However, they do
not handle unknown states and provide only limited support for fault diagnosis, even if they
are reset for every test pattern. Therefore, the EDT compaction scheme is designed in a
distinct manner so that it does not compromise test coverage [. In particular, it provides the
ability to:
• handle X states propagating to scan cells
• eliminate aliasing effects completely
• support diagnosis.
As the scheme comprises a number of linear spatial compactors driven by outputs of
selected scan chains. The spatial compactors are used to reduce the outputs of multiple scan
chains into a significantly smaller number of test data outputs which is equal to the number
of scan channel inputs. The scan chains are partitioned into multiple groups where each
group is connected to a separate spatial compactor feeding an output scan channel. It is
worth noting that while spatial compactors are essentially XOR trees, they are not
necessarily combinational circuits. If the propagation delay through the XOR tree becomes
unacceptable with respect to the shift frequency, the XOR tree can be pipelined to allow
faster operation.

Scan chain masking. A prominent feature of the EDT test response compaction is its
ability to selectively mask scan chains to protect the captured fault effects. Masking test data
stored in a scan chain before it is unloaded through the spatial compactor consists of adding
logic between the output of the scan chain and the compactor. This logic may force one or
more scan chain outputs to 0 before going into the compactor. Consequently, it allows
detecting faults even when they are captured on positions (scan cells) for which there exists
at least one corresponding counterpart in another scan chain that captures an unknown
state (X). Indeed, the fault effect will remain visible as it is XOR-ed with the logic value of 0
instead of X.

Aliasing. A similar technique is used to handle those faults that would escape detection
due to a phenomenon known as aliasing. It occurs when the fault effects appear only on
corresponding positions in an even number of scan chains and therefore they are XOR-ed in
the spatial compactor at the same time. In this scenario, aliasing effects are completely
eliminated by masking test data in certain scan chains in such a way that an odd number of
fault effects enter the compactor.

Conclusion. The test data volume increases exponentially with increase in circuit size. For large
circuits, the growing test data volume causes a significant increase in test cost because of much
longer test time and elevated tester memory requirements to store the test data. Therefore test
compression techniques are essential to reduce the test cost by reducing the Scan patterns while
trying to keep the same test quality. One of the most common hardware test compression technique
is EDT. Tessent TestKompress is the tool that can generate the decompressor and compactor logic at
the RTL level.
5) Explain masking and types of masking in Detail?
ANS:-
Why Masking is Needed

To facilitate compression, the tool inserts a compactor between the scan chain outputs and the scan
channel outputs. In this circuitry, one or more stages of XOR gates compact the response from several
chains into each channel output. Scan chains compacted into the same scan channel are said to be
in the same compactor group. One common problem with different compactor strategies is the
handling of Xs (unknown values). Scan cells can capture X values from unmodeled blocks, memories,
non-scan cells, and so forth Assume two scan chains are compacted into one channel. An X captured
in Chain I will then block the corresponding cell in Chain 2. If this X occurs in Chain I for all patterns,
the value in the corresponding cell in Chain 2 will never be measured.

The tool records an X in the pattern file in every position made unmeasurable as a result of the actual
occurrence of an X in the corresponding cell of a different scan chain in the same compactor group.
This is referred to as X blocking The capture data for Chain I and Chain 2 that you would see in the
ASCII pattern file for this example would look similar .

TYPES OF MASKING:-

Resolving X Blocking with Scan Chain Masking The solution to this problem is a mechanism utilized
in the EDT logic called "scan chain masking. This mechanism allows the selection of individual scan
chains on a per-pattern basis. Two types of scan chain masking are used:

1-hot masking
flexible masking
1-hot masking, only one chain is observed via each scan channel's compaction network. All the other
chains in that compactor are masked so they produce a constant 0 to the input of the compactor.
This allows observation of fault effects for the observed chains even if there are Xs in the observation
cycles for the other chains, 1-hot masking patterns are only generated for a few ATPG cycles at points
when the non-masking and flexible masking algorithms fail to detect any significant number of faults.

Flexible masking patterns allow multiple chains to be observed via each scan channel's compaction
network. Flexible masking is not fully non-masking, with fully nonmasking patterns, none of the
chains are masked so Xs in some cycles of some chains can block the observation of the fault effects
in some other chain. The Xpress compactor observes all chains with known values and masks out
those scan chains that contain X values so they do not block observation of other chains. With Xpress
flexible masking, only a subset of the chains is masked to maximize the fault detection profile while
reducing the impact on pattern count. When a fault effect cannot be observed at the channel output
under any of the flexible masking configurations, the tool uses 1-hot masking to guarantee the
detection of such faults.

6) What is Fault Aliasing? How Fault Aliasing is Avoided in EDT Compression

Technique
ANS:-
Fault Aliasing
Another potential issue with the compactor used in the EDT logic is called fault aliasing Assume one
fault is observed by two scan cells, and that these scan cells are located in two scant chains that are
compacted to the same scan channel. Further, assume that these cells are in the same locations
(columns) in the two chains and neither chain is masked.

Assume that the good value for a certain pattern is an I in the two scan cells. This corresponds to a 0
measured on the scan channel output, due to the XOR in the compactor. If a fault occurs on this site,
Os are measured in the scan cells, which also results in a 0 on the scan channel output. For this unique
scenario, it is not possible to see the difference between a good and a faulty circuit.

A fault is aliased when it is observed by an even number of scan cells that happened to line up at the
same location in different scan chains that are compacted to the same output channel. The example
 shown below here illustrates this case. For this unique scenario, it is not possible to see the difference
between a good and faulted circuit.

7) What are the needs, advantages and Disadvantages of Compression

technique?
ANS:-
• Maintain high test quality
• Easily fit into the design
• Add minimal test logic
• Achieve high test compression both test time and test data
• No impact on the functional design

Disadvantages:-

• It requires external pins to perform compression

• Area overhead
• High power requirement
• Requires additional shift cycles
• it is very hard to find which part is faulty since the signature is not compared for every
pattern. So it is not desirable to multi-core or multi-module chips. In multi-module chips if a
fault is detected in a single module then it can be used with less functionality, therefore MISR
Compactor is not suited for such configurations

Advantages:-

• test time reduction

• lesser pattern count

8) For a number of flops=100k, external channels=4, internal chains=40, no of

patterns=5000, frequency= 100Mhz. Calculate compression ratio, Test time,
maximum chain length?
ANS:-
9) What is the difference between Compression mode and Bypass mode?
ANS:-
• compression of scan test data by controlling a large number of internal scan chains using a
small number of scan channels.
 • Bypasses the EDT logic by using multiplexers (and lockup cells if necessary) to
concatenate the internal scan chains into fewer, longer chains. Enables you to access
the internal scan chains directly through the channel pins. Generated by default.
• compression bypass scan patterns that allow full debug capability at the expense of
simulation time.
• Compression verifies the compressed patterns in simulation without debugging
possibility
• The standard approach for debugging the shift phase of scan patterns is to focus first
on a bypass one. The reason for it is coming from the fact that only bypass patterns
are transiting as it along the scan chain, meaning that a data shift from a scan input
can be easily followed flip-flop after flip-flop until the data is going out of the design
through a scan output. When you have validated that the bypass shift is working as
expected, you can move to compression bypass capture simulation and other scan
modes (compressed) simulation. All those simulations are performed in serial mode;
most of the patterns are then simulated in parallel mode since only the capture phase
is then to verify.

10) Explain Xpress and Basic Type Compactor With a neat Diagram?
ANS: -
• The basic compactor consists of the decoder and in Xpress compactor consists of a
basic decoder and Xor decoder.
• In basic decoder only one scan chain is masked in order to prevent the X values coming
from nonscan cells or hard macros. In the Xpress compactor, the Xor decoder is used in order
to mask multiple chains and prevent the X values from coming in. In the Xpress compactor,
Mask shift registers are pretended with input channels.
• If the design complexity is more(more number of X propagations) we can use Xpress
compactor, if the design complexity is small (Less number of X propagations )we can use a
Basic compactor.
BASIC COMPACTOR: A mask code (pretended with a decoder mode bit) is generated with
each test pattern to determine which scan chains are masked or observed.
• The basic compactor determines which chains to observe or mask using the mask
code as follows,
• The decompressor loads the mask code into the mask shift register
• The mask code is parallel-loaded into the mask hold register, where the decoder mode
bit determines the observe mode: either one scan chain or all scan chains.
• The mask code in the mask hold register is decoded and each bit drives one input of
a masking AND gate in the compactor. Depending on the observe mode, the output of these
AND gates is either enabled or disabled
 Xpress Compactor OPERATION

A mask code (prepended with a decoder mode bit) is generated with each test pattern
to determine which scan chains are masked or observed. The Xpress compactor
determines which chains to observe or mask using the mask code as follows:
• Each test pattern is loaded into the decompressor through a mask shift register on
the input channel.
• The mask code is appended to each test pattern and remains in the mask shift
register once the test pattern is completely loaded into the decompressor.
• The mask code is then parallel-loaded into the mask hold register, where the
decoder mode bit determines whether the basic decoder or the XOR decoder i used on
the mask code.
❖ The basic decoder selects only one scan chain per compactor. The basic decoder is selected
when there is a very high rate of X values during scan testing or during chain test to allow
failing chains to be fully observed and easy to diagnose.

❖ The XOR decoder masks or observes multiple scan chains per compactor, depending on the
mask code. For example, if the mask code is all 1s, then all the scan chains are observed.

❖ The decoder output is shifted through a multiplexer, and each bit drives one input on the
masking AND gates in the compactor to either disable or enable the output, depending on
the decoder mode and bit value.
11) Draw the waveform of EDT and Explain the Need of all essential EDT
Signals?
ANS:-
 • Prior to each scan load, the EDT logic needs to be reset. This is done by pulsing the EDTclock
once while the EDT update is high
• During shifting, the EDT clock should be pulsed together with the scan clock(s).
• Both scans enable and EDT update is shown as 0 during the capture cycle. These two signals
can have any value during capture; they do not have to be constrained.
• On the other hand, the EDT clock must be 0 during the capture cycle.

The pin edt_updateis used to reset/update two sets of registers:

ring generator registers in the decompressor logic
mask hold registers in the compactor logic
During the load, procedure edt_updateis activated. This causes the following:
ring generator registers become 0
mask_hold_registeris loaded with value in the mask_shift_register

This is needed because:

ring generator needs a predictable state before generating random values, in this case, all0
is the predictable state.
mask_hold_registeris designed to do per pattern masking. Each pattern has a specific
masking sequence.

EDT_Clock
The default EDT logic contains combinational logic and flip-flops. All the flip-flops, except
lockup cells, are positive edge-triggered and clocked by a dedicated clock signal that is
different from the scan clock.
There is no clock gating within the EDT logic, so it does not interfere with the system clock(s)
Set up the clock to be a dedicated pin (named edt_clock by default) or share the clock with a
functional non-clock pin. Such sharing may cause a decrease in test coverage Because the tool
constrains the clock pin during test pattern generation.
12) Write and Explain all By Using TESTKOMPRESS tool Commands to perform
Single Configuration Compression On SCAN Design ( Note: write command for
External Flow only).
ANS:-
To Set the context to Scan compression
Setup>set context dft -edt

To Read the scan inserted netlist and Library

Setup>read_verilog div_scan_10.vg

Setup>read_cell_library adk. Tcelllib

To set the top module of the design

Setup>set current design div_1

To check the clocks and other pin details and automatically control the
operation of the tool & it contains necessary information about the next step
Setup>dofile div scan 10.dofile

Invoking the tessent tool it will check the all the files are ready
Setup>tessent_scan_setup

Scan compression configuration

Setup>set_edt_options -input_channels 2

Setup>set_edt_options -output _channels2

it will check for drc and any voilations

Setup>check_design_rules

Generate EDT reports

Analysis>write_edt files div 1

Analysis>report_scan_cells

Analysis>report_scan chains

Analysis>report_edt pins

Analysis>report_edt pins > edt pins_info.rpt.

Analysis>report_edt_configurations

Analysis>report_edt configurations > edt_config.rpt

Analysis>Exit

specify The Context

Setup>set_context dft -edt

Read Top Level Edt Wrapper Netlist.

Setup>read verilog div_1_edt_top.v

Read EDT Inserted Netlist (RTL or Gate Level).

Setup>read verilog div_1_edt.v

Read SCAN Inserted Gate Level Netlist.

Setup>read_verilog div_scan_10.vg

Read Tessent shall compitable Libraries

Setup>read_cell_library adk.tcelllib

Specify Top Module Name For EDT Wrapper Netlist and Elaborate The Design.
Setup>set current design div_1_edt_top

Open-Test Compress Toul In Graphical User Interface (GUI Mode).

Setup>open visualizer

13) Write Dual Configuration SCAN Compression Commands For External Flow
and Explain Each Command Neatly?
ANS:-
To Set the context to Scan compression
Setup>set context dft -edt

To Read the scan inserted netlist and Library

Setup>read_verilog div_scan_10.vg

Setup>read_cell_library adk. Tcelllib

To set the top module of the design

Setup>set current design div_1

To check the clocks and other pin details and automatically control the
operation of the tool & it contains necessary information about the next step
Setup>dofile div scan 10.dofile

Invoking the tessent tool it will check the all the files are ready
Setup>tessent_scan_setup

Scan compression configuaration

Setup>add_edt_configurations config1

Setup>set_edt_options -input_channels 2

Setup>set_edt_options -output channels 2

it will check for drc and any voilations

Setup>check_design_rules

Verify the EDT configuration as expected it lists the details including the of scan
channels and logic version
Analysis>report_edt_configurations

Analysis>report_edt_configurations> edt_config1.rpt

Analysis>set system_mode setup

Setup>add_edt_configurations config2

Setup>set_edt_options -channels 5

Setup>Check_design_rules

Analysis>report_edt_configurations

Analysis>report_edt_configurations edt_config2.rpt

Generate EDT reports

Analysis>write_edt files div 1

Analysis>report_scan_cells

Analysis>report_scan chains

Analysis>report_edt pins

Analysis>report_edt pins > edt pins_info.rpt.

Analysis>report_edt_configurations

Analysis>report_edt configurations > edt_config.rpt

Analysis>Exit

specify The Context

Setup>set_context dft -edt

Read Top Level Edt Wrapper Netlist.

Setup>read verilog div_1_edt_top.v
Read EDT Inserted Netlist (RTL or Gate Level).
Setup>read verilog div_1_edt.v

Read SCAN Inserted Gate Level Netlist.

Setup>read_verilog div_scan_10.vg

Read Tessent shall compitable Libraries

Setup>read_cell_library adk.tcelllib

Specify Top Module Name For EDT Wrapper Netlist and Elaborate The Design.
Setup>set current design div_1_edt_top

Open-Test Compress Toul In Graphical User Interface (GUI Mode).

Setup>open visualizer

14) Draw Individual Fixing Diagram For Following SCAN DRC? ( Note: Do not
Draw Entire Fixing Diagrams on one sheet, Draw Individual By Giving DRC issue
No. With its Solution Diagram).
ANS:-
15) Explain following all DRC in detail, which is inside the following
diagram and draw its solutions ? (note clock off value is logic 0). (2.5M)
1. Identify the no of DRC and fix it with diagrams
2. Create necessary scannable port for the design
3. Convert normal flop to scannable flop
4. Stitch all scannable flop into single chain
5. Explain any one fix using commands.
ANS:-