EE-122 Spring 2024

Computer Architecture and Logic Design

Lecture # 02
Sequential Logic Circuits and Design

Muhammad Imran
Acknowledgement
2

▪ These lectures notes are based on

▪ Digital System Design and Computer Architecture (Course)
▪ By Prof. Onur Mutlu, ETH Zurich
Contents
3

▪ Basics of Memory and Storage Elements

▪ Sequential Logic Circuits
▪ Finite State Machines
Sequential Logic Circuits and Design
No Real Computer Can Work w/o Memory
5

Apple M1,
2021

Source: https://www.anandtech.com/show/16252/mac-mini-apple-m1-tested
A Large Fraction of Modern Systems is Memory
6

A lot of
Storage DRAM SRAM DRAM Storage

Apple M1 Ultra System (2022)

https://www.gsmarena.com/apple_announces_m1_ultra_with_20core_cpu_and_64core_gpu-news-53481.php
A Large Fraction of Modern Systems is
Memory
7

Processor chip Level 2 cache chip

Multi-chip module package

Intel Pentium Pro, 1995

By Moshen - http://en.wikipedia.org/wiki/Image:Pentiumpro_moshen.jpg, CC BY-SA 2.5, https://commons.wikimedia.org/w/index.php?curid=2262471
 A Large Fraction of Modern Systems is
Memory
8
L2 Cache

https://download.intel.com/newsroom/kits/40thanniversary/gallery/images/Pentium_4_6xx-die.jpg
Intel Pentium 4, 2000
Circuits that Can Store Information
Introduction
10

▪ Combinational circuit output depends only on current input

▪ We want circuits that produce output depending on current and past
input values – circuits with memory
▪ How can we design a circuit that stores information?

Sequential Circuit

outputs
inputs

Combinational
Circuit

Storage
Element
Capturing Data
 Basic Element: Cross-Coupled Inverters
12

▪ Has two stable states: Q=1 or Q=0.

▪ Has a third possible “metastable” state with both outputs oscillating
between 0 and 1 (we will see this later)
▪ Not useful without a control mechanism for setting Q

Image source: Harris and Harris, Digital Design and Computer Architecture, 2nd Ed., p.110.
More Realistic Storage Elements
13

▪ Have a control mechanism for setting Q

▪ We will see the R-S latch soon
▪ Let’s look at an SRAM (static random access memory) cell first

bitline bitline
wordline

SRAM cell
The Big Picture: Storage Elements
14

▪ Latches and Flip-Flops

▪ Very fast, parallel access
▪ Very expensive (one bit costs tens of transistors)

▪ Static RAM (SRAM)

▪ Relatively fast
▪ Expensive (one bit costs 6+ transistors)

▪ Dynamic RAM (DRAM)

▪ Slower, reading destroys content (refresh), needs special process for
manufacturing
▪ Cheap (one bit costs only one transistor plus one capacitor)

▪ Other storage technology (flash memory, hard disk, tape)

▪ Much slower, access takes a long time, non-volatile
▪ Very cheap
Basic Storage Element: The R-S Latch
The R-S (Reset-Set) Latch
16

▪ Cross-coupled NAND gates

▪ Data is stored at Q (inverse at Q’)
▪ S and R are control inputs
▪ In quiescent (idle) state, both S and R are held at 1
▪ S (set): drive S to 0 (keeping R at 1) to change Q to 1
▪ R (reset): drive R to 0 (keeping S at 1) to change Q to 0

▪ S and R should never both be 0 at the same time

S Q Input Output
R S Q
1 1 Qprev
1 0 1
0 1 0
R Q’ 0 0 Forbidden
Why not R=S=0?
17

1. If R=S=0, Q and Q’ will both settle to 1, which breaks our invariant

that Q = !Q’
2. If S and R transition back to 1 at the same time, Q and Q’ begin to
oscillate between 1 and 0 because their final values depend on
each other (metastability)
▪ This eventually settles depending on variation in the circuits!

S
1
0 Q Input Output

1
0 R S Q
1 1 Qprev
1 0 1
1
0 0 1 0
R Q’ 0 0 Forbidden
1
0
The Gated D Latch
The Gated D Latch
19

▪ How do we guarantee correct operation of an R-S Latch?

S Q

Q’
R
The Gated D Latch
20

▪ How do we guarantee correct operation of an R-S Latch?

▪ Add two more NAND gates!

D S Q

Write
Enable

Q’
R

▪ Q takes the value of D, when write enable (WE) is set to 1

▪ S and R can never be 0 at the same time!
The Gated D Latch
21

D S
Q

Write
Enable

Q’
R
Input Output
WE D Q
0 0 Qprev
0 1 Qprev
1 0 0
1 1 1
The Register
 The Register
23

How can we use D latches to store more data?

• Use more D latches!
• A single WE signal for all latches for
simultaneous writes Here we have a
register, or a
D3 D2 D1 D0
structure that
stores more than
Write
Enable
one bit and can be
read from and
written to

This register holds

4 bits, and its data
Q3 Q2 Q1 Q0 is referenced as
Q[3:0]
The Register
24

How can we use D latches to store more data?

• Use more D latches!
• A single WE signal for all latches for
simultaneous writes Here we have a
D3:0 register, or a
structure that
4 stores more than
one bit and can be
read from and
WE Register x (Rx) written to

This register holds

4 4 bits, and its data
Q3:0 is referenced as
Q[3:0]
Memory
Memory
26

▪ Memory is comprised of locations that can be written to or read

from. An example memory array with 4 locations:
Addr(00): 0100 1001 Addr(01): 0100 1011
Addr(10): 0010 0010 Addr(11): 1100 1001

▪ Every unique location in memory is indexed with a unique address.

4 locations require 2 address bits (log[#locations]).
▪ Addressability: the number of bits of information stored in each
location. This example: addressability is 8 bits.
▪ The entire set of unique locations in memory is referred to as the
address space.
▪ Typical memory is MUCH larger (e.g., billions of locations)
 Addressing Memory
27

Let’s implement a simple memory array with:

• 3-bit addressability & address space size of 2 (total of 6 bits)
1 Bit
D Q
WE

6-Bit Memory Array

Addr(0) Bit2 Bit1 Bit0

Addr(1) Bit2 Bit1 Bit0

Reading from Memory
28

How can we select an address to read?

• Because there are 2 addresses, address size is log(2)=1 bit
 Reading from Memory
29

How can we select an address to read?

• Because there are 2 addresses, address size is log(2)=1 bit
Addr[0]

Wordline

D[2] D[1] D[0]

 Reading from Memory
30

How can we select an address to read?

• Because there are 2 addresses, address size is log(2)=1 bit
Addr[0]

Wordline

Address Decoder

D[2] D[1] D[0]

 Reading from Memory
31

How can we select an address to read?

• Because there are 2 addresses, address size is log(2)=1 bit
Addr[0]

Wordline

Address Decoder

D[2] D[1] D[0]

Multiplexer
(together w/ decoder)
Recall: Multiplexer (MUX), or Selector
32

▪ Selects one of the N inputs to connect it to the output

▪ based on the value of a log2N-bit control input called select
▪ Example: 2-to-1 MUX
A B A B

S S=0

a b A 0

A
C C
Writing to Memory
33

How can we select an address and write to it?

 Writing to Memory
34

How can we select an address and write to it?

• Input is indicated with Di
Addr[0]
Di[2] Di[1] Di[0]
WE
 Putting it all Together
35

Let’s enable reading from and writing to a memory array

Addr[0]
Di[2] Di[1] Di[0]
WE

D[2] D[1] D[0]

 A Bigger Memory Array – (4 locations X 3 bits)
36

Addr[1:0]
Di[2] Di[1] Di[0]
WE

D[2] D[1] D[0]

 A Bigger Memory Array – (4 locations X 3 bits)
Addr[1:0]
37
Di[2] Di[1] Di[0]
WE

Address Decoder
Multiplexer D[2] D[1] D[0]
(together w/ decoder)
 Example: Reading Location 3
38

Image source: Patt and Patel, “Introduction to Computing Systems”, 3rd ed., page 78.
Recall: Decoder (II)
39

▪ The decoder is useful in determining how to interpret a bit pattern

❑ It could be the A=1

address of a location 0
B=0
in memory, that the
processor intends to
read from 0

❑ It could be an
instruction in the 1
program and the
processor needs to
decide what action to 0
take (based on
instruction opcode)
Recall: A 4-to-1 Multiplexer
40
Aside: Implementing Logic Functions Using Memory
 Recall: A Bigger Memory Array – (4 locations X 3 bits)
42

Addr[1:0]
Di[2] Di[1] Di[0]
WE

Address Decoder
Multiplexer
(together w/ decoder) D[2] D[1] D[0]
Memory-Based Lookup Table Example
43

▪ Memory arrays can also perform Boolean Logic functions

▪ 2N-location M-bit memory can perform any N-input, M-output function
▪ Lookup Table (LUT): Memory array used to perform logic functions
▪ Each address: row in truth table; each data bit: corresponding output
value
Lookup Tables (LUTs)
44

▪ LUTs are commonly used in FPGAs

▪ To enable programmable/reconfigurable logic functions
▪ To enable easy integration of combinational and sequential logic
 Recall: A Multiplexer-Based LUT
45

▪ Let’s implement a function that outputs ‘1’ when there are at least
two ‘1’s in a 3-bit input In Hardware (e.g., FPGA):
In C: Data Inputs
int count = 0; 000 0
for(int i = 0; i < 3; i++) { Configuration Memory
count += input & 1; 001 0
input = input >> 1;
} 010 0
if(count > 1) return 1; 011 1
output (1 bit)
return 0; 100 0
switch(input){ 101
case 0: 1
case 1:
case 2: 110 1
case 4:
return 0; 111 1
default:
return 1;} 3
input (3 bits)
Sequential Logic Circuits
Sequential Logic Circuits
47

▪ We have examined designs of circuit elements that can store

information
▪ Now, we will use these elements to build circuits that remember
past inputs

Combinational Sequential
Only depends on current inputs Opens depending on past inputs
https://www.easykeys.com/228_ESP_Combination_Lock.aspx
https://www.fosmon.com/product/tsa-approved-lock-4-dial-combo
State
48

▪ In order for this lock to work, it has to keep track (remember) of the
past events!
▪ If passcode is R13-L22-R3, sequence of states to unlock:
A. The lock is not open (locked), and no relevant operations have
been performed
B. Locked but user has completed R13
C. Locked but user has completed R13-L22
D. Unlocked: user has completed R13-L22-R3

▪ The state of a system is a snapshot of all relevant elements of the

system at the moment of the snapshot
▪ To open the lock, states A-D must be completed in order
▪ If anything else happens (e.g., L5), lock returns to state A
 State Diagram of Our Sequential Lock
49

▪ Completely describes the operation of the sequential lock

▪ We will understand “state diagrams” fully later today

Image source: Patt and Patel, “Introduction to Computing Systems”, 2nd ed., page 76.
Asynchronous vs. Synchronous State Changes
50

▪ Sequential lock we saw is an asynchronous “machine”

▪ State transitions occur when they occur
▪ There is nothing that synchronizes when each state transition must
occur

▪ Most modern computers are synchronous “machines”

▪ State transitions take place after fixed units of time
▪ Controlled in part by a clock, as we will see soon

▪ These are two different design paradigms, with tradeoffs

Another Simple Example of State
51

▪ A standard (Swiss) traffic light has 4 states

A. Green
B. Yellow
C. Red
D. Red and Yellow

▪ The sequence of these states are always as follows

A B C D
Changing State: The Notion of Clock (I)
52

▪ When should the light change from one state to another?

▪ We need a clock to dictate when to change state
▪ Clock signal alternates between 0 & 1

A B C D
1
CLK:
0
Changing State: The Notion of Clock (I)
53

▪ When should the light change from one state to another?

▪ We need a clock to dictate when to change state
▪ Clock signal alternates between 0 & 1

A B C D
1
CLK:
0

▪ At the start of a clock cycle ( ), system state changes

▪ During a clock cycle, the state stays constant
▪ In this traffic light example, we are assuming the traffic light
stays in each state an equal amount of time
Changing State: The Notion of Clock (II)
54

▪ Clock is a general mechanism that triggers transition from one state

to another in a (synchronous) sequential circuit

▪ Clock synchronizes state changes across many sequential circuit

elements

▪ Combinational logic evaluates for the length of the clock cycle

▪ Clock cycle should be chosen to accommodate maximum

combinational circuit delay
▪ More on this later, when we discuss timing
Asynchronous vs. Synchronous State Changes
55

▪ Sequential lock we saw is an asynchronous “machine”

▪ State transitions occur when they occur
▪ There is nothing that synchronizes when each state transition must
occur

▪ Most modern computers are synchronous “machines”

▪ State transitions take place after fixed units of time
▪ Controlled in part by a clock, as we will see soon

▪ These are two different design paradigms, with tradeoffs

▪ Synchronous control can be easier to get correct when the system
consists of many components and many states
▪ Asynchronous control can be more efficient (no clock overheads)

We will assume synchronous systems in most of this course

Finite State Machines
Finite State Machines
57

▪ What is a Finite State Machine (FSM)?

▪ A discrete-time model of a stateful system
▪ Each state represents a snapshot of the system at a given time

▪ An FSM pictorially shows

1. the set of all possible states that a system can be in
2. how the system transitions from one state to another

▪ An FSM can model

▪ A traffic light, an elevator, fan speed, a microprocessor, etc.

▪ An FSM enables us to pictorially think of a stateful system

using simple diagrams
Finite State Machines (FSMs) Consist of:
58

▪ Five elements:
1. A finite number of states
▪ State: snapshot of all relevant elements of the system at the
time of the snapshot
2. A finite number of external inputs
3. A finite number of external outputs
4. An explicit specification of all state transitions
▪ How to get from one state to another
5. An explicit specification of what determines each external
output value
Finite State Machines (FSMs)
59

▪ Each FSM consists of three separate parts:

▪ next state logic
▪ state register
▪ output logic

CLK
M next
next k state k state output N
inputs state outputs
logic
logic

state register

At the beginning of the clock cycle, next state is latched into the state register
Finite State Machines (FSMs) Consist of:
60

CLK
▪ Sequential Circuits
▪ State register(s)
S’ S
▪ Store the current state and
Next Current
▪ Load the next state at the clock edge State State

▪ Combinational Circuits Next State

▪ Next state logic Logic
▪ Determines what the next state will be
CL Next
State

▪ Output logic
▪ Generates the outputs Output
Logic

CL Outputs
Finite State Machines (FSMs) Consist of:
61

CLK
▪ Sequential Circuits
▪ State register(s)
S’ S
▪ Store the current state and
Next Current
▪ Provide the next state at the clock edge State State

▪ Combinational Circuits Next State

▪ Next state logic Logic
▪ Determines what the next state will be
CL Next
State

▪ Output logic
▪ Generates the outputs Output
Logic

CL Outputs
State Register Implementation
62

▪ How can we implement a state register? Two properties:

1. We need to store data at the beginning of every clock cycle

2. The data must be available during the entire clock cycle

1
CLK:
0

Register
Input:

Register Desired behavior

Output:
The Problem with Latches
63

Recall the D Q
Gated D Latch
CLK = WE

▪ Currently, we cannot simply wire a clock to WE of a latch

▪ Whenever the clock is high, the latch propagates D to Q
▪ The latch is transparent

1
CLK:
0

Register
Input:

Register
Output:
The Problem with Latches
64

Recall the D Q
Gated D Latch
CLK = WE

▪ Currently, we cannot simply wire a clock to WE of a latch

▪ Whenever the clock is high, the latch propagates D to Q
▪ The latch is transparent

1
CLK:
0

Register
Input:

Register
Output:
Undesirable!
The Problem with Latches
65

Recall the D Q
Gated D Latch
CLK = WE

How can we change the latch, so that

1
CLK:
0 1) D (input) is observable at Q (output)
only at the beginning of next clock cycle?
Input:
2) Q is available for the full clock cycle
Output:
The Need for a New Storage Element
66

▪ To design viable FSMs

▪ We need storage elements that allow us to:

▪ read the current state throughout the entire current clock cycle

AND

▪ not write the next state values into the storage elements until the
beginning of the next clock cycle
 The D Flip-Flop
67

▪ 1) state change on clock edge, 2) data available for full cycle

D Latch (First)
D D Latch (Second)

CLK
1
CLK:
0
◼ When the clock is low, 1st latch propagates D to the input of the 2nd (Q unchanged)
◼ Only when the clock is high, 2nd latch latches D (Q stores D)
❑ At the rising edge of clock (clock going from 0->1), Q gets assigned D
 The D Flip-Flop
68

▪ 1) state change on clock edge, 2) data available for full cycle

D CLK Q

__
Q
D Flip-Flop

1
CLK:
0

◼ At the rising edge of clock (clock going from 0->1), Q gets assigned D
◼ At all other times, Q is unchanged
 The D Flip-Flop
69

▪ 1) state change on clock edge, 2) data available for full cycle

D CLK Q

__
We can use D Flip-Flops
Q
to implement the state register
D Flip-Flop

1
CLK:
0

◼ At the rising edge of clock (clock going from 0->1), Q gets assigned D
◼ At all other times, Q is unchanged
Rising-Clock-Edge Triggered Flip-Flop
70

▪ Two inputs: CLK, D

D Flip-Flop
CLKSymbols
▪ Function
▪ The flip-flop “samples” D on the rising edge
D Q
of CLK (positive edge)
▪ When CLK rises from 0 to 1, D passes Q
through to Q
▪ Otherwise, Q holds its previous value
▪ Q changes only on the rising edge of CLK

▪ A flip-flop is called an edge-triggered state element because it

captures data on the clock edge
▪ A latch is a level-triggered state element
D Flip-Flop Based Register
71

▪ Multiple
CLK
parallel D flip-flops, each of which storing 1 bit

D0 D Q Q0

CLK
D1 D Q Q1
4 4
D3:0 Q3:0
D2 D Q Q2

This line represents 4 wires

D3 D Q Q3
This register stores 4 bits
 A 4-Bit D-Flip-Flop-Based Register (Internally)
72

Image source: Patt and Patel, “Introduction to Computing Systems”, 3rd ed., tentative page 95.
Finite State Machines (FSMs)
73

▪ Next state is determined by the current state and the inputs

▪ Two types of finite state machines differ in the output logic:
▪ Moore FSM: outputs depend only on the current state

Moore FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic

Mealy FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic
Finite State Machines (FSMs)
74

▪ Next state is determined by the current state and the inputs

▪ Two types of finite state machines differ in the output logic:
▪ Moore FSM: outputs depend only on the current state
▪ Mealy FSM: outputs depend on the current state and the inputs
Moore FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic

Mealy FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic
 Finite State Machine Example
75

▪ “Smart” traffic light controller

▪ 2 inputs:
▪ Traffic sensors: TA , TB (TRUE when there’s traffic)
▪ 2 outputs:
▪ Lights: LA , LB (Red, Yellow, Green)

Bravado
Dining
▪ State can change every 5 seconds Hall
▪ Except if green and traffic, stay green LB

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms

Blvd.
From H&H Section 3.4.1 Fields
Finite State Machine Black Box
76

▪ Inputs: CLK, Reset, TA , TB

▪ Outputs: LA , LB
CLK

TA Traffic LA
Light
TB Controller LB

Reset
 Finite State Machine Transition Diagram
77

▪ Moore FSM: outputs labeled in each state

▪ States: Circles
▪ Transitions: Arcs

Reset
Bravado

Dining S0
Hall LA: green
LB LB: red

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms
Blvd.

Fields
 Finite State Machine Transition Diagram
78

▪ Moore FSM: outputs labeled in each state

▪ States: Circles
▪ Transitions: Arcs
TA
Reset
Bravado

Dining S0 TA S1
Hall LA: green LA: yellow
LB LB: red LB: red

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms S3 S2
LA: red LA: red
LB: yellow LB: green
Blvd.

TB
Fields TB
 Finite State Machine Transition Diagram
79

▪ Moore FSM: outputs labeled in each state

▪ States: Circles
▪ Transitions: Arcs
TA
Reset
Bravado

Dining S0 TA S1
Hall LA: green LA: yellow
LB LB: red LB: red

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms S3 S2
LA: red LA: red
LB: yellow LB: green
Blvd.

TB
Fields TB
 Finite State Machine Transition Diagram
80

▪ Moore FSM: outputs labeled in each state

▪ States: Circles
▪ Transitions: Arcs
TA
Reset
Bravado

Dining S0 TA S1
Hall LA: green LA: yellow
LB LB: red LB: red

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms S3 S2
LA: red LA: red
LB: yellow LB: green
Blvd.

TB
Fields TB
 Finite State Machine Transition Diagram
81

▪ Moore FSM: outputs labeled in each state

▪ States: Circles
▪ Transitions: Arcs
TA
Reset
Bravado

Dining S0 TA S1
Hall LA: green LA: yellow
LB LB: red LB: red

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms S3 S2
LA: red LA: red
LB: yellow LB: green
Blvd.

TB
Fields TB
Finite State Machine:
State Transition Table
FSM State Transition Table
83

TA
Reset
S0 TA S1
LA: green LA: yellow
Current State Inputs Next State
LB: red LB: red
S TA TB S'
S0 0 X
S0 1 X
S1 X X
S2 X 0
S2 X 1 S3 S2
S3 X X LA: red LA: red
LB: yellow LB: green
TB
TB
FSM State Transition Table
84

TA
Reset
S0 TA S1
LA: green LA: yellow
Current State Inputs Next State
LB: red LB: red
S TA TB S'
S0 0 X S1
S0 1 X S0
S1 X X S2
S2 X 0 S3
S2 X 1 S2 S3 S2
S3 X X S0 LA: red LA: red
LB: yellow LB: green
TB
TB
FSM State Transition Table
85

TA
Reset
S0 TA S1
LA: green LA: yellow
Current State Inputs Next State
LB: red LB: red
S TA TB S'
S0 0 X S1
S0 1 X S0
S1 X X S2
S2 X 0 S3
S2 X 1 S2 S3 S2
S3 X X S0 LA: red LA: red
LB: yellow LB: green
State Encoding TB
S0 00 TB
S1 01
S2 10
S3 11
FSM State Transition Table
86

TA
Reset
S0 TA S1
Current State Inputs Next State
LA: green LA: yellow
S1 S0 TA TB S’1 S’0
LB: red LB: red
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1
1 0 X 1 1 0
S3 S2
1 1 X X 0 0
LA: red LA: red
LB: yellow LB: green
State Encoding TB
S0 00 TB
S1 01
S2 10
S3 11
FSM State Transition Table
87

TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red
Current State Inputs Next State
S1 S0 TA TB S’1 S’0
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1 S3 S2
1 0 X 1 1 0 LA: red LA: red
1 1 X X 0 0 LB: yellow LB: green
TB
TB

State Encoding
S’1 = ? S0 00
S1 01
S2 10
S3 11
FSM State Transition Table
88

TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red
Current State Inputs Next State
S1 S0 TA TB S’1 S’0
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1 S3 S2
1 0 X 1 1 0 LA: red LA: red
1 1 X X 0 0 LB: yellow LB: green
TB
TB

State Encoding
S’1 = (S1 ∙ S0) + (S1 ∙ S0 ∙ TB) + (S1 ∙ S0 ∙ TB) S0 00
S1 01
S2 10
S3 11
FSM State Transition Table
89

TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red
Current State Inputs Next State
S1 S0 TA TB S’1 S’0
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1 S3 S2
1 0 X 1 1 0 LA: red LA: red
1 1 X X 0 0 LB: yellow LB: green
TB
TB

State Encoding
S’1 = (S1 ∙ S0) + (S1 ∙ S0 ∙ TB) + (S1 ∙ S0 ∙ TB) S0 00
S1 01
S’0 = ? S2 10
S3 11
FSM State Transition Table
90

TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red
Current State Inputs Next State
S1 S0 TA TB S’1 S’0
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1 S3 S2
1 0 X 1 1 0 LA: red LA: red
1 1 X X 0 0 LB: yellow LB: green
TB
TB

State Encoding
S’1 = (S1 ∙ S0) + (S1 ∙ S0 ∙ TB) + (S1 ∙ S0 ∙ TB) S0 00
S1 01
S’0 = (S1 ∙ S0 ∙ TA) + (S1 ∙ S0 ∙ TB) S2 10
S3 11
FSM State Transition Table
91

TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red
Current State Inputs Next State
S1 S0 TA TB S’1 S’0
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1 S3 S2
1 0 X 1 1 0 LA: red LA: red
1 1 X X 0 0 LB: yellow LB: green
TB
TB

State Encoding
S’1 = S1 xor S0 (Simplified)
S0 00
S1 01
S’0 = (S1 ∙ S0 ∙ TA) + (S1 ∙ S0 ∙ TB) S2 10
S3 11
Finite State Machine:
Output Table
FSM Output Table
93

TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB
FSM Output Table
94

TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red
Current State Outputs

S1 S0 LA LB

0 0 green red

0 1 yellow red S3 S2
LA: red LA: red
1 0 red green
LB: yellow LB: green
TB
1 1 red yellow
TB

Output Encoding

green 00

yellow 01

red 10
FSM Output Table
95

TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red
Current State Outputs
S1 S0 LA1 LA0 LB1 LB0
0 0 0 0 1 0
0 1 0 1 1 0
1 0 1 0 0 0 S3 S2
1 1 1 0 0 1 LA: red LA: red
LB: yellow LB: green
TB
TB
LA1 = S1
Output Encoding

green 00

yellow 01

red 10
FSM Output Table
96

TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red
Current State Outputs
S1 S0 LA1 LA0 LB1 LB0
0 0 0 0 1 0
0 1 0 1 1 0
1 0 1 0 0 0 S3 S2
1 1 1 0 0 1 LA: red LA: red
LB: yellow LB: green
TB
TB
LA1 = S1
Output Encoding
LA0 = S1 ∙ S0
green 00

yellow 01

red 10
FSM Output Table
97

TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red
Current State Outputs
S1 S0 LA1 LA0 LB1 LB0
0 0 0 0 1 0
0 1 0 1 1 0
1 0 1 0 0 0 S3 S2
1 1 1 0 0 1 LA: red LA: red
LB: yellow LB: green
TB
TB
LA1 = S1
Output Encoding
LA0 = S1 ∙ S0
green 00
LB1 = S1
yellow 01

red 10
FSM Output Table
98

TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red
Current State Outputs
S1 S0 LA1 LA0 LB1 LB0
0 0 0 0 1 0
0 1 0 1 1 0
1 0 1 0 0 0 S3 S2
1 1 1 0 0 1 LA: red LA: red
LB: yellow LB: green
TB
TB
LA1 = S1
Output Encoding
LA0 = S1 ∙ S0
green 00
LB1 = S1
yellow 01
LB0 = S1 ∙ S0
red 10
Finite State Machine:
Schematic
FSM Schematic: State Register
100
FSM Schematic: State Register
101

CLK
S'1 S1

S'0 S0
r
Reset
state register
FSM Schematic: Next State Logic
102

CLK
S'1 S1

TA S'0 S0
r
TB Reset
S1 S0

inputs next state logic state register

S’1 = S1 xor S0

S’0 = (S1 ∙ S0 ∙ TA) + (S1 ∙ S0 ∙ TB)

 FSM Schematic: Output Logic
103

CLK LA1
S'1 S1
LA0

TA S'0 S0
LB1
r
TB Reset
S1 S0 LB0

inputs next state logic state register output logic outputs

LA1 = S1
LA0 = S1 ∙ S0
LB1 = S1
LB0 = S1 ∙ S0
 TA__
Reset
S0 TA S1
FSM Timing Diagram LA: green LA: yellow
LB: red LB: red
104

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
 TA__
Reset
S0 TA S1
FSM Timing Diagram LA: green LA: yellow
LB: red LB: red
105

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
 TA__
Reset
S0 TA S1
FSM Timing Diagram LA: green LA: yellow
LB: red LB: red
106

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
 TA__
Reset
S0 TA S1
FSM Timing Diagram LA: green LA: yellow
LB: red LB: red
107

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
 TA__
Reset
S0 TA S1
FSM Timing Diagram LA: green LA: yellow
LB: red LB: red
108

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
 TA__
Reset
S0 TA S1
FSM Timing Diagram LA: green LA: yellow
LB: red LB: red
109

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
 TA__
Reset
S0 TA S1
FSM Timing Diagram LA: green LA: yellow
LB: red LB: red
110

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
 TA__
Reset
S0 TA S1
FSM Timing Diagram LA: green LA: yellow
LB: red LB: red
111

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
 TA__
Reset
S0 TA S1
FSM Timing Diagram LA: green LA: yellow
LB: red LB: red
112

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
 TA__
Reset
S0 TA S1
FSM Timing Diagram LA: green LA: yellow
LB: red LB: red
113

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
Finite State Machine:
State Encoding
FSM State Encoding
115

▪ How do we encode the state bits?

▪ Three common state binary encodings with different tradeoffs
1. Fully Encoded
2. 1-Hot Encoded
3. Output Encoded

▪ Let’s see an example Swiss traffic light with 4 states

▪ Green, Yellow, Red, Yellow+Red
FSM State Encoding (II)
116

1. Binary Encoding (Full Encoding):

▪ Use the minimum possible number of bits
▪ Use log2(num_states) bits to represent the states
▪ Example state encodings: 00, 01, 10, 11
▪ Minimizes # flip-flops, but not necessarily output logic or
next state logic

2. One-Hot Encoding:
▪ Each bit encodes a different state
▪ Uses num_states bits to represent the states
▪ Exactly 1 bit is “hot” for a given state
▪ Example state encodings: 0001, 0010, 0100, 1000
▪ Simplest design process – very automatable
▪ Maximizes # flip-flops, minimizes next state logic
FSM State Encoding (III)
117

3. Output Encoding:
▪ Outputs are directly accessible in the state encoding

▪ For example, since we have 3 outputs (light color),

encode state with 3 bits, where each bit represents a
color
▪ Example states: 001, 010, 100, 110
▪ Bit0 encodes green light output,
▪ Bit1 encodes yellow light output
▪ Bit2 encodes red light output

▪ Minimizes output logic

▪ Only works for Moore Machines (output function of state)
FSM State Encoding (III)
118

3. Output Encoding:
▪ Outputs are directly accessible in the state encoding

▪ For example, since we have 3 outputs (light color),

The designer
encode state with 3must carefully
bits, where each bitchoose
represents a
an encoding
color scheme to optimize the design
▪ Exampleunder given
states: 001, 010,constraints
100, 110
▪ Bit0 encodes green light output,
▪ Bit1 encodes yellow light output
▪ Bit2 encodes red light output

▪ Minimizes output logic

▪ Only works for Moore Machines (output function of state)
Moore vs. Mealy Machines
Recall: Moore vs. Mealy FSMs
120

▪ Next state is determined by the current state and the inputs

▪ Two types of FSMs differ in the output logic:
▪ Moore FSM: outputs depend only on the current state
▪ Mealy FSM: outputs depend on the current state and the inputs
Moore FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic

Mealy FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic
Moore vs. Mealy FSM Examples
121

▪ Alyssa P. Hacker has a snail that crawls down a paper tape

with 1’s and 0’s on it.
▪ The snail smiles whenever the last four digits it has crawled
over are 1101.
▪ Design Moore and Mealy FSMs of the snail’s brain.
Moore FSM

CLK
M next
next k state
k state output N
inputs state outputs
logic
logic

Mealy FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic
Moore vs. Mealy FSM Examples
122

▪ Alyssa P. Hacker has a snail that crawls down a paper tape

with 1’s and 0’s on it.
▪ The snail smiles whenever the last four digits it has crawled
over are 1101.
▪ Design Moore and Mealy FSMs of the snail’s brain.
Moore FSM

CLK
M next
next k state
k state output N
inputs state outputs
logic
logic

Mealy FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic
State Transition Diagrams
123

Moore FSM 1
reset
1 1 0 1

S0 S1 S2 S3 S4
0 0 0 0 1
0
1 0 0
0

What are the tradeoffs?

Mealy FSM
1/1
reset
1/0 1/0 0/0

S0 S1 S2 S3
0/0 1/0 0/0
0/0
FSM Design Procedure
124

▪ Determine all possible states of your machine

▪ Develop a state transition diagram

▪ Generally this is done from a textual description
▪ You need to
▪ 1) determine the inputs and outputs for each state and
▪ 2) figure out how to get from one state to another

▪ Approach
▪ Start by defining the reset state and what happens from it – this is typically an easy
point to start from
▪ Then continue to add transitions and states
▪ Picking good state names is very important
▪ Building an FSM is like programming (but it is not programming!)
▪ An FSM has a sequential “control-flow” like a program with conditionals and goto’s
▪ The if-then-else construct is controlled by one or more inputs
▪ The outputs are controlled by the state or the inputs
▪ In hardware, we typically have many concurrent FSMs
 Additional Content:
Different Types of Flip Flops
Enabled Flip-Flops
126

▪ Inputs: CLK, D, EN
▪ The enable input (EN) controls when new data (D) is stored
▪ Function:
▪ EN = 1: D passes through to Q on the clock edge
▪ EN = 0: the flip-flop retains its previous state

Internal
Circuit Symbol

EN CLK

0
D Q Q D Q
D 1
EN
Resettable Flip-Flop
127

▪ Inputs: CLK, D, Reset

▪ The Reset is used to set the output to 0.
▪ Function:
▪ Reset = 1: Q is forced to 0
▪ Reset = 0: the flip-flop behaves like an ordinary D flip-flop

Symbols

D Q
r
Reset
Resettable Flip-Flops
128

▪ Two types:
▪ Synchronous: resets at the clock edge only
▪ Asynchronous: resets immediately when Reset = 1
▪ Asynchronously resettable flip-flop requires changing the internal
circuitry of the flip-flop (see Exercise 3.10)
▪ Synchronously resettable flip-flop?

Internal
Circuit
CLK

D
D Q Q
Reset
Settable Flip-Flop
129

▪ Inputs: CLK, D, Set

▪ Function:
▪ Set = 1: Q is set to 1
▪ Set = 0: the flip-flop behaves like an ordinary D flip-flop

Symbols

D Q
s
Set