Introduction to Digital Systems

Part III (Sequential Components)

2024/2025

Sequential Logic Fundamentals

and Basic Circuits

Arnaldo Oliveira, Augusto Silva, Iouliia Skliarova

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 Lecture Contents
• Sequential logic circuits fundamentals
– Motivation and concepts
• Sequential logic basic circuits (memory elements built
with ordinary gates and feedback loops)
– S-R Latch
– D Latch
– D Flip-flop

Figures and most content extracted from: John F. Wakerly,

“Digital Design – Principles and Practices”, 4 ed., Pearson
– Prentice Hall, 2006 (chapter 7). Reading chapter 7 (4th
ed.) or chapter 10 (5th ed.) is highly recommended.

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Sequential Circuit Example

Next
+1 Volume Memory
0 +
Element Current
-1
Volume
Down Up
?
Button Button
Enable
Periodic
Update

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 Introduction
• Combinational logic circuit
– Is one whose outputs depend only on its current inputs
• Sequential logic circuit
– Is one whose outputs depend not only on its current
inputs, but also on the past sequence of inputs, possibly
far back in time
• State of a sequential circuit
– Is a collection of state variables whose values at any one
time contain all the information about the past, necessary
to account for the circuit’s future behavior
• N-bit state variable: 2N maximum number of states

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 Clock Signals
• State changes of most Next
+1
sequential circuits occur 0 +
Volume Memory
Element Current
-1
at times specified by a Volume
Down Up
free-running clock signal Button
?
Button
Enable

• Active high / active low Periodic

Update

clock signals

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 Bistable Element (Basic Structure)
• No inputs and therefore no way of controlling
or changing its state (random set at power up)
• Only illustrative but serves the basis for more
complex and useful memory elements

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Bistable Element (Analog Analysis)

3 equilibrium points: 2 stable and 1 metastable

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Metastability

Effects of noise and circuit

impairments on metastability
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 S-R Latch
(Structure and Function Table)

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 S-R Latch
(Operation/Timing Diagrams)

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 S-R Latch
Theoretical
(State Diagram)
SR=00,01 SR=00,10
SR=10
QQ QQ
01 SR=01 10
SR=01 SR=10 Real
SR=11 SR=00,01 SR=00,10
SR=10
QQ QQ QQ
SR=11 00 SR=11 01 SR=01 10
SR=00 SR=00 SR=01 SR=10
SR=11
SR=01 SR=10
QQ
SR=11 00 SR=11
QQ
11 SR=00 SR=00
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 S-R Latch
(Characteristic Equation)

Real
SR=00,01 SR=00,10
SR=10
QQ QQ
01 SR=01 10
SR=01 SR=10 SR
SR=11 Q 00 01 11 10

0 0 0 X 1
QQ 1 1 0 X 1
SR=11 00 SR=11
Q+= S + Q.R
SR=00 SR=00

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S-R Latch (Symbol)

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S-R Latch (Timing Parameters)
• tpLH – propagation time LOW-to-HIGH
• tpHL – propagation time HIGH-to-LOW
• Tpw(min) – minimum pulse width

Non-determinism/metastability due to violation of Tpw(min)

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S-R Latch (with NAND Gates)

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S-R Latch with Enable (C)

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S-R Latch with Enable (Operation)

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D Latch (Structure and Operation)

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 D Latch
(State Diagram and Characteristic Equation)

D
D=0 D=1 Q 0 1
D=1
0 0 1
QQ QQ
01 D=0 10 1 0 1

Q+= D

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D Latch (Timing Parameters)
• tpLH – propagation time LOW-to-HIGH
• tpHL – propagation time HIGH-to-LOW
• tsetup – setup time
• thold – hold time

Non-determinism/metastability due to violation of

tsetup and/or thold

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 Application Example of an S-R Latch
Debounce mechanical switches
+Vcc When When
moved to B moved to A
+Vcc
When B
moved to B Q
B +Vcc B
Q
A GND A

GND A

+Vcc

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 Latch Limitations/Issues
D
Q
C

Current Volume
Next Volume
Next Latch
+1 Volume Based
0 +
Memory Current D
-1 Q
Element Volume C
Down Up
? D
Button Button Q
C
Enable
Update

Uncontrolled (chaotic) updates

dependent on circuit delays!

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Possible Solution? Unfeasible!

Next Latch
+1 Volume Based
0 +
Memory Current
-1
Element Volume
Down Up
?
Button Button
Enable
Update

Very narrow enable pulses?

Very difficult to implement!
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 A Feasible Solution

Next Flip-flop
+1 Volume Based
0 +
Memory Current
-1
Element Volume
Down Up
?
Button Button
(Periodic)
Clock

Periodic updates triggered by

one of the edges (rising or
falling) of a clock signal

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 Positive-edge-triggered D Flip-flop
• Latches are not used frequently but are a building block for flip-flops

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Clock Signals (revisited)

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Positive-edge-triggered D Flip-flop
(Functional Behavior / Operation)

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Positive-edge-triggered D Flip-flop
(Timing Behavior)
• tpLH – propagation time LOW-to-HIGH
• tpHL – propagation time HIGH-to-LOW
• tsetup – setup time
• thold – hold time

Non-determinism/metastability due to violation of

tsetup and/or thold

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Negative-edge-triggered D Flip-flop

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Positive-edge-triggered D Flip-flop
with Preset and Clear

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 Positive-edge-triggered D Flip-flop
(7474 Commercial Integrated Circuit)
• 6 gates instead of 8
gates + inverters
• To be analyzed later…

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Positive-edge-triggered D Flip-flop
with Enable

Mux 2:1

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 Exercise
• Design the complete logic diagram of the volume
control system based on positive-edge-triggered D Flip-
flops with enable (assume 16 levels of volume).
• Component budget
– Flip-flops
Next Flip-flop
– Adder +1 Volume Based
0 +
– Mux 2:1 -1
Memory
Element
Current
Volume
– Logic gates Down
?
Up
Button Button
(Periodic)
Clock
• From the usability point of view, what
could be the clock frequency?
• How to force a predefined volume Periodic updates triggered by
level (e.g. half scale) at power up? one of the edges (rising or
falling) of a clock signal
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 Conclusion
• At the end of this lecture and corresponding lab, it is fundamental
to know and understand the structure, operation and timing
behavior of basic sequential logic circuits (latches and flip-flops)
• Plan for the next lectures
– Analysis of sequential circuits (Finite State Machines) and timing
aspects
– Synthesis of sequential circuits (Finite State Machines)
– Standard sequential circuits
• Registers and shift registers
• Counters
– Iterative vs. sequential circuits

Reading chapter 7 (4th ed.) or chapter 10 (5th ed.) of John F. Wakerly,

“Digital Design – Principles and Practices”, Pearson – Prentice Hall, is
highly recommended.

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