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Assembly Ass 1

The document discusses the specifications and solutions for six questions regarding cache memory organization. It provides the format of main memory addresses for various cache configurations including two-way set associative, eight-way set associative, four-way set associative, and directly mapped caches. It also calculates the number of addressable memory units and cache parameters such as number of sets, block size, and tag size.

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7 views11 pages

Assembly Ass 1

The document discusses the specifications and solutions for six questions regarding cache memory organization. It provides the format of main memory addresses for various cache configurations including two-way set associative, eight-way set associative, four-way set associative, and directly mapped caches. It also calculates the number of addressable memory units and cache parameters such as number of sets, block size, and tag size.

Uploaded by

rubafaraz56
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Comsats University Islamabad

Abbottabad Campus

ASSIGNMENT NO 2

SUBMITTED BY: RUBA FARAZ


SUBMITTED TO: hifza Ali
SUBJECT: computer organization or assembly
language
Question: 01
A two-way set-associative cache consists of 1024 lines, or slots, divided into several sets. Main
memory contains 8K blocks of 256 words each. Show the format of main memory address.

 Address length = (s + w) bits


 Number of addressable units = 2s+w words or bytes
 Block size = line size = 2w words or bytes
 Number of blocks in main memory = 2s+w/2w=2s
 Number of lines in set = k
 Number of sets = v = 2d
 Number of lines in cache = m=kv = k * 2d
 Size of cache = k * 2d+w words or bytes
 Size of tag = (s – d) bits

Solution:

Two-way=k-way
 size of set=k = 2
k=2

 total lines in cache=m=1024 lines


m=1024
=2^10

Number of lines in cache=m=kv


m=kv
v=m/k
v=2^10/2

no of sets=v=2^9

v=2^d
=2^d
2^9=2^d
Comparing powers;
d=9

 number of blocks in main memory=2^s=8k

2^s=2^3 *2^10
2^s=2^13
comparing powers
S=13

 block size=line size=2^w=256 words


2^w=256
2^w=2^8
comparing powers
W=8

Address length=s+w=13+8
Address length=31
Number of Addressable units=2^s+w
=2^13+8
=2^21
=2097152
Tag size=(s-d) bits
=13-9
Tag size=4

Tag =4bits set=9bits words=8

Question: 02
An eight-way set-associative cache has lines of 32 bytes and a total size of 16 MB. The 64-GB
main memory is byte addressable. Show the format of main memory addresses.

 Address length = (s + w) bits


 Number of addressable units = 2s+w words or bytes
 Block size = line size = 2w words or bytes
 Number of blocks in main memory = 2s+w/2w=2s
 Number of lines in set = k
 Number of sets = v = 2d
 Number of lines in cache = m=kv = k * 2d
 Size of cache = k * 2d+w words or bytes
 Size of tag = (s – d) bits

Solution:
eight-way=k-way
 size of set=k = 8
k=8

 block size=line size=2^w=32 bytes


2^w=32
2^w=2^5
comparing powers
w=5

No of lines in cache =m=16MB/32bytes


m=1*2^20/2
m=2^19
m=2^19

v =no of sets)

m=kv
v=m/k
v=2^19/8
v=2^19/2^3
v=2^16

v=2^d
2^16=2^d
comparing powers
d=16

Number of Addressable units=2^s+w=64GB


=2^6*2^30
=2^36
=2^s+w=2^36
S+w=36
And w=5
S=36-w
S=36-5
S=31

Tag size=(s-d) bits


=31-16

Tag size =15

TAG= 15 SET = 16 WORD a5

Question 3.
Given the following specifications for a cache memory: four-way set associative; line size of two
16-bit words; able to accommodate a total of 4K words from main memory of 256 G. Show the
format of main memory addresses.

 Address length = (s + w) bits


 Number of addressable units = 2s+w words or bytes
 Block size = line size = 2w words or bytes
 Number of blocks in main memory = 2s+w/2w=2s
 Number of lines in set = k
 Number of sets = v = 2d
 Number of lines in cache = m=kv = k * 2d
 Size of cache = k * 2d+w words or bytes
 Size of tag = (s – d) bits

Solution:

Four-way=k-way
 size of set=k = 4
K=4

 block size=line size=2^w=2


2^w=2
comparing powers
W=1

Total cache size = 4K words=2 ^2*2^10


=2^12

Main memory size = 2^s+w=256 GB

=(256 * 2^30 )

=2^9*2^30

=2^39

S+w=39

w=1
S=39-w
S=39-1
S=38

No of lines in cache =m=2^12/2


m=2^12/2
m=2^11
m=2^11

v= no of sets

m=kv
v=m/k
v=2^11/4=2^11/2^2

V=2^9

v=2^d
2^9=2^d
comparing powers
D=9

Tag size=(s-d) bits


=38-9

Tag size =29


Address length=(s+w) bits
=38-1

Address length=37

TAG 29 set=9 word= 1

Question 4:
Consider a directly mapped cache of 2000 lines that maps a main memory of 1024 G words
grouped into blocks of 32 words.
a. What is the number of maximum directly addressable memory units?
b. Show the format of the main memory address.
 Address length = (s + w) bits
 Number of addressable units = 2s+w words or bytes
 Block size = line size = 2w words or bytes
 Number of blocks in main memory = 2s+ w/2w = 2s
 Number of lines in cache = m = 2r
 Size of tag = (s – r) bits
Solution:
Size of cache =m=2000lines ~2^11
m=2^11

m=2^11

Size of cache =m=2^r


2^r=2^11
comparing powers
r=11
Size of 1 block=2^w=32
2^w=2^5
comparing powers
W=5

Main memory size = 2^s+w=1024 G words

= (1024* 2^30)

=2^10*2^30=2^40

s + w =40
w=5
s=40-w
s=40-5
S=35

directly addressable memory units (number of blocks)


Number of blocks=size of cache/size of block
=2^11/2^5
=2^11-5
=2^6

Number of blocks=64

Tag=s-r= 35-11
= 24
Tag=2
format of the main memory address;

Tag (s-r) =2 Line(r) =11 word=5


Question 5:
Consider a directly mapped cache of 16M lines that maps a Main Memory of 128 G blocks of 4
words each. Find the total addressable units in the main memory and the format of the main
memory address.

 Address length = (s + w) bits


 Number of addressable units = 2s+w words or bytes
 Block size = line size = 2w words or bytes
 Number of blocks in main memory = 2s+ w/2w = 2s
 Number of lines in cache = m = 2r
Solution:
Size of cache =m=16M lines
m= 16*2^20
m=2^4*2^20

m=24

main memory block size-2^s=128G


2^s=2^7*2^30

comparing powers
S=37

size of 1 block=2^w=4 words


2^w=2^4
W=4
Total addressable units in the main memory
Total addressable units=2^s+w
=2^37+4
=2^41
addressable units in the main memory.

Tag =s-r
=37-24
=13 bits

Tag=13 bits lines=24 words =4

Question 6:
Consider a Fully Associative mapped cache of 10 M lines that maps a Main Memory of 512 G
blocks of 32 words each. Find the total addressable units in the main memory as well as the total
no of blocks in the cache. and the format of the main memory address showing the size of the
tag.
Solution:
Size of cache =m=10M lines
m= 10*2^20
m=10*2^20

m=10*2^20

main memory block size=2^s=512G


2^s=2^9
comparing powers
S=9

size of 1 block=2^w
=32 words
comparing powers

2^w=2^5
comparing powers;
W=5
Total addressable units=2^s/2^w
=2^9/2^5
=2^4

Total addressable units=16


Tag=s
=9bits

Tag=9 words=5

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