PIC16F87XA

7.0 TIMER2 MODULE Register 7-1 shows the Timer2 Control register.
Additional information on timer modules is available in
Timer2 is an 8-bit timer with a prescaler and a
the PICmicro® Mid-Range MCU Family Reference
postscaler. It can be used as the PWM time base for the
Manual (DS33023).
PWM mode of the CCP module(s). The TMR2 register
is readable and writable and is cleared on any device
Reset. FIGURE 7-1: TIMER2 BLOCK DIAGRAM
The input clock (FOSC/4) has a prescale option of Sets Flag
TMR2
bit TMR2IF Output(1)
1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
Reset Prescaler
The Timer2 module has an 8-bit period register, PR2. TMR2 Reg
1:1, 1:4, 1:16
FOSC/4
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is Postscaler 2
Comparator
1:1 to 1:16 EQ
a readable and writable register. The PR2 register is T2CKPS1:
initialized to FFh upon Reset. 4 PR2 Reg T2CKPS0

The match output of TMR2 goes through a 4-bit T2OUTPS3:

postscaler (which gives a 1:1 to 1:16 scaling inclusive) T2OUTPS0

to generate a TMR2 interrupt (latched in flag bit, Note 1: TMR2 register output can be software selected by the
TMR2IF (PIR1<1>)). SSP module as a baud clock.

Timer2 can be shut-off by clearing control bit, TMR2ON

(T2CON<2>), to minimize power consumption.

REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 postscale
0001 = 1:2 postscale
0010 = 1:3 postscale
•
•
•
1111 = 1:16 postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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PIC16F87XA
7.1 Timer2 Prescaler and Postscaler 7.2 Output of TMR2
The prescaler and postscaler counters are cleared The output of TMR2 (before the postscaler) is fed to the
when any of the following occurs: SSP module, which optionally uses it to generate the
• a write to the TMR2 register shift clock.
• a write to the T2CON register
• any device Reset (POR, MCLR Reset, WDT
Reset or BOR)
TMR2 is not cleared when T2CON is written.

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Value on
Value on:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
10Bh, 18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.

DS39582B-page 62  2003 Microchip Technology Inc.

 PIC16F87XA
8.0 CAPTURE/COMPARE/PWM CCP2 Module:
MODULES Capture/Compare/PWM Register 2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
Each Capture/Compare/PWM (CCP) module contains CCPR2H (high byte). The CCP2CON register controls
a 16-bit register which can operate as a: the operation of CCP2. The special event trigger is
• 16-bit Capture register generated by a compare match and will reset Timer1
• 16-bit Compare register and start an A/D conversion (if the A/D module is
enabled).
• PWM Master/Slave Duty Cycle register
Additional information on CCP modules is available in
Both the CCP1 and CCP2 modules are identical in
the PICmicro® Mid-Range MCU Family Reference
operation, with the exception being the operation of the
Manual (DS33023) and in application note AN594,
special event trigger. Table 8-1 and Table 8-2 show the
“Using the CCP Module(s)” (DS00594).
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the TABLE 8-1: CCP MODE – TIMER
same as CCP1 except where noted. RESOURCES REQUIRED
CCP1 Module: CCP Mode Timer Resource
Capture/Compare/PWM Register 1 (CCPR1) is com- Capture Timer1
prised of two 8-bit registers: CCPR1L (low byte) and Compare Timer1
CCPR1H (high byte). The CCP1CON register controls PWM Timer2
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.

TABLE 8-2: INTERACTION OF TWO CCP MODULES

CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time base
Capture Compare The compare should be configured for the special event trigger which clears TMR1
Compare Compare The compare(s) should be configured for the special event trigger which clears TMR1
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt)
PWM Capture None
PWM Compare None

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PIC16F87XA
REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS 17h/1Dh)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1
resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is
enabled)
11xx = PWM mode

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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 PIC16F87XA
8.1 Capture Mode 8.1.2 TIMER1 MODE SELECTION
In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode, or Synchro-
16-bit value of the TMR1 register when an event occurs nized Counter mode, for the CCP module to use the
on pin RC2/CCP1. An event is defined as one of the capture feature. In Asynchronous Counter mode, the
following: capture operation may not work.

• Every falling edge 8.1.3 SOFTWARE INTERRUPT

• Every rising edge
When the Capture mode is changed, a false capture
• Every 4th rising edge interrupt may be generated. The user should keep bit
• Every 16th rising edge CCP1IE (PIE1<2>) clear to avoid false interrupts and
The type of event is configured by control bits, should clear the flag bit, CCP1IF, following any such
CCP1M3:CCP1M0 (CCPxCON<3:0>). When a cap- change in operating mode.
ture is made, the interrupt request flag bit, CCP1IF
(PIR1<2>), is set. The interrupt flag must be cleared in 8.1.4 CCP PRESCALER
software. If another capture occurs before the value in There are four prescaler settings, specified by bits
register CCPR1 is read, the old captured value is CCP1M3:CCP1M0. Whenever the CCP module is
overwritten by the new value. turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any Reset will clear
8.1.1 CCP PIN CONFIGURATION the prescaler counter.
In Capture mode, the RC2/CCP1 pin should be Switching from one capture prescaler to another may
configured as an input by setting the TRISC<2> bit. generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
Note: If the RC2/CCP1 pin is configured as an
a non-zero prescaler. Example 8-1 shows the recom-
output, a write to the port can cause a
mended method for switching between capture
Capture condition.
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
FIGURE 8-1: CAPTURE MODE
OPERATION BLOCK EXAMPLE 8-1: CHANGING BETWEEN
DIAGRAM CAPTURE PRESCALERS
Set Flag bit CCP1IF CLRF CCP1CON ; Turn CCP module off
(PIR1<2>) MOVLW NEW_CAPT_PS ; Load the W reg with
Prescaler ; the new prescaler
÷ 1, 4, 16
RC2/CCP1 ; move value and CCP ON
pin CCPR1H CCPR1L MOVWF CCP1CON ; Load CCP1CON with this
; value
and Capture
Edge Detect Enable

TMR1H TMR1L
CCP1CON<3:0>
Qs

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PIC16F87XA
8.2 Compare Mode 8.2.2 TIMER1 MODE SELECTION
In Compare mode, the 16-bit CCPR1 register value is Timer1 must be running in Timer mode, or Synchro-
constantly compared against the TMR1 register pair nized Counter mode, if the CCP module is using the
value. When a match occurs, the RC2/CCP1 pin is: compare feature. In Asynchronous Counter mode, the
compare operation may not work.
• Driven high
• Driven low 8.2.3 SOFTWARE INTERRUPT MODE
• Remains unchanged When Generate Software Interrupt mode is chosen, the
The action on the pin is based on the value of control CCP1 pin is not affected. The CCPIF bit is set, causing
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the a CCP interrupt (if enabled).
same time, interrupt flag bit CCP1IF is set.
8.2.4 SPECIAL EVENT TRIGGER
FIGURE 8-2: COMPARE MODE In this mode, an internal hardware trigger is generated
OPERATION BLOCK which may be used to initiate an action.
DIAGRAM The special event trigger output of CCP1 resets the
Special event trigger will: TMR1 register pair. This allows the CCPR1 register to
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>) effectively be a 16-bit programmable period register for
and set bit GO/DONE (ADCON0<2>).
Timer1.
Special Event Trigger The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
Set Flag bit CCP1IF
A/D module is enabled).
(PIR1<2>)
RC2/CCP1 CCPR1H CCPR1L
pin Note: The special event trigger from the CCP1
Q S and CCP2 modules will not set interrupt
Output
Logic Comparator flag bit TMR1IF (PIR1<0>).
R Match

TRISC<2> TMR1H TMR1L

Output Enable CCP1CON<3:0>
Mode Select

8.2.1 CCP PIN CONFIGURATION

The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC<2> bit.
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.

DS39582B-page 66  2003 Microchip Technology Inc.

 PIC16F87XA
8.3 PWM Mode (PWM) 8.3.1 PWM PERIOD
In Pulse Width Modulation mode, the CCPx pin The PWM period is specified by writing to the PR2
produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the
the CCP1 pin is multiplexed with the PORTC data latch, following formula:
the TRISC<2> bit must be cleared to make the CCP1 PWM Period = [(PR2) + 1] • 4 • TOSC •
pin an output. (TMR2 Prescale Value)
Note: Clearing the CCP1CON register will force PWM frequency is defined as 1/[PWM period].
the CCP1 PWM output latch to the default When TMR2 is equal to PR2, the following three events
low level. This is not the PORTC I/O data occur on the next increment cycle:
latch.
• TMR2 is cleared
Figure 8-3 shows a simplified block diagram of the
• The CCP1 pin is set (exception: if PWM duty
CCP module in PWM mode.
cycle = 0%, the CCP1 pin will not be set)
For a step-by-step procedure on how to set up the CCP • The PWM duty cycle is latched from CCPR1L into
module for PWM operation, see Section 8.3.3 “Setup CCPR1H
for PWM Operation”.
Note: The Timer2 postscaler (see Section 7.1
“Timer2 Prescaler and Postscaler”) is
FIGURE 8-3: SIMPLIFIED PWM BLOCK
not used in the determination of the PWM
DIAGRAM frequency. The postscaler could be used
CCP1CON<5:4> to have a servo update rate at a different
Duty Cycle Registers
frequency than the PWM output.
CCPR1L
8.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
CCPR1H (Slave)
to 10-bit resolution is available. The CCPR1L contains
RC2/CCP1 the eight MSbs and the CCP1CON<5:4> contains the
Comparator R Q two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
TMR2 (Note 1) used to calculate the PWM duty cycle in time:
S
PWM Duty Cycle =(CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
Comparator TRISC<2>
Clear Timer, CCPR1L and CCP1CON<5:4> can be written to at any
CCP1 pin and
latch D.C. time, but the duty cycle value is not latched into
PR2
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
Note 1: The 8-bit timer is concatenated with 2-bit internal Q CCPR1H is a read-only register.
clock, or 2 bits of the prescaler, to create 10-bit time
base. The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
A PWM output (Figure 8-4) has a time base (period) double-buffering is essential for glitch-free PWM
and a time that the output stays high (duty cycle). The operation.
frequency of the PWM is the inverse of the period
(1/period). When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
FIGURE 8-4: PWM OUTPUT the TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
Period frequency is given by the following formula.

EQUATION 8-1:
Duty Cycle
Resolution =
( FOSC
log FPWM ) bits
TMR2 = PR2 log(2)
TMR2 = Duty Cycle
Note: If the PWM duty cycle value is longer than
TMR2 = PR2
the PWM period, the CCP1 pin will not be
cleared.

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PIC16F87XA
8.3.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.

TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFFh 0xFFh 0xFFh 0x3Fh 0x1Fh 0x17h
Maximum Resolution (bits) 10 10 10 8 7 5.5

TABLE 8-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1

Value on
Value on:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
10Bh, 18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on 28-pin devices; always maintain these bits clear.

DS39582B-page 68  2003 Microchip Technology Inc.

 PIC16F87XA
TABLE 8-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
Value on:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
10Bh, 18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
92h PR2 Timer2 Module’s Period Register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.

 2003 Microchip Technology Inc. DS39582B-page 69