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PIC Micro Controllers Architecture-2 (Peripherals)

MC ARCHITECHTURE 2 PPT

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65 views26 pages

PIC Micro Controllers Architecture-2 (Peripherals)

MC ARCHITECHTURE 2 PPT

Uploaded by

Unique Pro
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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PIC® Micro controllers

Architecture-2
(Peripherals)
Contents
• Interrupts
• Timers
• Watchdog Timer
• PWM
• USART
Interrupts
When an interrupt request arrives, the
flag bit is to be set first.
Interrupts
INTCON register
PIE Registers
(Peripheral interrupt enable bits)
PIR Registers
(Peripheral interrupt flag bits)
PCON register
To differentiate between a: power-on reset, brown-out reset, Watchdog Timer
Reset and external reset (through MCLR pin).

ULPWUE - Ultra Low-Power Wake-up Enable bit


SBOREN - Software BOR Enable bit
POR - Power-on Reset Status bit
BOR - Brown-out Reset Status bit
I/O Ports
Port A
Port A is an 8-bit wide, bidirectional port.
Bits of the TRISA and ANSEL control the
PORTA pins.
Port B

Port B is an 8-bit wide, bidirectional port.


Timers
There are three completely independent
timers/counters marked as TMR0, TMR1
and TMR2.
Timer TMR0

8-bit timer/counter register


internal or external clock source
Interrupt on overflow
OPTION_REG Register

Timer mode is selected by clearing the


T0CS bit.
Will increment every instruction cycle
Timer TMR1

Timer TMR1 module is a 16-bit timer/counter,


Inputs may come from different sources
T1CON Register
Timer TMR2

Timer TMR2 module is an 8-bit timer which operates in a bit


specific way. The values of TMR2 and PR2 are constantly
compared and the TMR2 register keeps on being incremented
until it matches the value in PR2.
T2CON register
Watchdog Timer
• Can be set to reset the processor after watched-
time for finishing a task is over
• During normal operation, a WDT time-out generates
a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation
(Watchdog Timer Wake-up). The TO bit in the Status
register will be cleared upon a Watchdog Timer time-
out.
• The WDT can be permanently disabled by clearing
configuration bit, WDTE
CCP Modules
• In Capture Mode, the peripheral allows
timing of duration of an event.
• The Compare Mode compares values
contained in two registers at some point.
allows the user to trigger an external event
when a predetermined amount of time has
expired.
• PWM - can generate signals of varying
frequency and duty cycle.
Capture mode
Compare mode
PWM mode
CCP1CON Register

Bit 3-0:
CCP1M3:CCP1MO (CCP1 Mode select bits) 
0000=Capture/Compare/PWM Mode off 
0100=Capture mode, every falling edge 
0101=Capture mode, every rising edge
0110=Capture mode, every 4 th rising edge 
0111=Capture mode, every 16 th rising edge 
1000=Compare mode, set output on match (CCP1IF bit is set) 
1001=Compare mode, clear output on match (CCP1IF bit is set) 
1010=Compare mode, generate software interrupt on match (CCP1IF bit is set,
CCP1 pin unaffected) 
1011=Compare mode, trigger special event (CCP1IF bit is set;CCP1 resets
Tmr1; CCP2 resets TMR1 and starts A/D conversion if A/D module is
Enabled) 
11XX=PWM mode.
Asynch (Transmitter)
Asynch (Receiver)

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