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A simple figure of merit of RF MOSFET for low-noise amplifier design

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1380 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 12, 2008

A Simple Figure of Merit of RF MOSFET

for Low-Noise Amplifier Design
Ickhyun Song, Student Member, IEEE, Jongwook Jeon, Hee-Sauk Jhon, Junsoo Kim,
Byung-Gook Park, Member, IEEE, Jong Duk Lee, Member, IEEE, and
Hyungcheol Shin, Senior Member, IEEE

2
Abstract—In this letter, it is proposed that gm /ID , which has
been used as the figure of merit (FoM) of MOSFETs for analog
amplifiers, can also be used as the RF MOSFET FoM for op-
timizing low-noise amplifier (LNA) performance. From a simple
small-signal equivalent circuit, signal gain, noise figure, and power
consumption equations are derived analytically and verified with
the measurement results of the fabricated LNA. The proposed
2
gm /ID predicts the optimal bias point for the maximum LNA
performance.
Index Terms—Channel thermal noise, figure of merit (FoM),
low-noise amplifier (LNA), MOSFET.

I. I NTRODUCTION
Fig. 1. (a) CMOS LNA schematic and its simplified small-signal equivalent

R ADIO-FREQUENCY (RF) performance of CMOS tran-

sistors has been significantly improved due to continuous
technology scaling down. In a device perspective, short-channel
circuit. (b) LNA gain versus gate bias voltage (VGS ). A 5.8-GHz LNA is
fabricated using 130-nm CMOS technology. Both M1 and M2 have the
same width of 2 × 26 μm. The solid line shows the square of gm of input
MOSFETs have high-frequency figure of merit (FoM) such transistor M1 .
as cutoff frequency (fT ) and maximum oscillation frequency
(fMAX ) which are much higher than 100 GHz in the advanced ple equation for determining the optimum value of gate bias is
deep-submicron technology [1]. Although these FoMs suggest very helpful in the initial design stage. However, an FoM can be
the feasibility of CMOS devices for the operation in RF range 2
more complicated than gm /ID since noise performance should
[2], they usually do not provide design insight for RF circuit be considered in addition to gain and power consumption. In
optimization. Recently, gm fT /ID has been proposed as an FoM 2
this letter, we propose that gm /ID can also be used for RF
of RF MOSFETs [3]. However, high-frequency s-parameter MOSFETs for LNA design and that it has very close relation
measurement is required to obtain fT . Also, fundamental phys- to the circuit-level FoM optimum. In addition, the nonlinearity
ical reasons for using gm fT /ID as an FoM have not been aspect is considered and discussed.
addressed. In [4]–[6], the minimum point of noise figure was
suggested as an optimum bias point of low-noise amplifier
(LNA). Since noise measurement or accurate noise model II. RF MOSFET F O M
which is usually in a very complex form is needed, it is not A conventional RF LNA topology is shown in Fig. 1(a). It
suitable for designers to adopt. adopts inductive source degeneration to provide real impedance
2
For gain performance of analog amplifiers, gm /ID has been (50 Ω) for input matching. For LNA design, three most im-
considered as an FoM because it represents power gain per unit portant characteristics such as gain, noise figure, and power
dc power consumption [7], [8]. In the design of an LNA, a sim- consumption are considered in FoM, and it has been defined
as follows [9], [10]:

G
FoMLNA = (1)
Manuscript received March 12, 2008; revised September 7, 2008. Current (F − 1) · P
version published November 21, 2008. This work was supported by Samsung
Electronics Company and the Inter-University Semiconductor Research Center where G, F , and P are the gain, noise factor, and power
(ISRC). The review of this letter was arranged by Editor A. Z. Wang.
The authors are with the School of Electrical Engineering and Computer consumption, respectively.
Science and the Inter-University Semiconductor Research Center (ISRC), Seoul Each performance factor in the LNA FoM (1) is de-
National University, Seoul 151-744, Korea (e-mail: sonikyun@gmail.com; rived analytically using a small-signal equivalent circuit, as
voix0707@snu.ac.kr; kindro1@snu.ac.kr; horri4@snu.ac.kr; bgpark@snu.
ac.kr; jdlee@snu.ac.kr; hcshin@snu.ac.kr). shown in Fig. 1(a). With the assumption of the perfectly
Digital Object Identifier 10.1109/LED.2008.2006863 matched condition (Zin = Zout = 50 Ω), which is practically

0741-3106/$25.00 © 2008 IEEE

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SONG et al.: SIMPLE FIGURE OF MERIT OF RF MOSFET FOR LOW-NOISE AMPLIFIER DESIGN 1381

Fig. 2. (a) (Noise factor-1) versus VGS . The NF of the 5.8-GHz LNA was
measured. Simulation results predict a quite accurate noise factor. Due to the
ignorance of parasitic components, Sid /gm 2 shows a slightly different shape
when compared to F − 1. (b) The FoM of an LNA versus gate bias for various Fig. 3. Sid versus ID with MOSFETs with various channel lengths in
frequencies with the assumption of perfect matching is plotted using (1). (a) 130-nm CMOS technology and (b) in 65-nm CMOS technology. Sid is
For each frequency, the optimum bias is the same. roughly a linear function of ID .

saturation effect, and carrier heating effect, and is repeated here

reasonable at LNA target frequency, signal gain is derived as
follows: Sid = 4kT0
 2 2 V3
+ 10VO2 + 7VGT VO + 34 VGT O |2VGT −VO |
Pload 1 gm
4VGT −VO ln VO
G= = ∝ gm
2
. (2) ×
Pin 4 ω · Cgs 3(VGT − VO )(VGT + VO )2
× mID (4)
Since Cgs is approximately a constant in the strong inversion
2 where VGT , m, and V0 are the intrinsic overdrive voltage, body-
region, the signal gain is almost proportional to gm . In Fig. 1(b),
effect coefficient, and ID /W Cox vsat , respectively. Although
measured LNA gain versus gate bias is shown. The LNA was
Sid is a complex model of transistor bias voltage, current, and
fabricated using 130-nm CMOS technology, and the target
other parameters, it is roughly considered as a linear function
frequency is 5.8-GHz ISM band. As mentioned previously,
of ID [12]. Measured results of Sid versus IDS for MOSFETs
the measured maximum point of LNA gain coincides with the
2 with various channel lengths are shown in Fig. 3. Sid ’s of
maximum point of gm .
MOSFETs fabricated using 130- and 65-nm CMOS technolo-
Using Fig. 1(a), noise factor also can be derived as follows:
gies are shown in Fig. 3(a) and (b), respectively. Since linear
 2  2 fit curves of Sid data pass near the origin point, it is reasonable
Sid ω · Cgs 1 to assume that channel thermal noise is almost proportional to
F −1= · · Rsig ∝ Sid · (3)
4kT gm gm IDS in the saturation region [12]. Thus, (3) is further simplified
as follows:
where Sid is the power spectral density of the MOSFET channel
Sid ID
thermal noise [11]. Noise sources other than Sid are ignored F −1∝ 2
∝ 2 . (5)
since channel noise is the most dominant one [10]. In partic- gm gm
ular, the induced gate noise in nanoscale MOSFETs has been
Last, power consumption of an LNA is simply dc current
reported to be negligible [14], [15] and is therefore not included
multiplied by VDD
in (3). Thus, F − 1 is roughly proportional to Sid /gm 2
which is
shown in Fig. 2(a). Compared with simulation results and mea-
P = VDD ID . (6)
surement data, (3) is somewhat different in shape: Its minimum
noise bias point is slightly shifted, and the difference in slope Putting signal gain, noise figure, and power consumption
gets larger when bias moves to either end. Although these errors together, RF MOSFET FoM can be obtained
originate from the ignorance of parasitic components, overall
noise performance trends do not change significantly, which  2
G g2 2
gm
makes it possible to find the optimum bias point. FoMLNA = ∝  m ∝ . (7)
(F − 1) · P ID
·I ID
In Fig. 2(b), LNA FoM versus gate bias is shown at different 2 gm D
frequencies using (1) with the assumption of perfect matching.
As frequency increases, FoM decreases monotonically. Since Since (F − 1) is proportional to ID /gm 2
, the minimum point
the optimal bias which maximizes FoM is almost the same for of (F − 1) coincides with the maximum point of gm 2
/ID . Re-
each frequency, however, this bias point can be directly applied cently, Heydari et al. [13] also reported that the gain optimum
to various target frequencies. point and the noise optimum point of nanoscale MOSFETs are
2
An analytical channel thermal noise model is derived in [11], very close to each other. Therefore, gm /ID can be used as an
which takes into account channel length modulation, velocity FoM for LNA design.

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1382 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 12, 2008

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