Applications of logic design

• Conventional computer design

 CPUs, busses, peripherals
• Networking and communications
 phones, modems, routers
I. Introduction • Embedded products
 in cars, toys, appliances, entertainment devices
• Scientific equipment
 testing, sensing, reporting
• The world of computing is much much bigger than
담당교수: 김 석윤 just PCs!
Original Notes by G. Borriello and Randy H. Katz
Revision Notes by Ki-Young Kim

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What is logic design? What is digital hardware?

• What is design?
• Collection of devices that sense and/or control wires
 given a specification of a problem, come up with a way of solving it
choosing appropriately from a collection of available components
that carry a digital value (i.e., a physical quantity that
 while meeting some criteria for size, cost, power, beauty, elegance,
can be interpreted as a “0” or “1”)
etc.  example: digital logic where voltage < 0.8v is a “0” and > 2.0v is a “1”
• What is logic design?
 determining the collection of digital logic components to perform a • Primitive digital hardware devices
specified control and/or data manipulation and/or communication  logic computation devices (sense and drive)
function and the interconnections between them  are two wires both “1” - make another be “1” (AND)
 which logic components to choose? – there are many implementation  is at least one of two wires “1” - make another be “1” (OR)
technologies  is a wire “1” - then make another be “0” (NOT)
sense
 the design may need to be optimized and/or transformed to meet  memory devices (store)
design constraints  store a value
 recall a previously stored value AND drive

sense
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 Computation:
This Class : concepts/skills/abilities
abstract vs. implementation

• This class is about physically implementing

• Understanding the basics of logic design (concepts)
computation using physical devices that use voltages
• Understanding sound design methodologies (concepts) to represent logical values
• Modern specification methods (concepts) • Basic units of computation are:
• Familiarity with a full set of CAD tools (skills)  representation: "0", "1" on a wire
• Realize digital designs in an implementation set of wires (e.g., for binary ints)
technology (skills)  assignment: x = y
 data operations: x+y–5
• Appreciation for the differences and similarities
 control:
in hardware and software design (abilities) sequential statements: A; B; C
conditionals: if x == 1 then y
loops: for ( i = 1 ; i == 10, i++)
procedures: A; proc(...); B;
• We will study how each of these are implemented in
hardware and composed into computational structures
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Switches: basic element of physical

Switches (cont’d)
implementations
• Implementing a simple circuit (arrow shows action • Compose switches into more complex ones
if wire changes to “1”): (Boolean functions):

A Z A B
AND
close switch (if A is “1” or asserted) Z = A and B
and turn on light bulb (Z)

Z A
A
open switch (if A is “0” or unasserted) OR
Z = A or B
and turn off light bulb (Z)

Z = A B

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Transistor networks MOS transistors

• Modern digital systems are designed in CMOS • MOS transistors have three terminals: drain, gate,
technology and source
 MOS stands for Metal-Oxide on Semiconductor  they act as switches in the following way:
 C is for complementary because there are both normally-open and if the voltage on the gate terminal is (some amount) higher/lower than
normally-closed switches the source terminal then a conducting path will be established
between the drain and source terminals

• MOS transistors act as voltage-controlled switches G G

 similar, though easier to work with than relays.

S D S D

n-channel p-channel
open when voltage at G is low closed when voltage at G is low
closes when: opens when:
voltage(G) > voltage (S) +  voltage(G) < voltage (S) – 

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MOS networks Two input networks

X Y

3v
what is the
X what is the relationship
relationship between x, y and z?
between x and y? Z1
3v x y 0v x y z1 z2

Y 0 volts 3 volts X Y 0 volts 0 volts 3 volts 3 volts

0 volts 3 volts 3 volts 0 volts
0v 3 volts 0 volts
3v 3 volts 0 volts 3 volts 0 volts
Z2 3 volts 3 volts 0 volts 0 volts
NAND NOR
0v
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Speed of MOS networks Representation of digital designs

• What influences the speed of CMOS networks? • Physical devices (transistors, relays)
 charging and discharging of voltages on wires and gates of • Switches
transistors
• Truth tables
• Capacitors hold charge
• Boolean algebra
 capacitance is at gates of transistors and wire material
• Resistors slow movement of electrons • Gates scope of This Class

 resistance mostly due to transistors • Waveforms

• Finite state behavior
• Register-transfer behavior
• Concurrent abstract specifications

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Mapping from physical world to

Digital vs. analog
binary world
• Convenient to think of digital systems as having
only discrete, digital, input/output values Technology State 0 State 1
• In reality, real electronic components exhibit
continuous, analog, behavior Relay logic Circuit Open Circuit Closed
CMOS logic 0.0-1.0 volts 2.0-3.0 volts
Transistor transistor logic (TTL) 0.0-0.8 volts 2.0-5.0 volts
• Why do we make the digital abstraction anyway? Fiber Optics Light off Light on
Dynamic RAM Discharged capacitor Charged capacitor
 switches operate this way Nonvolatile memory (erasable) Trapped electrons No trapped electrons
 easier to think about a small number of discrete values Programmable ROM Fuse blown Fuse intact
• Why does it work? Bubble memory No magnetic bubble Bubble present
Magnetic disk No flux reversal Flux reversal
 does not propagate small errors in values Compact disc No pit Pit
 always resets to 0 or 1

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Combinational vs.
Logic gates
sequential digital circuits
X Y Z
• A simple model of a digital system is a unit with X 0 0 1
NAND Z 0
inputs and outputs: Y 1 1
1 0 1
X Y 1 1 0
NOT X Y 0 1
1 0
X Y Z
inputs system outputs X 0 0 1
X Y Z Z
0 0 0
NOR 0 1 0
X Y 1 0 0
AND Y Z 0 1 0 1 1 0
1 0 0
• Combinational means "memory-less" 1 1 1
 a digital circuit is combinational if its output values X Y Z
X Y Z X 0 0 0
only depend on its input values X 0 0 0 XOR Z 0 1 1
OR Z 0 1 1 Y
Y 1 0 1
1 0 1 1 1 0
1 1 1

X Y Z
X 0 0 1
XNOR Y Z 0 1 0
1 0 0
1 1 1
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Combinational logic symbols Sequential logic

• Common combinational logic systems have • Sequential systems

standard symbols called logic gates  exhibit behaviors (output values) that depend not only
on the current input values, but also on previous input values
 Buffer, NOT
A Z • In reality, all real circuits are sequential
 because the outputs do not change instantaneously after an input
change
 AND, NAND
 why not, and why is it then sequential?
A
Z easy to implement
B with CMOS transistors
(the switches we have • A fundamental abstraction of digital design is to
 OR, NOR available and use most) reason (mostly) about steady-state behaviors
A  look at the outputs only after sufficient time has elapsed for the
Z
B system to make its required changes and settle down

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Example of combinational and
An example
sequential logic
• Combinational: • Calendar subsystem: number of days in a month (to
 input A, B control watch display)
A
 wait for clock edge C  used in controlling the display of a wrist-watch LCD screen
 observe C B

 wait for another clock edge  inputs: month, leap year flag
 observe C again: will stay the same  outputs: number of days

• Sequential:
 input A, B A
 wait for clock edge C
B
 observe C
 wait for another clock edge
Clock
 observe C again: may be different

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Implementation as a
Implementation in software
combinational digital system
• Encoding:
integer number_of_days ( month, leap_year_flag) {  how many bits for each input/output?
switch (month) {  binary number for month
case 1: return (31);  four wires for 28, 29, 30, and 31 month leap d28 d29 d30 d31
0000 – – – – –
case 2: if (leap_year_flag == 1) then return (29) • Behavior: 0001 – 0 0 0 1
else return (28); 0010 0 1 0 0 0
 combinational
case 3: return (31); 0010 1 0 1 0 0
...  truth table 0011 – 0 0 0 1
specification 0100 – 0 0 1 0
case 12: return (31); 0101 – 0 0 0 1
default: return (0); month leap 0110 – 0 0 1 0
0111 – 0 0 0 1
} 1000 – 0 0 0 1
} 1001 – 0 0 1 0
1010 – 0 0 0 1
1011 – 0 0 1 0
1100 – 0 0 0 1
1101 – – – – –
111– – – – – –
d28 d29 d30 d31
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Combinational example (cont’d) Combinational example (cont’d)

• Truth-table to logic to switches to gates • d28 = m8'•m4'•m2•m1'•leap’

 d28 = 1 when month=0010 and leap=0 symbol • d29 = m8'•m4'•m2•m1'•leap
for not
 d28 = m8'•m4'•m2•m1'•leap'
• d30 = (m8'•m4•m2'•m1') + (m8'•m4•m2•m1') +
 d31 = 1 when month=0001 or month=0011 or ... month=1100
(m8•m4'•m2'•m1) + (m8•m4'•m2•m1)
 d31 = (m8'•m4'•m2'•m1) + (m8'•m4'•m2•m1) + ... (m8•m4•m2'•m1')
= (m8'•m4•m1') + (m8•m4'•m1)
 d31 = can we simplify more? • d31 = (m8'•m4'•m2'•m1) + (m8'•m4'•m2•m1) +
month leap d28 d29 d30 d31
0001 – 0 0 0 1 (m8'•m4•m2'•m1) + (m8'•m4•m2•m1) +
0010 0 1 0 0 0 (m8•m4'•m2'•m1') + (m8•m4'•m2•m1') +
0010 1 0 1 0 0
symbol symbol 0011 – 0 0 0 1 (m8•m4•m2'•m1')
for and for or 0100 – 0 0 1 0
...
1100 – 0 0 0 1
1101 – – – – –
111– – – – – –
0000 – – – – –

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Sequential example : Sequential example (cont’d):

finite-state machine encoding
• Finite-state machine • Encode state table
 generate state table (much like a truth-table)  state can be: S1, S2, S3, OPEN, or ERR
ERR
closed  needs at least 3 bits to encode: 000, 001, 010, 011, 100
not equal not equal not equal  and as many as 5: 00001, 00010, 00100, 01000, 10000
& new & new & new
S1 S2 S3 OPEN  choose 4 bits: 0001, 0010, 0100, 1000, 0000
reset closed closed closed open
mux=C1 equal mux=C2 equal mux=C3 equal
& new & new & new  output mux can be: C1, C2, or C3
next
not new not new not new  needs 2 to 3 bits to encode
reset new equal state state mux open/closed  choose 3 bits: 001, 010, 100
1 – – – S1 C1 closed
0 0 – S1 S1 C1 closed
 output open/closed can be: open or closed
0 1 0 S1 ERR – closed  needs 1 or 2 bits to encode
0 1 1 S1 S2 C2 closed  choose 1 bits: 1, 0
0 0 – S2 S2 C2 closed
0 1 0 S2 ERR – closed
0 1 1 S2 S3 C3 closed
0 0 – S3 S3 C3 closed
0 1 0 S3 ERR – closed
0 1 1 S3 OPEN – open
0 – – OPEN OPEN – open
0 – – ERR ERR – closed
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Sequential example (cont’d):
Summary
encoding
• That was what the entire course is about
 converting solutions to problems into combinational and sequential
networks effectively organizing the design hierarchically
next
reset new equal state state mux open/closed  doing so with a modern set of design tools that lets us handle large
1 – – – 0001 001 0
designs effectively
0 0 – 0001 0001 001 0
0 1 0 0001 0000 – 0 good choice of encoding!  taking advantage of optimization opportunities
0 1 1 0001 0010 010 0
0 0 – 0010 0010 010 0 mux is identical to
0 1 0 0010 0000 – 0 last 3 bits of state
0 1 1 0010 0100 100 0
0 0 – 0100 0100 100 0 open/closed is
0 1 0 0100 0000 – 0 identical to first bit
0 1 1 0100 1000 – 1 of state
0 – – 1000 1000 – 1
0 – – 0000 0000 – 0

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