Chapter 1

Introduction

These lecture notes are provided by Prentice Hall

accompanied with “Contemporary Logic Design” 2nd Ed.
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Why study logic design?

◼ it is the implementation basis for all modern computing

devices
❑ building large things from small components
❑ provide a model of how a computer works

◼ More important reasons

❑ the inherent parallelism in hardware is often our first exposure to
parallel computation
❑ it offers an interesting counterpoint to software design and is
therefore useful in furthering our understanding of computation, in
general

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What will we learn in this class? (1/2)

◼ The basics of logic design

❑ Boolean algebra, logic minimization, state, timing, CAD tools

◼ The concept of state in digital systems

❑ analogous to variables and program counters in software systems

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What will we learn in this class? (2/2)

◼ How to specify/simulate/compile/realize our designs

❑ hardware description languages (HDLs)
❑ tools to simulate the workings of our designs
❑ logic compilers to synthesize the hardware blocks of our designs
❑ mapping onto programmable hardware

◼ Contrast with software design

❑ sequential and parallel implementations
❑ specify algorithm as well as computing/storage resources it will use

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Applications of logic design

◼ Conventional computer design

❑ CPUs, busses, peripherals

◼ Networking and communications

❑ phones, modems, routers

◼ Embedded products
❑ in cars, toys, appliances, entertainment devices

◼ Scientific equipment
❑ testing, sensing, reporting

◼ The world of computing is much bigger than just PCs!

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Global processor/controller market

PC CPUs constitute less than 2% of the market

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What is logic design? (1/2)
◼ Logic design is to design digital hardware
❑ Digital hardware consists of components

◼ Components or building blocks

❑ Switches built from semiconductor transistors
• Most basic element
❑ Higher level circuits such as logic gates and memories

◼ A logic designer should choose the right component to

solve logic design problems

◼ Constraints: size, cost, performance, power

consumption
❑ Cost vs. size
* A circuit is an interconnected collection of switches
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What is logic design? (2/2)

◼ Each component has

❑ a set of input wires
❑ a set of output wires
❑ Each wire is set to some analog voltage value
• But will be interpreted as either 1 or 0 (digital abstraction)

◼ Transistors react to the voltage levels on the input wires

❑ Switch their state and cause a change in output wires
❑ At macro scale, a component that contains transistors reacts to
input voltage values

◼ Depending on the way a circuit reacts to the input

voltages
❑ Combinational logic circuits
❑ Sequential logic circuits
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What is digital hardware?

◼ Collection of devices that sense and/or control wires,

which carry a digital value (i.e., a physical quantity that
can be interpreted as a “0” or “1”)
❑ example: digital logic where voltage < 0.8v is a “0” and > 2.0v is a “1”

◼ Primitive digital hardware devices

❑ logic computation devices (sense and drive)
• are two wires both “1” - make another be “1” (AND)
• is at least one of two wires “1” - make another be “1” (OR)
• is a wire “1” - then make another be “0” (NOT)
❑ memory devices (store) sense
• store a value
• recall a previously stored value AND drive

sense 9
Computation: abstract vs. implementation

◼ Computation has been a mental exercise (paper, programs)

◼ This class is about physically implementing computation using
physical devices that use voltages to represent logical values
◼ Basic units of computation are:
❑ representation: "0", "1" on a wire
set of wires (e.g., binary integer)
❑ assignment: x = y
❑ data operations: x+y–5
❑ control:

sequential statements: A; B; C
conditionals: if x == 1 then y
loops: for ( i = 1 ; i == 10, i++)
procedures: A; proc(...); B;
◼ We will study how each of these are implemented in hardware
and composed into computational structures
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Switches: basic element of physical
implementations
◼ Implementing a simple circuit

A Z
close switch (if A is “1” or asserted)
and turn on light bulb (Z)

Z
A
open switch (if A is “0” or unasserted)
and turn off light bulb (Z)

Z  A

Z and A are equivalent boolean variables

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Switches (cont’d)

◼ Compose switches into more complex ones (Boolean

functions):

A B
AND
Z  A and B

A
OR
Z  A or B

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Switching networks

◼ Switch settings
❑ determine whether or not a conducting path exists to light
the light bulb
◼ To build larger computations
❑ use a light bulb (output of the network) to set other switches
(inputs to another network).
◼ Connect together switching networks
❑ to construct larger switching networks, i.e., there is a way to
connect outputs of one network to the inputs of the next.

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A switch?

◼ A mechanical switch

◼ A semiconductor switch or transistor

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Transistor networks

◼ Modern digital systems are designed in CMOS

technology
❑ MOS stands for Metal-Oxide on Semiconductor
❑ C is for complementary because there are both normally-open
and normally-closed switches: nMOS and pMOS
◼ MOS transistors act as voltage-controlled switches

* CMOS: complementary metal-oxide semiconductor

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n-channel (or n-type) MOS (nMOS) circuit

◼ Three terminals: source-gate-drain (or S-G-D for short)

◼ Three layers: polysilicon (used to be metal) – SiO2 - substrate
Source Gate Drain
Polysilicon
SiO2

n+ n+

p bulk Si

◼ If G is at positive voltage, electrons in the substrate will move

toward G terminal, which sets up a channel between S and D
❑ And D is at high voltage, current will flow from drain to source
◼ Metal is replaced by polysilicon which is more adhesive
* n+: heavily doped n-type semiconductor 16
p-channel (or p-type) MOS (pMOS) circuit

◼ Three terminals: source-gate-drain (or S-G-D for short)

◼ Same principle, but reverse doping and voltage
❑ Source (Vss) is positive with regard to drain (Vdd)
◼ Bubble indicates the inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

◼ If G is at positive voltage, the current does not flow

◼ If G is at ground level, the current flows

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MOS transistors

◼ MOS transistors have three terminals: drain, gate, and

source
❑ they act as switches in the following way:
if the voltage on the gate terminal is (some amount) higher/lower
than the source terminal, then a conducting path will be
established between the drain and source terminals
G G

S D S D

n-channel p-channel
open when voltage at G is low closed when voltage at G is low
closed when voltage at G is high open when voltage at G is high

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MOS networks

X what is the
relationship
between x and y?
3v x y

Y 0 volts 3 volts

0v 3 volts 0 volts

◼ A simple component is made up of two transistors

❑ X: input
❑ Y: output
❑ What is this function?
◼ In CMOS circuits, pMos and nMOS are used in pair
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Two input networks

X Y

3v What is the relationship

between x, y and z1/z2?
Z1 x y z1 z2

0v 0 volts 0 volts 3 volts 3 volts

0 volts 3 volts 3 volts 0 volts
X Y
3 volts 0 volts 3 volts 0 volts
3v 3 volts 3 volts 0 volts 0 volts
NAND NOR
Z2

0v
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Three input NAND gate

◼ Y pulls low if ALL inputs are 1

VDD
◼ Y pulls high if ANY input is 0
Y
A
B
C

◼ In general, the more inputs, the more transistors (TRs)

◼ In CMOS, a variable requires a pair of TRs

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Digital vs. analog

◼ Convenient to think of digital systems as having only

discrete, digital, input/output values
◼ In reality, real electronic components exhibit
continuous, analog behavior
◼ Why do we make the digital abstraction anyway?
❑ switches operate this way
❑ easier to think about a small number of discrete values
❑ Quantization error, though
◼ Why does it work?
❑ does not propagate small errors in values
❑ always resets to 0 or 1

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Combinational logic symbols

◼ Common combinational logic systems have standard

symbols called logic gates
❑ Buffer, NOT

A Z

❑ AND, NAND
A
Z easy to implement
B with CMOS transistors
(the switches we have
❑ OR, NOR available and use most)
A
Z
B

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Combinational vs. sequential digital circuits

◼ A simple model of a digital system is a unit with inputs

and outputs:

inputs system outputs

◼ Combinational means "memory-less"

❑ a digital circuit is combinational if its output values
only depend on its (current) input values

◼ Sequential systems
❑ exhibit behaviors (output values) that depend not only
on the current input values, but also on previous input values

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Combinational vs. sequential digital circuits

In Out
Logic Logic
In Out
Circuit Circuit

State

(a) Combinational (b) Sequential

Output = f(In) Output = f(In, Previous In)

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Example of combinational and sequential logic

◼ Combinational:
❑ input A, B
❑ wait for clock edge
A
❑ observe C C
B
❑ wait for another clock edge
❑ observe C again: will stay the same Clock

◼ Sequential:
❑ input A, B
❑ wait for clock edge
❑ observe C
❑ wait for another clock edge
❑ observe C again: may be different

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Intermediate Summary
◼ Some we've seen already
❑ digital interpretation of analog values
❑ transistors as switches
❑ switches as logic gates
❑ use of a clock to realize a synchronous sequential circuit
◼ Some others we will see
❑ truth tables and Boolean algebra to represent combinational logic
❑ encoding of signals with more than two logical values into
binary form
❑ state diagrams to represent sequential logic
❑ hardware description languages to represent digital logic
❑ waveforms to represent temporal behavior

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An example

◼ Calendar subsystem: number of days in a month (to

control watch display)
❑ Combinational logic

❑ used in controlling the display of a wrist-watch LCD screen

❑ inputs: month, leap year flag

❑ outputs: number of days

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Implementation in software

integer number_of_days ( month, leap_year_flag)

{
switch (month) {
case 1: return (31);
case 2: if (leap_year_flag == 1) then return (29)
else return (28);
case 3: return (31);
...
case 12: return (31);
default: return (0);
}
}

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Implementation as a combinational digital system
◼ Encoding:
❑ how many bits for each input/output?
Don’t
❑ binary number for month care
❑ four wires for 28, 29, 30, and 31
month leap d28 d29 d30 d31
◼ Behavior: 0000 – – – – –
0001 – 0 0 0 1
❑ combinational 0010 0 1 0 0 0
0010 1 0 1 0 0
❑ truth table 0011 – 0 0 0 1
0100 – 0 0 1 0
specification month leap 0101 – 0 0 0 1
0110 – 0 0 1 0
0111 – 0 0 0 1
1000 – 0 0 0 1
1001 – 0 0 1 0
1010 – 0 0 0 1
1011 – 0 0 1 0
1100 – 0 0 0 1
1101 – – – – –
d28 d29 d30 d31 111– – – – – –

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Combinational example (cont’d)

◼ Truth-table to logic to switches to gates

❑ d28 = 1 when month=0010 and leap=0
symbol
❑ d28 = m8'•m4'•m2•m1'•leap' for not

❑ d31 = 1 when month=0001 or month=0011 or ... month=1100

❑ d31 = (m8'•m4'•m2'•m1) + (m8'•m4'•m2•m1) + ... (m8•m4•m2'•m1')
❑ d31 = can we simplify more? month leap d28 d29 d30 d31
0001 – 0 0 0 1
0010 0 1 0 0 0
0010 1 0 1 0 0
symbol symbol 0011 – 0 0 0 1
for and for or 0100 – 0 0 1 0
...
1100 – 0 0 0 1
1101 – – – – –
111– – – – – –
0000 – – – – –
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Combinational example (cont’d)
◼ d28 = m8'•m4'•m2•m1'•leap’
◼ d29 = m8'•m4'•m2•m1'•leap
◼ d30 = (m8'•m4•m2'•m1') + (m8'•m4•m2•m1') +
(m8•m4'•m2'•m1) + (m8•m4'•m2•m1)
= (m8'•m4•m1') + (m8•m4'•m1)
◼ d31 = (m8'•m4'•m2'•m1) + (m8'•m4'•m2•m1) +
(m8'•m4•m2'•m1) + (m8'•m4•m2•m1) +
(m8•m4'•m2'•m1') + (m8•m4'•m2•m1') +
(m8•m4•m2'•m1')

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Combinational example (cont’d)
◼ d28 = m8'•m4'•m2•m1'•leap’
◼ d29 = m8'•m4'•m2•m1'•leap
◼ d30 = (m8'•m4•m2'•m1') + (m8'•m4•m2•m1') +
(m8•m4'•m2'•m1) + (m8•m4'•m2•m1)
◼ d31 = (m8'•m4'•m2'•m1) + (m8'•m4'•m2•m1) +
(m8'•m4•m2'•m1) + (m8'•m4•m2•m1) +
(m8•m4'•m2'•m1') + (m8•m4'•m2•m1') +
(m8•m4•m2'•m1')

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Summary of Combinational Circuit Design

◼ Step 1: Block Diagram (Specify Inputs and Outputs)

◼ Step 2: Truth Table

◼ Step 3: Implementation

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Another example (Door combination lock)

◼ punch in 3 values in sequence and the door opens; if

there is an error the lock must be reset; once the door
opens the lock must be reset
❑ Sequential logic

❑ inputs: sequence of input values, reset

• Numeric number: 4 wires

❑ outputs: door open/close

❑ memory: must remember combination

or always have it available as an input

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Implementation in software

integer combination_lock ( ) {
integer v1, v2, v3;
integer error = 0;
static integer c[3] = 3, 4, 2;

while (!new_value( ));

v1 = read_value( );
if (v1 != c[1]) then error = 1; Array index starts from 1
while (!new_value( ));
v2 = read_value( );
if (v2 != c[2]) then error = 1;

while (!new_value( ));

v3 = read_value( );
if (v2 != c[3]) then error = 1;

if (error == 1) then return(0); else return (1);

}

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Implementation as a sequential digital system
new value reset

◼ Encoding:
❑ how many bits per input value? state
clock
❑ how many values in sequence?
❑ how do we know a new input value is entered?
open/closed
❑ how do we represent the states of the system?
◼ Behavior:
❑ clock wire tells us when it’s ok
to look at inputs
(i.e., they have settled after change)
❑ sequential: sequence of values
must be entered
❑ sequential: remember if an error occurred
❑ finite-state specification

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Sequential example (cont’d): abstract control

◼ Finite-state diagram
❑ states: 5 states
• represent point in execution of machine
• each state has inputs and outputs
❑ transitions: 6 from state to state, 5 self transitions, 1 global
• changes of state occur when clock says it’s ok
ERR
• based on value of inputs
closed
❑ inputs: reset, new, results of comparisons
❑ output: open/closed C1!=value
C2!=value C3!=value
& new
& new & new
S1 S2 S3 OPEN
reset closed closed closed open
C1=value C2=value C3=value
& new & new & new

not new not new not new

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Sequential example (cont’d): data-path vs. control

◼ Internal structure
❑ data-path ❑ control
• storage for combination • finite-state machine controller
• comparators • control for data-path
• state changes controlled by clock

new equal reset

value
C1 C2 C3
multiplexer
mux
controller
control
clock
comparator

equal open/closed

* Multiplexer (MUX)

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Sequential example (cont’d): FSM

◼ Finite-state machine (FSM)

❑ refine state diagram to include internal structure

ERR
closed

not equal not equal

& new not equal
& new & new
S1 S2 S3 OPEN
closed closed closed
reset open
mux=C1 equal mux=C2 equal mux=C3 equal
& new & new & new

not new not new not new

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Sequential example (cont’d): FSM
ERR
◼ Finite-state machine closed

❑ generate state table (much like a truth-table) not equal not equal not equal
& new & new & new
S1 S2 S3 OPEN
closed closed closed
reset open
mux=C1 equal mux=C2 equal mux=C3 equal
& new & new & new

not new not new not new

next
reset new equal state state mux open/closed
1 – – – S1 C1 closed
0 0 – S1 S1 C1 closed
0 1 0 S1 ERR – closed
0 1 1 S1 S2 C2 closed
0 0 – S2 S2 C2 closed
0 1 0 S2 ERR – closed
0 1 1 S2 S3 C3 closed
0 0 – S3 S3 C3 closed
0 1 0 S3 ERR – closed
0 1 1 S3 OPEN – open
0 – – OPEN OPEN – open
0 – – ERR ERR – closed

* state is not input, but internal variable

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Sequential example (cont’d): encoding
◼ Encode state table
❑ state can be: S1, S2, S3, OPEN, or ERR
• needs at least 3 bits to encode: 000, 001, 010, 011, 100
• and as many as 5: 00001, 00010, 00100, 01000, 10000
• choose 4 bits: 0001, 0010, 0100, 1000, 0000
❑ output mux can be: C1, C2, or C3
• needs 2 to 3 bits to encode
• choose 3 bits: 001, 010, 100
❑ output open/closed can be: open or closed
• needs 1 or 2 bits to encode
• choose 1 bits: 1, 0

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 Sequential example (cont’d): encoding
◼ Encode state table
❑ state can be: S1, S2, S3, OPEN, or ERR
• choose 4 bits: 0001, 0010, 0100, 1000, 0000 Internal
input
❑ output mux can be: C1, C2, or C3 system’s
• choose 3 bits: 001, 010, 100 Internal or external
❑ output open/closed can be: open or closed output output
• choose 1 bits: 1, 0
next
reset new equal state state mux open/closed
1 – – – 0001 001 0
external 0 0 – 0001 0001 001 0
input 0 1 0 0001 0000 – 0 good choice of encoding!
0 1 1 0001 0010 010 0
0 0 – 0010 0010 010 0 mux is identical to
0 1 0 0010 0000 – 0 last 3 bits of next state
0 1 1 0010 0100 100 0
0 0 – 0100 0100 100 0 open/closed is
0 1 0 0100 0000 – 0 identical to first bit
0 1 1 0100 1000 – 1 of next state
0 – – 1000 1000 – 1
0 – – 0000 0000 – 0
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Sequential example (cont’d): controller
implementation
◼ Implementation of the controller
special circuit element, called a register, for

new equal reset remembering inputs when told to by clock

mux
control controller new equal reset
clock
mux
comb. logic
open/closed control
state clock

open/closed

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Sequential Circuit Design hierarchy

system

data-path control

code multiplexer comparator state combinational

registers registers logic

register logic

switching
networks

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Summary of Sequential Circuit Design

◼ Step 1: Block diagram (Specify Inputs and Outputs)

◼ Step 2: State diagram

◼ Step 3: Decomposition into data part and control part

◼ Step 4: FSM for control part

◼ Step 5: Implementation

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Terminologies

SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

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Summary

◼ That was what the entire course is about

❑ converting solutions for problems into combinational and
sequential networks effectively organizing the design
hierarchically

❑ doing so with a modern set of design tools that lets us handle

large designs effectively

❑ taking advantage of optimization opportunities

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